Patent application number | Description | Published |
20100150359 | Methods and Systems for Improved Acoustic Environment Characterization - In embodiments of the present invention improved capabilities are described for determining a multi-dimensional sound signature for a location within a hypothetical space, comparing the multi-dimensional sound signature to a known multi-dimensional sound signature, and modifying the hypothetical space such that the similarity between the multi-dimensional sound signature for the location within the modified hypothetical space and the known multi-dimensional sound signature is increased. | 06-17-2010 |
20130208904 | METHODS AND SYSTEMS FOR IMPROVED ACOUSTIC ENVIRONMENT CHARACTERIZATION - In embodiments of the present invention improved capabilities are described for determining a multi-dimensional sound signature for a location within a hypothetical space, comparing the multi-dimensional sound signature to a known multi-dimensional sound signature, and modifying the hypothetical space such that the similarity between the multi-dimensional sound signature for the location within the modified hypothetical space and the known multi-dimensional sound signature is increased. | 08-15-2013 |
20150286966 | UTILIZING A MEASURED ACOUSTIC PROFILE FROM A SOUND SPACE TO PROVIDE A TICKET BUYER WITH A SOUND CHARACTERISTIC MEASURE FOR DIFFERENT SEATS WITHIN THE SOUND SPACE - In embodiments of the present invention improved capabilities are described for generating and accessing a computer stored multi-dimensional sound profile for a plurality of seat locations within a space, the multi-dimensional sound profile comprising a plurality of multi-dimensional sound signatures, wherein each multi-dimensional sound signature comprises a time-based sound reflection sequence for a corresponding seat location of the plurality of seat locations within the space. A ticket purchase selection option may be provided to a user, wherein the ticket purchase selection option relates a seat location to a corresponding sound characteristic for the seat location based upon the accessed multi-dimensional sound profile for the plurality of seat locations within the space. | 10-08-2015 |
20150289071 | REPRODUCING AN ACOUSTIC ENVIRONMENT FROM A FIRST SPACE IN A SECOND SPACE WHEN THE ACOUSTIC SOURCE IN THE SECOND SPACE IS A MEDIA DEVICE - In embodiments of the present invention, methods for reproducing an acoustic environment are described, which may include accessing a computer stored multi-dimensional sound profile of a first space, measuring a multi-dimensional sound profile in a second space, comparing multi-dimensional sound profile of the first space and the multi-dimensional sound profile of the second space, accessing the sound characteristics of an audio output device that will serve as the audio output device in the second space, and modifying the audio output of a media content of the audio output device taking into account the sound characteristics of the audio output device, wherein the modifying reduces the difference as determined in the comparing between the multi-dimensional sound profile of the first space and the multi-dimensional sound profile of the second space as output by the audio output device. | 10-08-2015 |
Patent application number | Description | Published |
20110138817 | METHOD OF INCREASING THE SAFETY OF A POWER PLANT, AND A POWER PLANT SUITABLE FOR IMPLEMENTING THE METHOD - The present invention relates to a method of increasing the safety of a power plant ( | 06-16-2011 |
20120253560 | METHOD AND A DEVICE FOR ASSISTING THE PILOTING OF AN AIRCRAFT, AND AN AIRCRAFT - A method of assisting the piloting of an aircraft ( | 10-04-2012 |
20130184903 | AIRCRAFT POWER PLANT, AN AIRCRAFT, AND A METHOD OF PILOTING SAID AIRCRAFT - An aircraft power plant ( | 07-18-2013 |
20130184958 | METHOD OF CONTROLLING A GROUP OF ENGINES, AND AN AIRCRAFT - A method of controlling a group ( | 07-18-2013 |
20130199198 | METHOD OF AUTOMATICALLY REGULATING AN AIRCRAFT POWER PLANT, A DEVICE, AND AN AIRCRAFT - A method of automatically regulating a power plant ( | 08-08-2013 |
20140020396 | METHOD OF AUTOMATICALLY REGULATING AN AIRCRAFT POWER PLANT, A DEVICE, AND AN AIRCRAFT - The present invention relates to an automatic method of regulating a power plant ( | 01-23-2014 |
20140200844 | METHOD OF OPTIMIZING THE PERFORMANCE OF AN AIRCRAFT, A DEVICE, AND AN AIRCRAFT - A method of optimizing the performance of a rotary wing aircraft having at least one turbine engine with a gas generator and a turbine assembly comprising at least one turbine. In a definition step (STP | 07-17-2014 |
Patent application number | Description | Published |
20120288676 | METHOD FOR STRUCTURING A SURFACE BY MEANS OF ION-BEAM ETCHING, STRUCTURED SURFACE AND USES - A process for forming an array of irregularities or features that are submicron-size in height and that have a characteristic lateral dimension that is micron- or submicron-size, over a surface of a material, by ion erosion, the process including: supplying the material with a thickness at least equal to 100 nm, the material being a solid hybrid material that includes: a simple oxide or a mixed oxide of one or more elements, an oxide molar percentage in the material being at least 40%; and a species, of a different nature to the one or more elements of the oxide, a molar percentage of the species in the material ranging from 6 mol % up to 50 mol % while remaining below the percentage of the oxide, most of the species having a largest characteristic dimension smaller than 50 nm, optionally heating the hybrid material before the erosion; structuring the surface of the hybrid material with an erosion that lasts less than one hour over an erosion area greater than 1 cm | 11-15-2012 |
20120288681 | METHOD FOR STRUCTURING A SURFACE BY MEANS OF REACTIVE ION-BEAM ETCHING, STRUCTURED SURFACE AND USES - A process for forming an array of irregularities or features that are submicron-size in height and that have a characteristic lateral dimension that is micron- or submicron-size, over a surface of a material by reactive-ion etching, the process including: supplying the material with a thickness at least equal to 100 nm, the material being a solid hybrid material that includes: a simple silicon oxide or a mixed silicon oxide, most of the oxides in the case of a mixed oxide being silicon oxide, an oxide molar percentage in the material being at least 40%; and a species, of a different nature to the silicon of the oxide, a molar percentage of the species in the material ranging from 1 mol % or even up to 50 mol % while remaining below the percentage of the silicon oxide, at least most of the species having a largest characteristic dimension smaller than 50 nm, optionally heating the hybrid material before the etching; structuring the surface of the hybrid material, without masking, with etching that lasts less than 30 minutes over an etching area greater than 1 cm | 11-15-2012 |
20150099079 | TUBE MADE OF HYDROPHILIZED SILICONE - The invention relates to a process for the production of a piece made of silicone including: (a) the blending of 100 parts by weight of an HCR silicone base having a viscosity of greater than 10 | 04-09-2015 |
20150330383 | MEMBRANE PUMP - A pump comprising a pump body defining a circulation space for circulation of fluid according to a direction of circulation from an entry orifice of the circulation space to an output orifice of the circulation space; a membrane retained in the circulation space substantially parallel to the direction of circulation; and an actuating device adapted to vibrate the membrane in a direction substantially perpendicular to the direction of circulation, wherein the membrane comprises a material or a protective coating having a polymer organic matrix with a Young's modulus in a range of between 100 MPa and 10 GPa. | 11-19-2015 |
Patent application number | Description | Published |
20140117417 | PERFORMANCE ENHANCEMENT IN TRANSISTORS BY PROVIDING A GRADED EMBEDDED STRAIN-INDUCING SEMICONDUCTOR REGION WITH ADAPTED ANGLES WITH RESPECT TO THE SUBSTRATE SURFACE - In sophisticated semiconductor devices, transistors may be formed on the basis of an efficient strain-inducing mechanism by using an embedded strain-inducing semiconductor alloy. The strain-inducing semiconductor material may be provided as a graded material with a smooth strain transfer into the neighboring channel region in order to reduce the number of lattice defects and provide enhanced strain conditions, which in turn directly translate into superior transistor performance. The superior architecture of the graded strain-inducing semiconductor material may be accomplished by selecting appropriate process parameters during the selective epitaxial growth process without contributing to additional process complexity. | 05-01-2014 |
20140264349 | LOW THERMAL BUDGET SCHEMES IN SEMICONDUCTOR DEVICE FABRICATION - In aspects of the present invention, a method of forming a semiconductor device is disclosed, wherein amorphous regions are formed at an early stage during fabrication and the amorphous regions are conserved during subsequent processing sequences, and an intermediate semiconductor device structure with amorphous regions are provided at an early stage during fabrication. Herein a gate structure is provided over a semiconductor substrate and amorphous regions are formed adjacent the gate structure. Source/drain extension regions or source/drain regions are formed in the amorphous regions. In some illustrative embodiments, fluorine may be implanted into the amorphous regions. After the source/drain extension regions and/or the source/drain regions are formed, a rapid thermal anneal process is performed. | 09-18-2014 |
20140264626 | METHOD FOR FORMING A GATE ELECTRODE OF A SEMICONDUCTOR DEVICE, GATE ELECTRODE STRUCTURE FOR A SEMICONDUCTOR DEVICE AND ACCORDING SEMICONDUCTOR DEVICE STRUCTURE - The present disclosure provides, in some aspects, a gate electrode structure for a semiconductor device. In some illustrative embodiments herein, the gate electrode structure includes a first high-k dielectric layer over a first active region of a semiconductor substrate and a second high-k dielectric layer on the first high-k dielectric layer. The first high-k dielectric layer has a metal species incorporated therein for adjusting the work function of the first high-k dielectric layer. | 09-18-2014 |
20140361385 | METHOD OF FORMING A SEMICONDUCTOR DEVICE STRUCTURE EMPLOYING FLUORINE DOPING AND ACCORDING SEMICONDUCTOR DEVICE STRUCTURE - Methods of forming a semiconductor device structure at advanced technology nodes and respective semiconductor device structures are provided at advanced technology nodes, i.e., smaller than 100 nm. In some illustrative embodiments, a fluorine implantation process for implanting fluorine at least into a polysilicon layer formed over a dielectric layer structure is performed prior to patterning the gate dielectric layer structure and the polysilicon layer for forming a gate structure and implanting source and drain regions at opposing sides of the gate structure. | 12-11-2014 |
20150145000 | INTEGRATED CIRCUITS WITH SHALLOW TRENCH ISOLATIONS, AND METHODS FOR PRODUCING THE SAME - Integrated circuits with electrical components near shallow trench isolations and methods for producing such integrated circuits are provided. The method includes forming a trench is a substrate, where the trench has a trench surface. A barrier layer including silicon and germanium is formed overlying the trench surface. A shallow trench isolation is then formed with a core overlying the barrier layer, where the core includes a shallow trench isolation insulator. | 05-28-2015 |
20150187909 | METHODS FOR FABRICATING MULTIPLE-GATE INTEGRATED CIRCUITS - A method for fabricating an integrated circuit includes providing a silicon semiconductor substrate including a single-crystal crystallography, removing a portion of the semiconductor substrate to form a fin structure, the fin structure being defined by adjacent trenches formed within the semiconductor substrate, and forming an insulating material in the trenches, the insulating material covering a first portion of the fin and leaving a second portion of the fin exposed. The method further includes applying a wet etchant to the second portion of the fin, the wet etchant including an etching chemistry that selectively etches the fin against a <111> crystallographic orientation of the single-crystal silicon. | 07-02-2015 |
20150243787 | METHOD FOR A UNIFORM COMPRESSIVE STRAIN LAYER AND DEVICE THEREOF - A methodology for forming a compressive strain layer with increased thickness that exhibits improved device performance and the resulting device are disclosed. Embodiments may include forming a recess in a source or drain region of a substrate, implanting a high-dose impurity in a surface of the recess, and depositing a silicon-germanium (SiGe) layer in the recess. | 08-27-2015 |
20150287646 | METHODS FOR FABRICATING INTEGRATED CIRCUITS WITH IMPROVED IMPLANTATION PROCESSES - Methods for fabricating integrated circuits are provided. In an embodiment, a method for fabricating an integrated circuit includes providing a structure having an n-channel gate stack and a p-channel gate stack formed over a semiconductor substrate. The method includes forming halo implant regions in the semiconductor substrate adjacent the p-channel gate stack and forming extension implant regions in the semiconductor substrate adjacent the p-channel gate stack. The method further includes annealing the halo implant regions and the extension implant regions in the semiconductor substrate adjacent the p-channel gate stack by performing a laser anneal process. Also, the method forms extension implant regions in the semiconductor substrate adjacent the n-channel gate stack. | 10-08-2015 |