Gunwani
Manoj Gunwani, Bangalore IN
Patent application number | Description | Published |
---|---|---|
20110058431 | METHOD AND APPARATUS FOR COMPRESSION OF CONFIGURATION BITSTREAM OF FIELD PROGRAMMABLE LOGIC - A memory is disclosed that can be utilized with a field programmable gate array. In some embodiments, the memory can include a memory array comprising a plurality of memory banks, each memory bank including at least one memory block, each of the at least one memory block including an array of memory cells; an address decoder coupled to each of the at least one memory block, the address decoder including a comparator coupled to receive an input address and a block address and provide a compare bit that indicates when a portion of the input address matches the block address, and an OR gate coupled to receive the compare bit and a wildcard bit, the OR gate providing an enable to the memory block when either the compare bit or the wildcard bit is asserted; and a logic unit that receives a mode value and the input address and provides the wildcard bit to each of the address decoders. Data can be simultaneously written into the memory array in patterns in accordance with the mode value. For example, in some embodiments the mode value indicates one of four patterns, a normal pattern, a block checkerboard pattern, a bank checkerboard pattern, and an all banks pattern. | 03-10-2011 |
20110225222 | METHODS AND APPARATUSES FOR CORDIC PROCESSING - A CORDIC engine includes an N-stage CORDIC processor for performing N micro-iterations of a CORDIC algorithm and generating a 3-vector CORDIC output responsive to a 3-vector CORDIC input. A counter counts a number of M macro-iterations for the CORDIC algorithm and indicates a start of the cycle iterations. A multiplexer selects an input to the N-stage CORDIC processor as the 3-vector CORDIC input at the start of the cycle iterations or the 3-vector CORDIC output at other times. The CORDIC algorithm is complete after N*M clock cycles by generating N micro-iterations for each of the M macro-iterations. In some embodiments, the CORDIC engine is coupled to programmable logic blocks as part of a programmable logic array. | 09-15-2011 |
20110231463 | METHODS AND APPARATUSES FOR FLEXIBLE AND HIGH PERFORMANCE DIGITAL SIGNAL PROCESSING - A Signal Processing Engine (SPE) includes circuitry for generating a selectable forward tap and a selectable reverse tap from a forward delay chain and a reverse delay chain, respectively. An add/subtract unit arithmetically combines the selectable forward tap and the selectable reverse tap to generate an intermediate output. A multiplier combines the intermediate output and a coefficient output from a circular coefficient buffer to generate a multiply result. Another adder/subtractor combines the multiply result with a second term including a processed input or an accumulator feedback by bypassing, adding, or subtracting the second term with the multiply result to generate an accumulator output. The accumulator output may be delayed a programmable number of clock cycles to generate a processed output. In some embodiments, the SPE is coupled to programmable logic blocks forming a programmable logic array through a programmable SPE routing block. | 09-22-2011 |
Manoj Gunwani, San Jose, CA US
Patent application number | Description | Published |
---|---|---|
20110010406 | Programmable Logic Systems and Methods Employing Configurable Floating Point Units - A programmable system is disclosed having multiple configurable floating point units (“FPU”) that are coupled to multiple programmable logic and routing blocks and multiple memories. Each floating point unit has static configuration blocks and dynamic configuration blocks, where the dynamic configuration blocks can be reconfigured to perform a different floating point unit function. A floating point unit includes a pre-normalization for shifting an exponent calculation as well as shifting and aligning a mantissa, and a post-normalization for normalizing and rounding a received input. The post-normalization receives an input Z and realigns the input, normalizes the input and rounds the input Z. | 01-13-2011 |
Manoj Gunwani, Vallejo, CA US
Patent application number | Description | Published |
---|---|---|
20090160483 | Field programmable application specific integrated circuit with programmable logic array and method of designing and programming the programmable logic array - A programmable logic array for use in a field programmable application specific integrated circuit (ASIC) implementation is provided. The programmable logic array includes programmable logic blocks, and programmable logic interfaces. The programmable logic interfaces couple the programmable logic blocks to external interfaces of the field programmable ASIC, and enable the programmable logic array to be inserted into the field programmable ASIC as a hard macro block. | 06-25-2009 |