Patent application number | Description | Published |
20120103602 | Systems, Methods, and Devices for Tagging Carbon Dioxide Stored in Geological Formations - Methods and systems for tagging carbon dioxide to be stored in a geologic formation are disclosed. In some embodiments, a method includes: providing a carbon dioxide tracer that is quantifiable and distinguishable versus non-anthropogenic produced carbon dioxide; providing carbon dioxide to be stored in the geologic formation; determining what portion of the carbon dioxide is anthropogenic produced carbon dioxide; and mixing a predetermined quantity of the carbon dioxide tracer with the carbon dioxide stored to develop a tagged quantity of carbon dioxide for storage in the geologic formation. In some embodiments, a system for tagging a stream of carbon dioxide includes a tagging module and a mixing module. Tagging module includes a carbon dioxide tracer that is quantifiable and distinguishable versus non-anthropogenic produced carbon dioxide. Mixing module includes mechanisms for containing and injecting the carbon dioxide tracer into a stream of carbon dioxide. | 05-03-2012 |
20120225007 | Methods and Systems for Synthesizing Iron-Based Materials and Sequestering Carbon Dioxide - Methods and systems for sequestering carbon dioxide and generating hydrogen are disclosed. In some embodiments, the methods include the following: dissolving an iron based material that includes a carbonate-forming element into a solution including the carbonate-forming element and iron; increasing a pH of the solution to cause precipitation of iron oxide from the solution thereby generating a first source of Fe | 09-06-2012 |
20130193040 | SYSTEMS FOR AUTOMATED CAPTURE AND RECOVERY OF OIL FROM OIL-CONTAMINATED WATER AND SOLIDS - Systems for automated capture and recovery of oil from oil-contaminated water and solids are disclosed. In some embodiments, the systems include the following: a plurality of automated robotic oil recovery units; a plurality of deployable oil collection membranes positioned within each of the units, each of the membranes including an upper half including a material impermeable to both water and crude oil and a lower half including a semi-permeable hydrophilic membrane that is permeable to water but impermeable to crude oil; and a high pressure carbon dioxide oil solids separation unit for separating oil from oil-contaminated solids thereby producing substantially oil-free solids and an oil and carbon dioxide mixture; a solids separation unit for the separating substantially oil-free solids from the oil and carbon dioxide mixture via gravity separation; and an oil separation unit for separating oil from the oil and carbon dioxide mixture using a pressure swing. | 08-01-2013 |
20130209339 | Methods And Systems For Producing Hydrogen And Capturing Carbon Dioxide - Methods and systems for producing hydrogen and capturing carbon dioxide are disclosed. In some embodiments, the methods include the following: mixing magnesium bearing minerals with one or more acids and/or chelating agents to form a magnesium-rich solvent including magnesium hydroxide; mixing a gas including carbon dioxide with the magnesium-rich solvent in a reactor possibly in the presence of one or more water-gas shift catalysts; increasing a temperature and a steam pressure inside the reactor until a substantial portion of the magnesium hydroxide in the solvent and the carbon dioxide and water in the gas react to form magnesium carbonate and hydrogen; and increasing pH in the reactor thereby increasing a rate that the solvent and the carbon dioxide react. | 08-15-2013 |
20150014182 | Methods and Systems for Capturing Carbon Dioxide and Producing a Fuel Using a Solvent Including a Nanoparticle Organic Hybrid Material and a Secondary Fluid - Methods and systems for capturing carbon dioxide and producing fuels such as alcohol using a solvent including a nanoparticle organic hybrid material and a secondary fluid are disclosed. In some embodiments, the methods include the following: providing a solvent including a nanoparticle organic hybrid material and a secondary fluid, the material being configured to capture carbon dioxide; introducing a gas including carbon dioxide to the solvent until the material is loaded with carbon dioxide; introducing at least one of catalysts for carbon dioxide reduction and a proton source to the solvent; heating the solvent including the material loaded with carbon dioxide until carbon dioxide loaded on the material is electrochemically converted to a fuel. | 01-15-2015 |
20150033812 | Methods and Systems for the Co-Generation of Gaseous Fuels, Biochar, and Fertilizer From Biomass and Biogenic Wastes - Methods and systems for converting a biomass and biogenic wastes to hydrogen with integrated carbon dioxide capture and storage are disclosed. In some embodiments, the methods include the following: mixing at least one of a dry solid or liquid or liquid hydroxide and catalysts with a biomass to form a biomass mixture; heating the biomass mixture until the hydroxide and the biomass react to produce hydrogen, carbonate, biochar, and potentially fertilizer; calcining the carbonate or performing double replacement reactions of the carbonate to produce sequestration-ready carbon dioxide and a hydroxide; storing the carbon dioxide produced; transferring the hydrogen produced to a fuel cell; and generating electricity with the fuel cell. | 02-05-2015 |
20150044757 | Methods and Systems for Capturing and Storing Carbon Dioxide - Methods and systems for capturing and storing carbon dioxide are disclosed. In some embodiments, the methods include the following: mixing materials including magnesium or calcium with one or more acids and chelating agents to form a magnesium or calcium-rich solvent; using the organic acids derived from biogenic wastes as acids or chelating agents; generating carbonate ions by reacting a gas including carbon dioxide with a carbonic anhydrase biocatalyst; reacting the solvent with the carbonate ions to form magnesium or calcium carbonates; recycling a solution containing the biocatalyst after forming magnesium or calcium carbonates for re-use in the generating step; using the magnesium and calcium carbonates as carbon neutral filler materials and using the silica product as green filler materials or inexpensive absorbents. | 02-12-2015 |
Patent application number | Description | Published |
20130005131 | SEMICONDUCTOR DEVICE FABRICATION USING GATE SUBSTITUTION - Methods is provided for forming a CMOS device. The method includes providing a substrate and depositing a gate stack on the substrate. The gate stack includes a gate dielectric and a dummy gate including polycrystalline silicon (polySi). The method also includes depositing a dielectric layer on the substrate after depositing the gate stack on the substrate. The method further includes substituting the dummy gate with a metal without first removing the dummy gate. | 01-03-2013 |
20130040450 | Methods of Forming a Dielectric Cap Layer on a Metal Gate Structure - Disclosed herein are various methods of forming metal-containing insulating material regions on a metal layer of a gate structure of a semiconductor device. In one example, the method includes forming a gate structure of a transistor, the gate structure comprising at least a first metal layer, and forming a first metal-containing insulating material region in the first metal layer by performing a gas cluster ion beam process using to implant gas molecules into the first metal layer. | 02-14-2013 |
20130043592 | Methods of Forming a Replacement Gate Comprised of Silicon and a Device Including Same - Disclosed herein are various methods of forming a replacement gate comprised of silicon and various semiconductor devices incorporation such a replacement gate structure. In one example, the method includes removing a sacrificial gate electrode structure to define a gate opening, forming a replacement gate structure in the gate opening, the replacement gate structure including at least one metal layer and a silicon-containing gate structure that is at least partially made of a metal silicide and forming a protective layer above at least a portion of the replacement gate structure. | 02-21-2013 |
20130217204 | METHODS FOR FABRICATING INTEGRATED CIRCUITS - Methods are provided for forming semiconductor devices. One method includes forming a first layer overlying a bulk semiconductor substrate. A second layer is formed overlying the first layer. A first plurality of trenches is etched into the first and second layers. The first plurality of trenches is filled to form a plurality of support structures. A second plurality of trenches is etched into the first and second layers. Portions of the second layer disposed between adjacent trenches of the first and second pluralities of trenches define a plurality of fins. The first layer is etched to form gap spaces between the bulk semiconductor substrate and the plurality of fins. The plurality of fins is supported in position adjacent to the gap spaces by the plurality of support structures. The gap spaces are filled with an insulating material. | 08-22-2013 |
20130260548 | TECHNIQUES FOR USING MATERIAL SUBSTITUTION PROCESSES TO FORM REPLACEMENT METAL GATE ELECTRODES OF SEMICONDUCTOR DEVICES WITH SELF-ALIGNED CONTACTS - Generally, the present disclosure is directed to techniques for using material substitution processes to form replacement metal gate electrodes, and for forming self-aligned contacts to semiconductor devices made up of the same. One illustrative method disclosed herein includes removing at least a dummy gate electrode to define a gate cavity, forming a work-function material in said gate cavity, forming a semiconductor material above said work-function material, and performing a material substitution process on said semiconductor material to substitute a replacement material for at least a portion of said semiconductor material. | 10-03-2013 |
20140065811 | REPLACEMENT METAL GATE SEMICONDUCTOR DEVICE FORMATION USING LOW RESISTIVITY METALS - Embodiments of the present invention relate to approaches for forming RMG FinFET semiconductor devices using a low-resistivity metal (e.g., W) as an alternate gap fill metal. Specifically, the semiconductor will typically comprise a set (e.g., one or more) of dielectric stacks formed over a substrate to create one or more trenches/channels (e.g., short/narrow and/or long/wide trenches/channels). A work function layer (e.g., TiN) will be provided over the substrate (e.g., in and around the trenches). A low-resistivity metal gate layer (e.g., W) may then be deposited (e.g., via chemical vapor deposition) and polished (e.g., via chemical-mechanical polishing). Thereafter, the gate metal layer and the work function layer may be etched after the polishing to provide a trench having the etched gate metal layer over the etched work function layer along a bottom surface thereof. | 03-06-2014 |
20140141605 | FINFET FORMATION USING DOUBLE PATTERNING MEMORIZATION - Approaches for forming a FinFET device using double patterning memorization techniques are provided. Specifically, a device will initially be formed by defining a set of fins, depositing a poly-silicon layer, and depositing a hardmask. Thereafter, a front end of the line (FEOL) lithography-etch, lithography-etch (LELE) process will be performed to form a set of trenches in the device. The set of trenches will be filled with an oxide layer that is subsequently polished. Thereafter, the device is selectively etched to yield a (e.g., poly-silicon) gate pattern. | 05-22-2014 |
Patent application number | Description | Published |
20100119847 | SEAL STRUCTURE AND ASSOCIATED METHOD - A seal structure is provided for an energy storage device. The seal structure includes a sealing glass joining an ion-conducting first ceramic to an electrically insulating second ceramic. The sealing glass has a composition that includes about 48 weight percent silica, about 20 weight percent to about 25 weight percent boria, about 20 weight percent to about 24 weight percent alumina, and about 8 weight percent to about 12 weight percent sodium oxide based on the total weight of the sealing glass composition. A method for making the seal structure is provided. An article comprising the seal structure is also provided. | 05-13-2010 |
20100120602 | SEALING GLASS COMPOSITION, METHOD AND ARTICLE - A sealing glass for an energy storage device is provided. The sealing glass includes silicon dioxide, boron oxide, aluminum oxide, sodium oxide and zirconium oxide. Methods for preparing the sealing glass and the energy storage device incorporating the sealing glass are also provided. | 05-13-2010 |
20100178532 | SEAL STRUCTURE AND ASSOCIATED METHOD - A seal structure is provided for an energy storage device. The seal structure includes a first sealing glass composition and a second sealing glass composition joining an ion-conducting first ceramic to an electrically insulating second ceramic. The first sealing glass composition includes less than or equal to about 20 weight percent silica based on the weight of the first sealing glass composition. The second sealing glass composition includes greater than or equal to about 40 weight percent silica based on the weight of the second sealing glass composition. A method for making the seal structure is provided. An article comprising the seal structure is also provided. | 07-15-2010 |
20110223475 | SEAL STRUCTURE AND ASSOCIATED METHOD - A seal structure is provided for an energy storage device. The seal structure includes a sealing glass joining an ion-conducting first ceramic to an electrically insulating second ceramic, wherein the ion-conducting first ceramic has an anode surface defining an anode compartment and a cathode surface defining a cathode compartment, wherein the sealing glass has an exposed portion, wherein the exposed portion is open to one or more of the anode compartment and the cathode compartment, wherein the exposed portion of the sealing glass is coated with a coating composition comprising one or more of boria, alumina, titania, zirconia, yttria, and ceria. Methods for forming the seal structure and article made therefrom are also provided. | 09-15-2011 |
20110244303 | Metalized Ceramic and Associated Method - A metalized ceramic comprising a ceramic substrate comprising a first ceramic and a ceramic metallization layer disposed on the ceramic substrate. The ceramic metallization layer comprises a mixture of (i) a second ceramic and (ii) a metal comprising nickel or a refractory metal. The refractory metal may consist one or more of molybdenum, tungsten, niobium and tantalum. The first ceramic and the second ceramic have a purity of greater than about 95 percent. A method of making the metalized ceramic is provided. An electrochemical cell including the metalized ceramic is also provided. | 10-06-2011 |
20120017825 | METHOD ASSOCIATED WITH A CRYSTALLINE COMPOSITION AND WAFER - A method for growing a crystalline composition, the first crystalline composition may include gallium and nitrogen. The crystalline composition may have an infrared absorption peak at about 3175 cm | 01-26-2012 |
20130189568 | SEALING GLASS COMPOSITION AND ARTICLE - A sealing glass composition for providing a glass seal in an electrochemical cell is presented. The sealing glass composition includes boron oxide, aluminum oxide, barium oxide, and zirconium oxide, and the glass composition is substantially free of silicon oxide and titanium oxide. The electrochemical cell incorporating the glass seal is also provided. | 07-25-2013 |
Patent application number | Description | Published |
20080276649 | Isopipe sag control using improved end support conditions - The invention is directed to a method of preventing isopipe sag when using the overflow drawdown fusion process for making flat glass sheets. The method applies a vertical restraint on at least one end of an isopipe resting on a support to thereby reduce sage and/or the rate of sag during use of the isopipe. Using the vertical restraint block in accordance with the invention, the sag and/or rate of sag has been found to be reduced by at least 40 percent relative to an isopipe that does not use the vertical restraints of the invention or a compressive force along the sides of the isopipe. | 11-13-2008 |
20100218557 | THERMAL CONTROL OF THE BEAD PORTION OF A GLASS RIBBON - Methods and apparatus for controlling the stress in, and the shape of, the glass ribbon ( | 09-02-2010 |
20110126587 | METHOD AND APPARATUS FOR MAKING A GLASS SHEET WITH CONTROLLED HEATING - A method and apparatus for forming a glass sheet using a fusion down-draw process, wherein the heating powers of the heating elements are managed such that in case of a failure of one heating element, the heating power of the adjacent heating element is immediately increased. The method decreases the thermal stress the forming body is exposed to due to the failure of the heating element. | 06-02-2011 |
20110253226 | ISOPIPE SAG CONTROL USING IMPROVED END SUPPORT CONDITIONS - The invention is directed to a method of preventing isopipe sag when using the overflow drawdown fusion process for making flat glass sheets. The method applies a vertical restraint on at least one end of an isopipe resting on a support to thereby reduce sage and/or the rate of sag during use of the isopipe. Using the vertical restraint block in accordance with the invention, the sag and/or rate of sag has been found to be reduced by at least 40 percent relative to an isopipe that does not use the vertical restraints of the invention or a compressive force along the sides of the isopipe. | 10-20-2011 |
20110302965 | Thermal Control of the Bead Portion of a Glass Ribbon - Methods and apparatus for controlling the stress in, and the shape of, the glass ribbon ( | 12-15-2011 |
20120111055 | METHOD OF PRODUCING UNIFORM LIGHT TRANSMISSION FUSION DRAWN GLASS - In a method of making a glass sheet using an overflow fusion downdraw process, a glass sheet quality metric level Q | 05-10-2012 |
20120180528 | HIGH STATIC FATIGUE ALUMINA ISOPIPES | 07-19-2012 |
20130269393 | METHOD AND APPARATUS FOR MAKING A GLASS SHEET WITH CONTROLLED HEATING - A method and apparatus for forming a glass sheet using a fusion down-draw process, wherein the heating powers of the heating elements are managed such that in case of a failure of one heating element, the heating power of the adjacent heating element is immediately increased. The method decreases the thermal stress the forming body is exposed to due to the failure of the heating element. | 10-17-2013 |
Patent application number | Description | Published |
20080282059 | METHOD AND APPARATUS FOR DETERMINING MEMBERSHIP IN A SET OF ITEMS IN A COMPUTER SYSTEM - A method and apparatus for maintaining membership in a set of items to be used in a predetermined manner in a computer system. A representation of each member of the set is mapped into a number of components of a primary and secondary vector when a member is added to the set. Periodically, the primary vector is changed to the secondary vector and the secondary vector to the primary vector. When members of the set are deleted, the components of the secondary vector are changed to indicate deletion of these members after the primary vector is changed to the secondary vector. Finally, membership in the set is determined by examining the components in the primary vector, and the members in the set of items are then used in a predetermined manner in the computer system. More specifically, in a sample embodiment of the present invention, membership in the set would determine if data is to be stored or removed from cache memory in a computer system. This invention, for example, provides a low cost and high performance mechanism to phase out aging membership information in a prefeteching mechanism for caching data or instructions in a computer system. | 11-13-2008 |
20080288760 | BRANCH TARGET PREDICTION FOR MULTI-TARGET BRANCHES BY IDENTIFYING A REPEATED PATTERN - An information processing system for branch target prediction includes: a first memory for storing entries for multi-target branch, wherein each entry includes a plurality of target addresses representing a history of target addresses for each single branch in the multi-target branch, and wherein said first memory stores an entry for the branch only if the branch is a multi-target branch; hardware logic for reading the memory and identifying a repeated pattern in each of the plurality of target addresses for the multi-target branch; logic for predicting a next target address for the multi-target branch based on the repeated pattern that was identified, using a pattern matching algorithm; and a second memory for storing information regarding whether a branch is a multi-target branch; wherein the logic for reading and the logic for predicting are executed only if the branch is the multi-target branch. | 11-20-2008 |
20090037708 | TARGET BRANCH PREDICTION USING CORRELATION OF LOCAL TARGET HISTORIES - A system for predicting multiple targets for a single branch includes: a branch target buffer that includes a previous next address for an instruction and that receives an indirect instruction address to provide a first branch target prediction; a first branch table for capturing local past target information of an indirect branch in an encoded form; a second branch table which is a correlation table for storing potential branch targets based on a local branch history and which provides a second branch target prediction when the first branch target prediction is not successful; an exclusion predictor for inhibiting updates of inefficient entries; and a multiplexer to select the predicted target as output. | 02-05-2009 |
20110138125 | EVENT TRACKING HARDWARE - An event tracking hardware engine having N (≧2) caches is invoked when an event of interest occurs, using a corresponding key. The engine stores, for each of the different kinds of events, a corresponding cumulative number of occurrences, by carrying out additional steps. In some instances, the additional steps include searching in the N caches for an entry for the key; if an entry for the key is found, and no overflow of the corresponding cumulative number of occurrences for the entry for the key would occur by incrementing the corresponding cumulative number of occurrences, incrementing; if the entry for the key is found, and overflow would occur, promoting the entry to a next highest cache; and if the entry for the key is not found, entering the entry for the key in a zeroth one of the caches with the corresponding cumulative number of occurrences being initialized. In other instances, the additional steps include searching in a zeroth one of the caches for an entry for the key; if an entry for the key is found in the zeroth one of the caches, and no overflow of the corresponding cumulative number of occurrences for the entry for the key would occur by incrementing the corresponding cumulative number of occurrences, incrementing; if the entry for the key is found in the zeroth one of the caches, and overflow would occur, promoting the entry from the zeroth one of the caches in which the entry exists to a next highest cache; and if the entry for the key is not found, entering the entry for the key in the zeroth one of the caches with the corresponding cumulative number of occurrences being initialized. The engine includes a plurality of caches and a corresponding plurality of control circuits. | 06-09-2011 |
20110238962 | Register Checkpointing for Speculative Modes of Execution in Out-of-Order Processors - A mechanism is provided for generating a checkpoint for a speculatively executed portion of code. The mechanisms identify, during a speculative execution of a portion of code, a register renaming operation occurring to an entry in a register renaming table of the processor. In response to the register renaming operation occurring to the register renaming table, a determination is made as to whether an update to an entry in a hardware-implemented recovery renaming table is to be performed. If so, the entry in the hardware-implemented recovery renaming table is updated. The entry in the recovery renaming table is part of the checkpoint for the speculative execution of the portion of code. | 09-29-2011 |
20110314259 | OPERATING A STACK OF INFORMATION IN AN INFORMATION HANDLING SYSTEM - A pointer is for pointing to a next-to-read location within a stack of information. For pushing information onto the stack: a value is saved of the pointer, which points to a first location within the stack as being the next-to-read location; the pointer is updated so that it points to a second location within the stack as being the next-to-read location; and the information is written for storage at the second location. For popping the information from the stack: in response to the pointer, the information is read from the second location as the next-to-read location; and the pointer is restored to equal the saved value so that it points to the first location as being the next-to-read location. | 12-22-2011 |
Patent application number | Description | Published |
20090200642 | HIGHLY TUNABLE METAL-ON-SEMICONDUCTOR TRENCH VARACTOR - An array of deep trenches is formed in a doped portion of the semiconductor substrate, which forms a lower electrode. A dielectric layer is formed on the sidewalls of the array of deep trenches. The array of deep trenches is filled with a doped semiconductor material to form an upper electrode comprising a top plate portion and a plurality of extension portions into the array of trenches. In a depletion mode, the bias condition across the dielectric layer depletes majority carriers within the top electrode, thus providing a low capacitance. In an accumulation mode, the bias condition attracts majority carriers toward the dielectric layer, providing a high capacitance. Thus, the trench metal-oxide-semiconductor (MOS) varactor provides a variable capacitance depending on the polarity of the bias. | 08-13-2009 |
20120007145 | ASYMMETRIC CHANNEL MOSFET - A field effect transistor includes a partial SiGe channel, i.e., a channel including a SiGe channel portion, located underneath a gate electrode and a Si channel portion located underneath an edge of the gate electrode near the drain region. The SiGe channel portion can be located directly underneath a gate dielectric, or can be located underneath a Si channel layer located directly underneath a gate dielectric. The Si channel portion is located at the same depth as the SiGe channel portion, and contacts the drain region of the transistor. By providing a Si channel portion near the drain region, the GIDL current of the transistor is maintained at a level on par with the GIDL current of a transistor having a silicon channel only during an off state. | 01-12-2012 |
20120190160 | ASYMMETRIC CHANNEL MOSFET - A field effect transistor includes a partial SiGe channel, i.e., a channel including a SiGe channel portion, located underneath a gate electrode and a Si channel portion located underneath an edge of the gate electrode near the drain region. The SiGe channel portion can be located directly underneath a gate dielectric, or can be located underneath a Si channel layer located directly underneath a gate dielectric. The Si channel portion is located at the same depth as the SiGe channel portion, and contacts the drain region of the transistor. By providing a Si channel portion near the drain region, the GIDL current of the transistor is maintained at a level on par with the GIDL current of a transistor having a silicon channel only during an off state. | 07-26-2012 |
20120256268 | INTEGRATED CIRCUIT STRUCTURE HAVING SUBSTANTIALLY PLANAR N-P STEP HEIGHT AND METHODS OF FORMING - Solutions for forming an integrated circuit structure having a substantially planar N-P step height are disclosed. In one embodiment, a method includes: providing a structure having an n-type field effect transistor (NFET) region and a p-type field effect transistor (PFET) region; forming a mask over the PFET region to leave the NFET region exposed; performing dilute hydrogen-flouride (DHF) cleaning on the exposed NFET region to substantially lower an STI profile of the NFET region; and forming a silicon germanium (SiGE) channel in the PFET region after the performing of the DHF. | 10-11-2012 |
Patent application number | Description | Published |
20110082680 | COMPACT MODEL FOR DEVICE/CIRCUIT/CHIP LEAKAGE CURRENT (IDDQ) CALCULATION INCLUDING PROCESS INDUCED UPLIFT FACTORS - A system, method and computer program product for implementing a quiescent current leakage specific model into semiconductor device design and circuit design flows. The leakage model covers all device geometries with wide temperature and voltage ranges and, without the need for stacking factor calculations nor spread sheet based IDDQ calculations. The leakage model for IDDQ calculation incorporates further parasitic and proximity effects. The leakage model implements leakage calculations at different levels of testing, e.g., from a single device to a full chip design, and are integrated within one single model. The leakage model implements leakage calculations at different levels of testing with the leverage of a single switch setting. The implementation is via a hardware definition language code or object oriented code that can be compiled and operated using a netlist of interest, e.g., for conducting a performance analysis. | 04-07-2011 |
20110095333 | HIGH-DRIVE CURRENT MOSFET - A method of forming a semiconductor device having an asymmetrical source and drain. In one embodiment, the method includes forming a gate structure on a first portion of the substrate having a well of a first conductivity. A source region of a second conductivity and drain region of the second conductivity is formed within the well of the first conductivity in a portion of the substrate that is adjacent to the first portion of the substrate on which the gate structure is present. A doped region of a second conductivity is formed within the drain region to provide an integrated bipolar transistor on a drain side of the semiconductor device, in which a collector is provided by the well of the first conductivity, the base is provided by the drain region of the second conductivity and the emitter is provided by the doped region of the second conductivity that is present in the drain region. A semiconductor device formed by the above-described method is also provided. | 04-28-2011 |
20110227136 | SPACER PROTECTION AND ELECTRICAL CONNECTION FOR ARRAY DEVICE - The present disclosure provides a method of forming an electrical device. The method may begin with forming a gate structure on a substrate, in which a spacer is present in direct contact with a sidewall of the gate structure. A source region and a drain region is formed in the substrate. A metal semiconductor alloy is formed on the gate structure, an outer sidewall of the spacer and one of the source region and the drain region. An interlevel dielectric layer is formed over the metal semiconductor alloy. A via is formed through the interlevel dielectric stopping on the metal semiconductor alloy. An interconnect is formed to the metal semiconductor alloy in the via. The present disclosure also includes the structure produced by the method described above. | 09-22-2011 |
Patent application number | Description | Published |
20120001283 | Germanium Photodetector - A method for forming a photodetector device includes forming an insulator layer on a substrate, forming a germanium (Ge) layer on the insulator layer and a portion of the substrate, forming a second insulator layer on the Ge layer, implanting n-type ions in the Ge layer, patterning the n-type Ge layer, forming a capping insulator layer on the second insulator layer and a portion of the first insulator layer, heating the device to crystallize the Ge layer resulting in an single crystalline n-type Ge layer, and forming electrodes electrically connected to the single crystalline n-type Ge layer. | 01-05-2012 |
20120288992 | Germanium Photodetector - A method for forming a photodetector device includes forming an insulator layer on a substrate, forming a germanium (Ge) layer on the insulator layer and a portion of the substrate, forming a second insulator layer on the Ge layer, patterning the Ge layer, forming a capping insulator layer on the second insulator layer and a portion of the first insulator layer, heating the device to crystallize the Ge layer resulting in an single crystalline Ge layer, implanting n-type ions in the single crystalline Ge layer, heating the device to activate n-type ions in the single crystalline Ge layer, and forming electrodes electrically connected to the single crystalline n-type Ge layer. | 11-15-2012 |
20140134789 | Germanium Photodetector - A method for forming a photodetector device includes forming an insulator layer on a substrate, forming a germanium (Ge) layer on the insulator layer and a portion of the substrate, forming a second insulator layer on the Ge layer, patterning the Ge layer, forming a capping insulator layer on the second insulator layer and a portion of the first insulator layer, heating the device to crystallize the Ge layer resulting in an single crystalline Ge layer, implanting n-type ions in the single crystalline Ge layer, heating the device to activate n-type ions in the single crystalline Ge layer, and forming electrodes electrically connected to the single crystalline n-type Ge layer. | 05-15-2014 |
20140134790 | Germanium Photodetector - A method for forming a photodetector device includes forming an insulator layer on a substrate, forming a germanium (Ge) layer on the insulator layer and a portion of the substrate, forming a second insulator layer on the Ge layer, patterning the Ge layer, forming a capping insulator layer on the second insulator layer and a portion of the first insulator layer, heating the device to crystallize the Ge layer resulting in an single crystalline Ge layer, implanting n-type ions in the single crystalline Ge layer, heating the device to activate n-type ions in the single crystalline Ge layer, and forming electrodes electrically connected to the single crystalline n-type Ge layer. | 05-15-2014 |
Patent application number | Description | Published |
20120168724 | TRANSFER-FREE BATCH FABRICATION OF SINGLE LAYER GRAPHENE DEVICES - A method of manufacturing one or more graphene devices is disclosed. A thin film growth substrate is formed directly on a device substrate. Graphene is formed on the thin film growth substrate. A transistor is also disclosed, having a device substrate and a source supported by the device substrate. The transistor also has a drain separated from the source and supported by the device substrate. The transistor further has a single layer graphene (SLG) channel grown partially on and coupling the source and the drain. The transistor also has a gate aligned with the SLG channel, and a gate insulator between the gate and the SLG channel. Integrated circuits and other apparati having a device substrate, a thin film growth substrate formed directly on at least a portion of the device substrate, and graphene formed directly on at least a portion of the thin film growth substrate are also disclosed. | 07-05-2012 |
20130062104 | RESONANT MATERIAL LAYER APPARATUS, METHOD AND APPLICATIONS - A resonant structure and a method for fabricating the resonant structure each include a substrate that includes at least one cavity. The resonant structure and the method for fabricating the resonant structure also include a resonant material layer located and formed over the substrate and at least in-part covering the at least one cavity. The resonant structure may comprise a graphene resonator structure. | 03-14-2013 |
20140037944 | COVALENT ORGANIC FRAMEWORK FILMS, AND METHODS OF MAKING AND USES OF SAME - Multilayer structures comprising a covalent organic framework (COF) film in contact with a polyaromatic carbon (PAC) film. The multilayer structures can be made by combining precursor compounds in the presence of a PAC film. The PAC film can be for example, a single layer graphene film. The multilayer structures can be used in a variety of applications such as solar cells, flexible displays, lighting devices, RFID tags, sensors, photoreceptors, batteries, capacitors, gas-storage devices, and gas-separation devices. | 02-06-2014 |
20140097537 | THIN FILM COMPOSITIONS AND METHODS - Certain embodiments of the present invention include a versatile and scalable process, “patterned regrowth,” that allows for the spatially controlled synthesis of lateral junctions between electrically conductive graphene and insulating h-BN, as well as between intrinsic and substitutionally doped graphene. The resulting films form mechanically continuous sheets across these heterojunctions. These embodiments represent an element of developing atomically thin integrated circuitry and enable the fabrication of electrically isolated active and passive elements embedded in continuous, one atom thick sheets, which may be manipulated and stacked to form complex devices at the ultimate thickness limit. | 04-10-2014 |
Patent application number | Description | Published |
20080211347 | Circuit System With Supply Voltage For Driving An Electromechanical Switch - A circuit for controlling operation of a load. In one example, a MEMS switch is positioned in the circuit to place the load in one of a conducting state or a nonconducting state. A piezoelectric transformer provides a relatively high voltage output signal or a relatively low voltage output signal to control movement of the switch between a closed position, placing the load in the conducting state, and an open position. The high voltage output signal includes a frequency component in the resonant frequency range of the transformer. Control circuitry provides an input voltage signal to the piezoelectric transformer to provide the high voltage output signal or the low voltage output signal at the output terminals of the piezoelectric transformer. | 09-04-2008 |
20080308394 | MICRO-ELECTROMECHANICAL SYSTEM BASED SWITCHING - A current control device is disclosed. The current control device includes control circuitry integrally arranged with a current path and at least one micro electromechanical system (MEMS) switch disposed in the current path. The current control device further includes a hybrid arcless limiting technology (HALT) circuit connected in parallel with the at least one MEMS switch facilitating arcless opening of the at least one MEMS switch, and a pulse assisted turn on (PATO) circuit connected in parallel with the at least one MEMS switch facilitating arcless closing of the at least one MEMS switch. | 12-18-2008 |
20080309438 | MICRO-ELECTROMECHANICAL SYSTEM BASED SWITCHING - A current control device is disclosed. The current control device includes control circuitry and a current path integrally arranged with the control circuitry. The current path includes a set of conduction interfaces and a micro electromechanical system (MEMS) switch disposed between the set of conduction interfaces. The set of conduction interfaces have geometry of a defined fuse terminal geometry and include a first interface disposed at one end of the current path and a second interface disposed at an opposite end of the current path. The MEMS switch is responsive to the control circuitry to facilitate the interruption of an electrical current passing through the current path. | 12-18-2008 |
20080310058 | MEMS MICRO-SWITCH ARRAY BASED CURRENT LIMITING ARC-FLASH ELIMINATOR - The present invention comprises MEMS enabled apparatus for the detection of arc-faults and the elimination of arc-flash conditions. The apparatus comprises an arc-flash detection component and a current limiting component. The current limiting component comprises a logic circuit in communication with the user interface, an MEMS protection circuit in communication with the logic circuit, and a switching circuit in communication with the MEMS protection circuit. The switching circuit comprises a plurality of micro-electromechanical system switching devices and a voltage limiting device, wherein the voltage limiting device is configured to prevent an over voltage event during a current limiting operation. | 12-18-2008 |
20080315980 | MEMS MICRO-SWITCH ARRAY BASED ON CURRENT LIMITING ENABLED CIRCUIT INTERRUPTING APPARATUS - The present invention comprises a micro-electromechanical system (MEMS) micro-switch array based current limiting enabled circuit interrupting apparatus. The apparatus comprising an over-current protective component, wherein the over-current protective component comprises a switching circuit, wherein the switching circuit comprises a plurality of micro-electromechanical system switching devices. The apparatus also comprises a circuit breaker or switching component, wherein the circuit breaker or switching component is in operable communication with the over-current protective component. | 12-25-2008 |
20100237227 | OPTICALLY GATED MEMS SWITCH - An optically powered MEMS gate driver includes a photovoltaic converter configured to receive a light signal from a light source and output a DC supply voltage for a MEMS gate driver in response thereto. The MEMS gate driver further includes a DC to DC converter electrically coupled to the photovoltaic converter and configured to output a line level DC voltage in response to the DC supply voltage. An electrical circuit, also included as a portion of the MEMS gate driver is electrically coupled to both the photovoltaic converter and the DC to DC converter is configured to receive the supply voltage and the line level voltage and to output a line level drive signal in response thereto. The optically powered MEMS gate driver is self-contained within a common EMI enclosure thus providing isolation between the gate driver and command signal electronics. | 09-23-2010 |
20110096444 | MICRO-ELECTROMECHANICAL SYSTEM BASED ARC-LESS SWITCHING WITH CIRCUITRY FOR ABSORBING ELECTRICAL ENERGY DURING A FAULT CONDITION - A system is presented. The system includes a micro-electromechanical system switch. Further, the system includes a balanced diode bridge configured to suppress arc formation between contacts of the micro-electromechanical system switch. A pulse circuit is coupled to the balanced diode bridge to form a pulse signal in response to a fault condition. An energy-absorbing circuitry is coupled in a parallel circuit with the pulse circuit and is adapted to absorb electrical energy resulting from the fault condition without affecting a pulse signal formation by the pulse circuit. | 04-28-2011 |
20110140546 | SWITCH STRUCTURE AND ASSOCIATED CIRCUIT - An apparatus, such as a switch module, is provided. The apparatus can include an electromechanical switch structure configured to move between an open configuration and a fully-closed configuration (associated with a minimum characteristic resistance) over a characteristic time. A commutation circuit can be connected in parallel with the electromechanical switch structure, and can include a balanced diode bridge configured to suppress arc formation between contacts of the electromechanical switch structure and a pulse circuit including a pulse capacitor configured to form a pulse signal (in connection with a switching event of the electromechanical switch structure) for causing flow of a pulse current through the balanced diode bridge. The electromechanical switch structure and the balanced diode bridge can be disposed such that a total inductance associated with the commutation circuit is less than or equal to a product of the characteristic time and the minimum characteristic resistance. | 06-16-2011 |
Patent application number | Description | Published |
20120154684 | METHOD FOR PRODUCING A BLENDED VIDEO SEQUENCE - A method for producing a blended video sequence that combines a still image and a video image sequence comprising: designating a first face in the still image, designating a second face in the video image sequence; detecting a series of video frames in the video image sequence containing the second face; identifying a video frame in the detected series of video frames suitable for transitioning from the first face into the second face; using a data processor to automatically produce a transition image sequence where the first face transitions into the second face, and a first background transitions into a second background; and producing the blended video sequence by concatenating the transition image sequence, and a plurality of video frames from the video image sequence starting from the identified video frame. | 06-21-2012 |
20120242794 | PRODUCING 3D IMAGES FROM CAPTURED 2D VIDEO - A method of producing a stereo image from a temporal sequence of digital images, comprising: receiving a temporal sequence of digital images; analyzing pairs of digital images to produce corresponding stereo suitability scores, wherein the stereo suitability score for a particular pair of images is determined responsive to the relative positions of corresponding features in the particular pair of digital image; selecting a pair of digital images including a first image and a second image based on the stereo suitability scores; using a processor to analyze the selected pair of digital images to produce a motion consistency map indicating regions of consistent motion, the motion consistency map having an array of pixels; producing a stereo image pair including a left view image and a right view image by combining the first image and the second image responsive to the motion consistency map; and storing the stereo image pair in a processor-accessible memory. | 09-27-2012 |
20120275701 | IDENTIFYING HIGH SALIENCY REGIONS IN DIGITAL IMAGES - A method for identifying high saliency regions in a digital image, comprising: segmenting the digital image into a plurality of segmented regions; determining a saliency value for each segmented region, merging neighboring segmented regions that share a common boundary in response to determining that one or more specified merging criteria are satisfied; and designating one or more of the segmented regions to be high saliency regions. The determination of the saliency value for a segmented region includes: determining a surround region including a set of image pixels surrounding the segmented region; analyzing the image pixels in the segmented region to determine one or more segmented region attributes; analyzing the image pixels in the surround region to determine one or more corresponding surround region attributes; determining a region saliency value responsive to differences between the one or more segmented region attributes and the corresponding surround region attributes. | 11-01-2012 |
20130002814 | METHOD FOR AUTOMATICALLY IMPROVING STEREO IMAGES - A method for improving a stereo image including a left view image and a right view image, comprising: using a data processor to automatically analyze the stereo image to determine an original stereo quality score responsive to relative positions of corresponding points in the left view image and the right view image; specifying a set of one or more candidate modifications to the stereo image; determining revised stereo quality scores based on each of the candidate modifications to the stereo image; selecting a particular candidate modification that produces a revised stereo quality score which indicates a higher quality level than the original stereo quality score; forming an output stereo image corresponding to the selected particular candidate modification; and storing the output stereo image in a processor-accessible memory. | 01-03-2013 |
20130235223 | COMPOSITE VIDEO SEQUENCE WITH INSERTED FACIAL REGION - A method for forming a composite video sequence, from a first digital video sequence captured of a scene by a photographer, and a second digital video sequence captured simultaneously with the first digital video sequence that includes the photographer. The first digital video sequence is analyzed to determine a low-interest spatial image region. A facial video sequence including the photographer's face is extracted from the second digital video sequence, and inserted into the low-interest spatial image region in the first digital video sequence to form the composite video sequence. | 09-12-2013 |
20130235224 | VIDEO CAMERA PROVIDING A COMPOSITE VIDEO SEQUENCE - A digital camera system including a first video capture unit for capturing a first digital video sequence of a scene and a second video capture unit that simultaneously captures a second digital video sequence that includes the photographer. A data processor automatically analyzes first digital video sequence to determine a low-interest spatial image region. A facial video sequence including the photographer's face is extracted from the second digital video sequence, and inserted into the low-interest spatial image region in the first digital video sequence to form the composite video sequence. | 09-12-2013 |
20140063536 | Method For Computing Scale For Tag Insertion - Computing a scale factor to insert a first set of shapes into a second set of shapes to form a combined image includes receiving the two sets of shapes, using a processor to convert the first set of shapes into a set of rectangles and the second set of shapes into a set of intervals and computing the scale factor for either the set of intervals or the set of rectangles to generate the combined image by iteratively inserting the set of rectangles into the set of intervals and updating the scale factor in response to a residual area or an overflow area until all the rectangles in the set of rectangles have been inserted into the set of intervals and the residual area in the set of intervals is below a threshold, and storing the combined image in memory. | 03-06-2014 |
20140063555 | Method For Generating Tag Layouts - Generating a tag layout from a set of tags and an ordering of the set of tags, wherein each tag includes a text label and a size for the text label, is disclosed. The method further includes receiving at least one closed shape corresponding to a space for the tag layout. A processor computes a scale factor for at least one of the closed shape or the size of the text labels in the set of tags to generate the tag layout of the set of tags within the closed shape such that all the tags in the set of tags fit within the closed shape and the tags are placed in the space based at least upon the ordering of the tags in the set of tags. | 03-06-2014 |
20140063556 | System For Generating Tag Layouts - Generating a tag layout from a set of tags and an ordering of the set of tags, wherein each tag includes a text label and a size for the text label, is disclosed. The system includes a processor accessible memory for receiving an ordered set of tags, each tag including a text label and a size for the text label, and at least one closed shape corresponding to a space for the tag layout. The system further includes a processor for generating the tag layout by computing a scale factor for either the closed shape or the size of the text labels in the set of tags such that all the tags in the set of tags fit within the closed shape, and the processor stores the generated tag layout in the memory. | 03-06-2014 |
20140176803 | METHOD FOR PRODUCING A BLENDED VIDEO SEQUENCE - A method for producing a blended video sequence that combines a still image and a video image sequence comprising: designating a first face in the still image, designating a second face in the video image sequence; detecting a series of video frames in the video image sequence containing the second face; identifying a video frame in the detected series of video frames suitable for transitioning from the first face into the second face; using a data processor to automatically produce a transition image sequence where the first face transitions into the second face, and a first background transitions into a second background; and producing the blended video sequence by concatenating the transition image sequence, and a plurality of video frames from the video image sequence starting from the identified video frame. | 06-26-2014 |
Patent application number | Description | Published |
20090160027 | Methods of Manufacturing Semiconductor Devices and Optical Proximity Correction - Methods of manufacturing semiconductor devices and methods of optical proximity correction methods are disclosed. In one embodiment, a method of manufacturing a semiconductor device includes determining an amount of reactive ion etch (RIE) lag of a RIE process for a material layer of the semiconductor device, and adjusting a size of at least one pattern for a feature of the material layer by an adjustment amount to partially compensate for the amount of RIE lag determined. | 06-25-2009 |
20090160062 | Semiconductor Devices and Methods of Manufacturing Thereof - Semiconductor devices, methods of manufacturing thereof, lithography masks, and methods of designing lithography masks are disclosed. In one embodiment, a semiconductor device includes a plurality of first features disposed in a first material layer. At least one second feature is disposed in a second material layer, the at least one second feature being disposed over and coupled to the plurality of first features. The at least one second feature includes at least one void disposed between at least two of the plurality of first features. | 06-25-2009 |
20100203701 | Crack Stop and Moisture Barrier - A design for a crack stop and moisture barrier for a semiconductor device includes a plurality of discrete conductive features formed at the edge of an integrated circuit proximate a scribe line. The discrete conductive features may comprise a plurality of staggered lines, a plurality of horseshoe-shaped lines, or a combination of both. | 08-12-2010 |
20110171821 | Semiconductor Devices and Methods of Manufacturing Thereof - Semiconductor devices, methods of manufacturing thereof, lithography masks, and methods of designing lithography masks are disclosed. In one embodiment, a semiconductor device includes a plurality of first features disposed in a first material layer. At least one second feature is disposed in a second material layer, the at least one second feature being disposed over and coupled to the plurality of first features. The at least one second feature includes at least one void disposed between at least two of the plurality of first features. | 07-14-2011 |
20120228743 | Methods of Manufacturing Semiconductor Devices and Optical Proximity Correction - Methods of manufacturing semiconductor devices and methods of optical proximity correction methods are disclosed. In one embodiment, a method of manufacturing a semiconductor device includes determining an amount of reactive ion etch (RIE) lag of a RIE process for a material layer of the semiconductor device, and adjusting a size of at least one pattern for a feature of the material layer by an adjustment amount to partially compensate for the amount of RIE lag determined. | 09-13-2012 |
Patent application number | Description | Published |
20090072387 | CURVILINEAR HEAT SPREADER/LID WITH IMPROVED HEAT DISSIPATION - A heat spreader or lid for a microelectronic package, in which the heat spreader has an underside surface that includes at least one curvilinear contour, in which the curvilinear contour is selected from at least one positive or protruding curvilinear feature, at least one negative or recessed curvilinear feature, and a combination thereof. A microelectronic package that includes the heat spreader/lid, in which there is improved heat dissipation or reduced mechanical stress in an interface between the heat spreader/lid and a circuit chip. | 03-19-2009 |
20110049221 | METHOD OF JOINING A CHIP ON A SUBSTRATE - A method and apparatus for making chip assemblies is disclosed that prevent or reduce the cracking and delamination of ultra low-k dielectrics in the back-end-of-line in Si chips that can occur during the chip assembly process. The method and apparatus apply pressure to the top and bottom surfaces of a substrate during the chip bonding process so that the bending and warping of the assembled modules are reduced. The reduced bending and warping prevent or reduce the cracking and delamination of ultra low-k dielectrics. | 03-03-2011 |
20110224951 | Integrated Framework for Finite-Element Methods for Package, Device and Circuit Co-Design - Electrical finite element analysis is carried out on a circuit design, which includes devices, to determine an acceptable power-performance envelope and to obtain data for circuit temperature mapping. A circuit temperature map is developed for the circuit design, based on the data for circuit temperature mapping. Thermo-mechanical finite element analysis is carried out on a package design for the circuit design, based on the circuit temperature map, to determine a package reliability limit based on thermal stress considerations. It is determined whether the package design and the circuit design jointly satisfy: (i) power-performance conditions specified in the acceptable power-performance envelope; and (ii) the package reliability limit based on the thermal stress considerations. | 09-15-2011 |
20120292375 | METHOD OF JOINING A CHIP ON A SUBSTRATE - A method and apparatus for making chip assemblies is disclosed that prevent or reduce the cracking and delamination of ultra low-k dielectrics in the back-end-of-line in Si chips that can occur during the chip assembly process. The method and apparatus apply pressure to the top and bottom surfaces of a substrate during the chip bonding process so that the bending and warping of the assembled modules are reduced. The reduced bending and warping prevent or reduce the cracking and delamination of ultra low-k dielectrics. | 11-22-2012 |
20120309132 | CURVILINEAR HEAT SPREADER/LID WITH IMPROVED HEAT DISSIPATION - A heat spreader or lid for a microelectronic package, in which the heat spreader has an underside surface that includes at least one curvilinear contour, in which the curvilinear contour is selected from at least one positive or protruding curvilinear feature, at least one negative or recessed curvilinear feature, and a combination thereof. A microelectronic package that includes the heat spreader/lid, in which there is improved heat dissipation or reduced mechanical stress in an interface between the heat spreader/lid and a circuit chip. | 12-06-2012 |
Patent application number | Description | Published |
20080235685 | METHOD AND SYSTEM FOR DYNAMIC APPLICATION COMPOSITION IN STREAMING SYSTEMS - A system and method for dynamically building applications for stream processing includes providing processing elements with a flow specification describing each input and a stream description describing each output such that the flow specification indicates a stream or streams which are to be received based on processing information and the stream descriptions indicate the processing information. Processing elements that can be reused are identified by determining equivalence between the processing elements. Processing elements that are new and are not reusable are instantiated in a flow graph. An application is dynamically composed, using the instantiated processing elements by routing available streams to the instantiated processing elements in accordance with the flow specifications. | 09-25-2008 |
20080256149 | SYSTEM AND METHOD FOR DEPENDENT FAILURE-AWARE ALLOCATION OF DISTRIBUTED DATA-PROCESSING SYSTEMS - A system and method for allocating distributed processing systems includes inputting component descriptions in a distributed processing system and determining importance of each component. Capacity and failure characteristics of resource groups representing units of available processing capacity are also input. Components are assigned to a plurality of resource groups based on the capacity. Each resource group includes components where the failure characteristics permit simultaneous failures, such that in the event of such failures, an output value of the application is maximized. | 10-16-2008 |
20090178046 | Methods and Apparatus for Resource Allocation in Partial Fault Tolerant Applications - Techniques are disclosed for allocation of resources in a distributed computing system. For example, a method for allocating a set of one or more components of an application to a set of one or more resource groups includes the following steps performed by a computer system. The set of one or more resource groups is ordered based on respective failure measures and resource capacities associated with the one or more resource groups. An importance value is assigned to each of the one or more components, wherein the importance value is associated with an affect of the component on an output of the application. The one or more components are assigned to the one or more resource groups based on the importance value of each component and the respective failure measures and resource capacities associated with the one or more resource groups, wherein components with higher importance values are assigned to resource groups with lower failure measures and higher resource capacities. The application may be a partial fault tolerant (PFT) application that comprises a set of one or more PFT application components. The set of one or more resource groups may comprise a heterogeneous set of resource groups (or clusters). | 07-09-2009 |
20090238178 | METHOD, SYSTEM, AND COMPUTER PROGRAM PRODUCT FOR IMPLEMENTING STREAM PROCESSING USING A RECONFIGURABLE OPTICAL SWITCH - A method, system, and computer program product for implementing stream processing are provided. The system includes an application framework and applications containing dataflow graphs managed by the application framework running on a first network. The system also includes at least one circuit switch in the first network having a configuration that is controlled by the application framework, a plurality of processing nodes interconnected by the first network over one of wireline and wireless links, and a second network for providing at least one of control and additional data transfer over the first network. The application framework reconfigures circuit switches in response to monitoring aspects of the applications and the first network | 09-24-2009 |
20130036424 | RESOURCE ALLOCATION IN PARTIAL FAULT TOLERANT APPLICATIONS - A method for allocating a set of components of an application to a set of resource groups includes the following steps performed by a computer system. The set of resource groups is ordered based on respective failure measures and resource capacities associated with the resource groups. An importance value is assigned to each of the components. The importance value is associated with an affect of the component on an output of the application. The components are assigned to the resource groups based on the importance value of each component and the respective failure measures and resource capacities associated with the resource groups. The components with higher importance values are assigned to resource groups with lower failure measures and higher resource capacities. The application may be a partial fault tolerant (PFT) application that comprises PFT application components. The resource groups may comprise a heterogeneous set of resource groups (or clusters). | 02-07-2013 |
20130046811 | STREAM PROCESSING USING A CLIENT-SERVER ARCHITECTURE - A method of responding to requests using stream processing can include receiving a server request from a server, wherein the server is configured to generate the server request responsive to a client request, and generating a request identifier associated with the server request. The method can include, responsive to the server request, sending a stream processing request derived from the server request to a first stream processing node. The stream processing request can include the request identifier. Responsive to receiving a create response message including a stream processing result and the request identifier from a second stream processing node, the stream processing result can be correlated with the server request. A write response message specifying the stream processing result can be sent to the server. | 02-21-2013 |
20130046859 | STREAM PROCESSING USING A CLIENT-SERVER ARCHITECTURE - A system for responding to requests using stream processing can include a processor configured to initiate executable operations including include receiving a server request from a server, wherein the server is configured to generate the server request responsive to a client request, generating a request identifier associated with the server request, and, responsive to the server request, sending a stream processing request derived from the server request to a first stream processing node. The stream processing request can include the request identifier. Responsive to receiving a create response message including a stream processing result and the request identifier from a second stream processing node, the stream processing result can be correlated with the server request. A write response message specifying the stream processing result can be sent to the server. | 02-21-2013 |
20130263121 | METHOD TO EMBED A LIGHT-WEIGHT KERNEL IN A FULL-WEIGHT KERNEL TO PROVIDE A HETEROGENEOUS EXECUTION ENVIRONMENT - Enabling a Light-Weight Kernel (LWK) to run in a virtualized environment on a Full-Weight Kernel (FWK), in one aspect, may include replacing a FWK loader, e.g., FWK's dynamic library loader or linker, with a LWK library on a first computing entity for an application allocated to run on one or more second computing entities. The LWK library may be enabled to initialize the one or more second computing entities and associated memory allocated to run the application under the LWK library. The LWK library may be enabled to manage the one or more second computing entities and said associated memory and resources needed by the application. | 10-03-2013 |
20130263157 | METHOD TO UTILIZE CORES IN DIFFERENT OPERATING SYSTEM PARTITIONS - A system call utility may be provided on a first operating system managing a first hardware computing entity. The system call utility may take as an argument a pointer to a computer code a second operating system established to run on the first hardware computing entity. The first operating system is enabled to execute the computer code natively on the first hardware computing entity, and return a result of the computer code executed on the first hardware computing entity to the second operating system. | 10-03-2013 |
20140115043 | STREAM PROCESSING USING A CLIENT-SERVER ARCHITECTURE - A computer hardware system configured to respond to requests using stream processing includes a HTTP stream server including at least one processor. The at least one processor is configured to initiate and/or perform the following. Responsive to a server request received from a server, a stream processing request is sent to a first stream processing node. Responsive to a create response message received from a second stream processing node, a stream processing result is correlated with the server request. A write response message including the stream processing result is sent to the server. The stream processing request is derived from the server request and includes a request identifier associated with the server request. The create response message includes the stream processing result and the request identifier. | 04-24-2014 |
20140115044 | STREAM PROCESSING USING A CLIENT-SERVER ARCHITECTURE - A system for responding to requests using stream processing comprises a computer readable storage medium having computer readable program code embodied therewith and a processor coupled to the computer readable storage medium. Responsive to a client request, a processing thread is assigned for handling the client request. A return connection is established within the processing thread. A server request derived from the client request to a stream server configured to interact with a plurality of stream processing nodes is sent, and the server request comprises a thread identifier specifying the processing thread. The processing thread for handling the client request is maintained in an idle state pending a write response message from the stream server. Responsive to receiving the write response message comprising a stream processing result and the thread identifier from the stream server, the processing thread is returned to an active state. | 04-24-2014 |
20140115045 | STREAM PROCESSING USING A CLIENT-SERVER ARCHITECTURE - A method for responding to requests using stream processing includes, responsive to a server request received from a server, a stream processing request being sent to a first stream processing node. Responsive to a create response message received from a second stream processing node, a stream processing result is correlated with the server request. A write response message including the stream processing result is sent to the server. The stream processing request is derived from the server request and includes a request identifier associated with the server request. The create response message includes the stream processing result and the request identifier. | 04-24-2014 |
20140115046 | STREAM PROCESSING USING A CLIENT-SERVER ARCHITECTURE - A method of responding to requests using stream processing includes, responsive to a client request, assigning a processing thread for handling the client request. A return connection is established within the processing thread. A server request derived from the client request is sent to a stream server configured to interact with a plurality of stream processing nodes. The server request includes a thread identifier specifying the processing thread. The processing thread for handling the client request is maintained in an idle state pending a write response message from the stream server. Responsive to receiving the write response message comprising a stream processing result and the thread identifier from the stream server, the processing thread specified by the thread identifier is returned to an active state using a processor. A client response comprising the stream processing result is returned to the client over the return connection. | 04-24-2014 |
20150074367 | METHOD AND APPARATUS FOR FAULTY MEMORY UTILIZATION - A method for faulty memory utilization in a memory system includes: obtaining information regarding memory health status of at least one memory page in the memory system; determining an error tolerance of the memory page when the information regarding memory health status indicates that a failure is predicted to occur in an area of the memory system affecting the memory page; initiating a migration of data stored in the memory page when it is determined that the data stored in the memory page is non-error-tolerant; notifying at least one application regarding a predicted operating system failure and/or a predicted application failure when it is determined that data stored in the memory page is non-error-tolerant and cannot be migrated; and notifying at least one application regarding the memory failure predicted to occur when it is determined that data stored in the memory page is error-tolerant. | 03-12-2015 |
20150074469 | METHODS, APPARATUS AND SYSTEM FOR NOTIFICATION OF PREDICTABLE MEMORY FAILURE - A method for providing notification of a predictable memory failure includes the steps of: obtaining information regarding at least one condition associated with a memory; calculating a memory failure probability as a function of the obtained information; calculating a failure probability threshold; and generating a signal when the memory failure probability exceeds the failure probability threshold, the signal being indicative of a predicted future memory failure. | 03-12-2015 |