Patent application number | Description | Published |
20090232876 | Method and composition for in situ formation of an artificial blockage to control bleeding - A composition for in situ formation of an artificial blockage to control bleeding includes a suitable amount of a polymer-forming component, a suitable amount of a crosslinking agent, hydrogen peroxide, and a decomposing agent for hydrogen peroxide. The decomposing agent includes exogenous or endogenous catalase, or both. | 09-17-2009 |
20090232877 | Method and composition for in situ formation and/or expansion of a polymer-based hemostatic agent to control bleeding - A composition for in situ formation and/or expansion of a polymer-based hemostatic agent to control bleeding includes a suitable amount of a polymer or polymer-forming component, hydrogen peroxide or chemical(s) capable of forming hydrogen peroxide, or a combination of both, and a decomposing agent for hydrogen peroxide. The decomposing agent includes an endogenously or exogenously supplied catalyst (other than catalase), or both, and/or the polymer or polymer-forming component. | 09-17-2009 |
20120308509 | Method and Composition for In Situ Formation of an Artificial Blockage to Control Blood Loss - Two siloxane-based mixtures combine to form a soft or semi-solid matrix for forming an artificial blockage to control bleeding, particularly moderate to severe bleeding. The first component includes a homogeneous mixture or solution that includes a polymeric matrix, a surfactant, filler(s) and metal compound(s). The second component includes a homogeneous mixture or solution that includes a polymer(s), a filler(s), a surfactant, and hydrogen peroxide. The combination of the two components is carried out with adequate mixing using mechanical and micro-kinetic mixing mechanisms and can be performed in a field-ready delivery device. | 12-06-2012 |
20140276484 | Clay Composites and their Applications - Clay composite sheets, mats, films or membranes without polymers. Methods of preparing clay composite sheets, mats, films or membranes without using polymers in the method. Methods of using clay composite sheets, mats, films or membranes prepared without using polymers. Antimicrobial dressing having organo-modified clay product. Transdermal delivery of drugs using organo-modified clay product and methods. | 09-18-2014 |
20140287640 | Functionalized Ionic Liquids and Their Applications - Disclosure of functionalized ionic liquids. Use of disclosed ionic liquids as solvent for carbon dioxide. Use of disclosed ionic liquids as flame retardant. Use of disclosed ionic liquids for coating fabric to obtain flame retardant fabric. | 09-25-2014 |
20140363393 | Method and Composition for In Situ Formation and/or Expansion of a Polymer-Based Hemostatic Agent to Control Bleeding - A composition for in situ formation and/or expansion of a polymer-based hemostatic agent to control bleeding includes a suitable amount of a polymer or polymer-forming component, hydrogen peroxide or chemical(s) capable of forming hydrogen peroxide, or a combination of both, and a decomposing agent for hydrogen peroxide. The decomposing agent includes an endogenously or exogenously supplied catalyst (other than catalase), or both, and/or the polymer or polymer-forming component. | 12-11-2014 |
Patent application number | Description | Published |
20090156213 | INTERWORKING GATEWAY FOR MOBILE NODES - Systems and methods are provided that allow inter-working between communication networks for the delivery of service to mobile nodes. A gateway is provided that communicates with a femto cell to extend service to an area that otherwise does not receive coverage from a service provider. The femto cell is a small scale base station used to provide coverage over a small area (such as a home or business), and connect to a home or enterprise network. The femto cell provides service for a mobile node and a gateway permits communication over a broadband network. The gateway integrates the mobile nodes connecting via a femto cell into the service provider's network. The gateway also allows provisioning of services and applications, control of service levels, and provides seamless handoffs to macro base stations and other types of access technologies such as Wi-Fi. | 06-18-2009 |
20100039978 | MULTIMEDIA BROADCAST AND MULTICAST SERVICE ENHANCEMENTS - Systems and methods for enhancing broadcast/multicast services in telecommunication networks are disclosed. A multicast router is provided between a network node, such as an SGSN or GGSN, and a radio access network. A multicast transport address can be provided to send packet data from network devices to the radio network in a multicast fashion. The multicast transport address works with multicast equipment, such as multicast routers, to reduce the burdens of sending data in a broadcast or multicast fashion to mobile nodes. | 02-18-2010 |
20110075557 | PROVIDING OFFLOADS IN A COMMUNICATION NETWORK - This disclosure relates to a system and method for offloading selected data to an alternate communication network. The offloading provides another route for selected packet traffic that can relieve the burden on a mobile operator's network, such as the backhaul and core networks. As the proliferation of data rich content and increasingly more capable mobile devices has continued, the amount of data communicated over mobile operator's networks has exponentially increased. Upgrading the existing network that was designed for voice calls is not desirable or practical for many mobile operators. A offload gateway is provided that inspects packets and determines those packets to offload to an alternate network as well as providing mobility management to allow for seamless handoffs and gateway relocations. | 03-31-2011 |
20120044908 | INTERWORKING GATEWAY FOR MOBILE NODES - Systems and methods are provided that allow inter-working between communication networks for the delivery of service to mobile nodes. A gateway is provided that communicates with a femto cell to extend service to an area that otherwise does not receive coverage from a service provider. The femto cell is a small scale base station used to provide coverage over a small area (such as a home or business), and connect to a home or enterprise network. The femto cell provides service for a mobile node and a gateway permits communication over a broadband network. The gateway integrates the mobile nodes connecting via a femto cell into the service provider's network. The gateway also allows provisioning of services and applications, control of service levels, and provides seamless handoffs to marco base stations and other types of access technologies such as Wi-Fi. | 02-23-2012 |
20120170548 | DISTRIBUTED LOAD MANAGEMENT ON NETWORK DEVICES - This disclosure relates to a system and method for dynamically managing load on network devices in a distributed manner. As the proliferation of data rich content and increasingly more capable mobile devices has continued, the amount of data communicated over mobile operator's networks has exponentially increased. Upgrading the existing network to accommodate increased data traffic is neither desirable nor practical. One way to accommodate increased data traffic is by utilizing network resources more efficiently. This disclosure provides systems and methods for efficiently utilizing network resources by dynamically configuring the network in a distributed manner based on real-time load information. | 07-05-2012 |
20130258854 | DISTRIBUTED LOAD MANAGEMENT ON NETWORK DEVICES - This disclosure relates to a system and method for dynamically managing load on network devices in a distributed manner. As the proliferation of data rich content and increasingly more capable mobile devices has continued, the amount of data communicated over mobile operator's networks has exponentially increased. Upgrading the existing network to accommodate increased data traffic is neither desirable nor practical. One way to accommodate increased data traffic is by utilizing network resources more efficiently. This disclosure provides systems and methods for efficiently utilizing network resources by dynamically configuring the network in a distributed manner based on real-time load information. | 10-03-2013 |
20140287760 | APPARATUS, SYSTEMS, AND METHODS FOR PROVIDING INTERWORKING GATEWAY - Systems and methods are provided that allow inter-working between communication networks for the delivery of service to mobile nodes. A gateway is provided that communicates with a femto cell to extend service to an area that otherwise does not receive coverage from a service provider. The femto cell is a small scale base station used to provide coverage over a small area (such as a home or business), and connect to a home or enterprise network. The femto cell provides service for a mobile node and a gateway permits communication over a broadband network. The gateway integrates the mobile nodes connecting via a femto cell into the service provider's network. The gateway also allows provisioning of services and applications, control of service levels, and provides seamless handoffs to marco base stations and other types of access technologies such as Wi-Fi. | 09-25-2014 |
Patent application number | Description | Published |
20090077354 | Techniques for Predicated Execution in an Out-of-Order Processor - A technique for handling predicated code in an out-of-order processor includes detecting a predicate defining instruction associated with a predicated code region. Renaming of predicated instructions, within the predicated code region, is then stalled until a predicate of the predicate defining instruction is resolved. | 03-19-2009 |
20090271772 | Using hardware interrupts to drive dynamic binary code recompilation - A method, computer system, and computer program product for using one or more hardware interrupts to drive dynamic binary code recompilation. The execution of a plurality of instructions is monitored to detect a problematic instruction. In response to detecting the problematic instruction, a hardware interrupt is thrown to a dynamic interrupt handler. A determination is made whether a threshold for dynamic binary code recompilation is satisfied. If the threshold for dynamic code recompilation is satisfied, the dynamic interrupt handler optimizes at least one of the plurality of instructions. | 10-29-2009 |
20090287908 | PREDICATION SUPPORT IN AN OUT-OF-ORDER PROCESSOR BY SELECTIVELY EXECUTING AMBIGUOUSLY RENAMED WRITE OPERATIONS - A predication technique for out-of-order instruction processing provides efficient out-of-order execution with low hardware overhead. A special op-code demarks unified regions of program code that contain predicated instructions that depend on the resolution of a condition. Field(s) or operand(s) associated with the special op-code indicate the number of instructions that follow the op-code and also contain an indication of the association of each instruction with its corresponding conditional path. Each conditional register write in a region has a corresponding register write for each conditional path, with additional register writes inserted by the compiler if symmetry is not already present, forming a coupled set of register writes. Therefore, a unified instruction stream can be decoded and dispatched with the register writes all associated with the same re-name resource, and the conditional register write is resolved by executing the particular instruction specified by the resolved condition. | 11-19-2009 |
20090288063 | PREDICATION SUPPORTING CODE GENERATION BY INDICATING PATH ASSOCIATIONS OF SYMMETRICALLY PLACED WRITE INSTRUCTIONS - A predication technique for out-of-order instruction processing provides efficient out-of-order execution with low hardware overhead. A special op-code demarks unified regions of program code that contain predicated instructions that depend on the resolution of a condition. Field(s) or operand(s) associated with the special op-code indicate the number of instructions that follow the op-code and also contain an indication of the association of each instruction with its corresponding conditional path. Each conditional register write in a region has a corresponding register write for each conditional path, with additional register writes inserted by the compiler if symmetry is not already present, forming a coupled set of register writes. Therefore, a unified instruction stream can be decoded and dispatched with the register writes all associated with the same re-name resource, and the conditional register write is resolved by executing the particular instruction specified by the resolved condition. | 11-19-2009 |
Patent application number | Description | Published |
20100077497 | IP-10 ANTIBODIES AND THEIR USES - The present invention provides isolated monoclonal antibodies, particularly human antibodies, that bind to IP-10 with high affinity, inhibit the binding of IP-10 to its receptor, inhibit IP-10-induced calcium flux and inhibit IP-10-induced cell migration. Nucleic acid molecules encoding the antibodies of the invention, expression vectors, host cells and methods for expressing the antibodies of the invention are also provided. Immunoconjugates, bispecific molecules and pharmaceutical compositions comprising the antibodies of the invention are also provided. The invention also provides methods for inhibiting IP-10 activity using the antibodies of the invention, including methods for treating various inflammatory and autoimmune diseases. | 03-25-2010 |
20120230998 | IP-10 ANTIBODIES AND THEIR USES - The present invention provides isolated monoclonal antibodies, particularly human antibodies, that bind to IP-10 with high affinity, inhibit the binding of IP-10 to its receptor, inhibit IP-10-induced calcium flux and inhibit IP-10-induced cell migration. Nucleic acid molecules encoding the antibodies of the invention, expression vectors, host cells and methods for expressing the antibodies of the invention are also provided. Immunoconjugates, bispecific molecules and pharmaceutical compositions comprising the antibodies of the invention are also provided. The invention also provides methods for inhibiting IP-10 activity using the antibodies of the invention, including methods for treating various inflammatory and autoimmune diseases. | 09-13-2012 |
20150104866 | IP-10 ANTIBODIES AND THEIR USES - The present invention provides isolated monoclonal antibodies, particularly human antibodies, that bind to IP-10 with high affinity, inhibit the binding of IP-10 to its receptor, inhibit IP-10-induced calcium flux and inhibit IP-10-induced cell migration. Nucleic acid molecules encoding the antibodies of the invention, expression vectors, host cells and methods for expressing the antibodies of the invention are also provided. Immunoconjugates, bispecific molecules and pharmaceutical compositions comprising the antibodies of the invention are also provided. The invention also provides methods for inhibiting IP-10 activity using the antibodies of the invention, including methods for treating various inflammatory and autoimmune diseases. | 04-16-2015 |
Patent application number | Description | Published |
20120011090 | METHODS AND SYSTEMS FOR THREE-MEMRISTOR SYNAPSE WITH STDP AND DOPAMINE SIGNALING - The present disclosure proposes implementation of a three-memristor synapse where an adjustment of synaptic strength is based on Spike-Timing-Dependent Plasticity (STDP) with dopamine signaling. | 01-12-2012 |
20120011092 | METHODS AND SYSTEMS FOR MEMRISTOR-BASED NEURON CIRCUITS - Certain embodiments of the present disclosure support techniques for designing neuron circuits based on memristors. Bulky capacitors as electrical current integrators can be eliminated and nanometer scale memristors can be utilized instead. Using the nanometer feature-sized memristors, the neuron hardware area can be substantially reduced. | 01-12-2012 |
20120036099 | METHODS AND SYSTEMS FOR REWARD-MODULATED SPIKE-TIMING-DEPENDENT-PLASTICITY - Certain embodiments of the present disclosure support techniques for simplified hardware implementation of the reward-modulated spike-timing-dependent plasticity (STDP) learning rule in networks of spiking neurons. | 02-09-2012 |
20140043962 | STATISTICS AND FAILURE DETECTION IN A NETWORK ON A CHIP (NoC) NETWORK - Certain aspects of the present disclosure support techniques for collecting system information in a network on a chip (NoC). A dedicated packet may be transmitted from a source node to a destination node. As it traverses through the NoC, the dedicated packet may collect information from various nodes, which may be made available by the destination node. The collected information may be used in an effort to detect failures and collect statistics regarding the NoC. | 02-13-2014 |
20140046885 | METHOD AND APPARATUS FOR OPTIMIZED REPRESENTATION OF VARIABLES IN NEURAL SYSTEMS - Certain aspects of the present disclosure support a technique for optimized representation of variables in neural systems. Bit-allocation for neural signals and parameters in a neural network described in the present disclosure may comprise allocating quantization levels to the neural signals based on at least one measure of sensitivity of a pre-determined performance metric to quantization errors in the neural signals, and allocating bits to the parameters based on the at least one measure of sensitivity of the pre-determined performance metric to quantization errors in the parameters. | 02-13-2014 |
20140101661 | METHOD AND APPARATUS FOR TIME MANAGEMENT AND SCHEDULING FOR SYCHRONOUS PROCESSING ON A CLUSTER OF PROCESSING NODES - Certain aspects of the present disclosure provide techniques for time management and scheduling of synchronous neural processing on a cluster of processing nodes. A slip (or offset) may be introduced between processing nodes of a distributed processing system formed by a plurality of interconnected processing nodes, to enable faster nodes to continue processing without waiting for slower nodes to catch up. In certain aspects, a processing node, after completing each processing step, may check for received completion packets and apply a defined constraint to determine whether it may start processing a subsequent step or not. | 04-10-2014 |
20140252531 | SYSTEMS AND METHODS FOR HARVESTING DISSIPATED HEAT FROM INTEGRATED CIRCUITS (ICS) IN ELECTRONIC DEVICES INTO ELECTRICAL ENERGY FOR PROVIDING POWER FOR THE ELECTRONIC DEVICES - Systems and methods for harvesting dissipated heat from integrated circuits (ICs) in electronic devices into electrical energy for providing power for the electronic devices are disclosed. In one embodiment, energy transferred from one or more ICs in the form of dissipated heat is harvested to convert at least a portion of this dissipated heat into electricity. This power can be used to provide power to the ICs to reduce overall power consumption by the electronic device. The harvested dissipated heat can be supplied to ICs in the electronic device to provide power to the ICs. Alternatively, or in addition, the harvested dissipated heat can be stored in an energy storage device to provide power to the ICs at a later time. | 09-11-2014 |
20140351190 | EFFICIENT HARDWARE IMPLEMENTATION OF SPIKING NETWORKS - Certain aspects of the present disclosure support operating simultaneously multiple super neuron processing units in an artificial nervous system, wherein a plurality of artificial neurons is assigned to each super neuron processing unit. The super neuron processing units can be interfaced with a memory for storing and loading synaptic weights and plasticity parameters of the artificial nervous system, wherein organization of the memory allows contiguous memory access. | 11-27-2014 |
20140365413 | EFFICIENT IMPLEMENTATION OF NEURAL POPULATION DIVERSITY IN NEURAL SYSTEM - Certain aspects of the present disclosure support a technique for efficient implementation of neural population diversity in neural systems. A set of parameters for each class of artificial neurons of a plurality of classes can be stored in a storage medium. A generator can be configured to obtain noise parameters for each class of artificial neurons in the neural system. After that, the noise parameters can be combined with the set of parameters for each class of artificial neurons to obtain a dithered set of parameters for each class of artificial neurons. The dithered set of parameters can be stored for each class of artificial neurons to be used for a neuron model for the artificial neurons that emulates behavior of the artificial neurons in the neural system. | 12-11-2014 |
20150046381 | IMPLEMENTING DELAYS BETWEEN NEURONS IN AN ARTIFICIAL NERVOUS SYSTEM - Methods and apparatus are provided for implementing delays in an artificial nervous system. Synaptic and/or axonal delays between a post-synaptic artificial neuron and one or more pre-synaptic artificial neurons may be accounted for at the post-synaptic artificial neuron. One example method for managing delay between neurons in an artificial nervous system generally includes receiving, at a post-synaptic artificial neuron, input current values from one or more pre-synaptic artificial neurons; accounting for delays between the one or more pre-synaptic artificial neurons and the post-synaptic artificial neuron at the post-synaptic artificial neuron; and determining a state of the post-synaptic artificial neuron based at least in part on at least a portion of the input current values, according to the accounting. | 02-12-2015 |
20150046382 | COMPUTED SYNAPSES FOR NEUROMORPHIC SYSTEMS - Methods and apparatus are provided for determining synapses in an artificial nervous system based on connectivity patterns. One example method generally includes determining, for an artificial neuron, an event has occurred; based on the event, determining one or more synapses with other artificial neurons based on a connectivity pattern associated with the artificial neuron; and applying a spike from the artificial neuron to the other artificial neurons based on the determined synapses. In this manner, the connectivity patterns (or parameters for determining such patterns) for particular neuron types, rather than the connectivity itself, may be stored. Using the stored information, synapses may be computed on the fly, thereby reducing memory consumption and increasing memory bandwidth. This also saves time during artificial nervous system updates. | 02-12-2015 |
20150066826 | METHODS AND APPARATUS FOR IMPLEMENTING A BREAKPOINT DETERMINATION UNIT IN AN ARTIFICIAL NERVOUS SYSTEM - Methods and apparatus are provided for using a breakpoint determination unit to examine an artificial nervous system. One example method generally includes operating at least a portion of the artificial nervous system; using the breakpoint determination unit to detect that a condition exists based at least in part on monitoring one or more components in the artificial nervous system; and at least one of suspending, examining, modifying, or flagging the operation of the at least the portion of the artificial nervous system, based at least in part on the detection. | 03-05-2015 |
20150106317 | SHARED MEMORY ARCHITECTURE FOR A NEURAL SIMULATOR - Aspects of the present disclosure provide methods and apparatus for allocating memory in an artificial nervous system simulator implemented in hardware. According to certain aspects, memory resource requirements for one or more components of an artificial nervous system being simulated may be determined and portions of a shared memory pool (which may include on-chip and/or off-chip RAM) may be allocated to the components based on the determination. | 04-16-2015 |
20150134582 | IMPLEMENTING SYNAPTIC LEARNING USING REPLAY IN SPIKING NEURAL NETWORKS - Aspects of the present disclosure relate to methods and apparatus for training an artificial nervous system. According to certain aspects, timing of spikes of an artificial neuron during a training iteration are recorded, the spikes of the artificial neuron are replayed according to the recorded timing, during a subsequent training iteration, and parameters associated with the artificial neuron are updated based, at least in part, on the subsequent training iteration. | 05-14-2015 |
20150213356 | METHOD FOR CONVERTING VALUES INTO SPIKES - A method for transmitting values in a neural network includes obtaining a parameter value. The method also includes encoding the parameter value based on at least one value used by a neuron. The encoding is based on a spike to be transmitted via a spike channel. | 07-30-2015 |
20160078001 | EVENT-BASED SPATIAL TRANSFORMATION - A method for computing a spatial Fourier transform for an event-based system includes receiving an asynchronous event output stream including one or more events from a sensor. The method further includes computing a discrete Fourier transform (DFT) matrix based on dimensions of the sensor. The method also includes computing an output based on the DFT matrix and applying the output to an event processor. | 03-17-2016 |
20160078321 | INTERFACING AN EVENT BASED SYSTEM WITH A FRAME BASED PROCESSING SYSTEM - A method of interfacing an event based processing system with a frame based processing system is presented. The method includes converting multiple events into a frame. The events may be generated from an event sensor. The method also includes inputting the frame into the frame based processing system. | 03-17-2016 |
20160080670 | EVENT-BASED DOWN SAMPLING - A method of event-based down sampling includes receiving multiple sensor events corresponding to addresses and time stamps. The method further includes spatially down sampling the addresses based on the time stamps and the addresses. The method may also include updating a pixel value for each of the multiple sensor events based on the down sampling. | 03-17-2016 |
20160092735 | SCANNING WINDOW IN HARDWARE FOR LOW-POWER OBJECT-DETECTION IN IMAGES - An apparatus includes a hardware sensor array including a plurality of pixels arranged along at least a first dimension and a second dimension of the array, each of the pixels capable of generating a sensor reading. A hardware scanning window array includes a plurality of storage elements arranged along at least a first dimension and a second dimension of the hardware scanning window array, each of the storage elements capable of storing a pixel value based on one or more sensor readings. Peripheral circuitry for systematically transfers pixel values, based on sensor readings, into the hardware scanning window array, to cause different windows of pixel values to be stored in the hardware scanning window array at different times. Control logic coupled to the hardware sensor array, the hardware scanning window array, and the peripheral circuitry, provides control signals to the peripheral circuitry to control the transfer of pixel values. | 03-31-2016 |
20160094800 | FEATURE COMPUTATION IN A SENSOR ELEMENT ARRAY - Techniques describe computing computer vision (CV) features based on sensor readings from a sensor and detecting macro-features based on the CV features. The sensor may include a sensor element array that includes a plurality of sensor elements. The sensor may also include in-pixel circuitry coupled to the sensor elements, peripheral circuitry and/or a dedicated microprocessor coupled to the sensor element array. The in-pixel circuitry, the peripheral circuitry or the dedicated microprocessor may include computation structures configured to perform analog or digital operations representative of a multi-pixel computation for a sensor element (or block of sensor elements), based on sensor readings generated by neighboring sensor elements in proximity to the sensor element, and to generate CV features. The dedicated microprocessor may process the CV features and detect macro-features. Furthermore, in certain embodiments, the dedicated microprocessor may be coupled to a second microprocessor through a wired or wireless interface. | 03-31-2016 |
20160094814 | LOW-POWER ALWAYS-ON FACE DETECTION, TRACKING, RECOGNITION AND/OR ANALYSIS USING EVENTS-BASED VISION SENSOR - Techniques disclosed herein utilize a vision sensor that integrates a special-purpose camera with dedicated computer vision (CV) computation hardware and a dedicated low-power microprocessor for the purposes of detecting, tracking, recognizing, and/or analyzing subjects, objects, and scenes in the view of the camera. The vision sensor processes the information retrieved from the camera using the included low-power microprocessor and sends “events” (or indications that one or more reference occurrences have occurred, and, possibly, associated data) for the main processor only when needed or as defined and configured by the application. This allows the general-purpose microprocessor (which is typically relatively high-speed and high-power to support a variety of applications) to stay in a low-power (e.g., sleep mode) most of the time as conventional, while becoming active only when events are received from the vision sensor. | 03-31-2016 |
Patent application number | Description | Published |
20090265609 | Method and System for Producing and Organizing Electronically Stored Information - The invention provides techniques for efficiently organizing and reviewing electronic documents to be produced in the course of a discovery process. The technique provides for marking the master or pivot document with review information, and identifying a plurality of duplicate documents related to the master or pivot document. The technique provides for reviewing a master or pivot document and propagating the review information to a set of related documents. The technique provides for producing a plurality of electronic documents where each of the electronic documents is marked up in accordance with the review information. The method provides for organizing the plurality of electronic documents so it can be presented and searched in an efficient manner. | 10-22-2009 |
20100318700 | Systems and methods for scalable distributed storage processing - A system including a storage processing device with an input/output module. The input/output module has port processors to receive and transmit network traffic. The input/output module also has a switch connecting the port processors. Each port processor categorizes the network traffic as fast path network traffic or control path network traffic. The switch routes fast path network traffic from an ingress port processor to a specified egress port processor. The storage processing device also includes a control module to process the control path network traffic received from the ingress port processor. The control module routes processed control path network traffic to the switch for routing to a defined egress port processor. The control module is connected to the input/output module. The input/output module and the control module are configured to interactively support data virtualization, data migration, data journaling, and snapshotting. The distributed control and fast path processors achieve scaling of storage network software. The storage processors provide line-speed processing of storage data using a rich set of storage-optimized hardware acceleration engines. The multi-protocol switching fabric provides a low-latency, protocol-neutral interconnect that integrally links all components with any-to-any non-blocking throughput. | 12-16-2010 |
20120209847 | METHODS AND SYSTEMS FOR AUTOMATICALLY GENERATING SEMANTIC/CONCEPT SEARCHES - In various embodiments, a semantic space associated with a corpus of electronically stored information (ESI) may be created and used for concept searches. Documents (and any other objects in the ESI, in general) may be represented as vectors in the semantic space. Vectors may correspond to identifiers, such as, for example, indexed terms. The semantic space for a corpus of ESI can be used in information filtering, information retrieval, indexing, and relevancy rankings. | 08-16-2012 |
20120209853 | METHODS AND SYSTEMS TO EFFICIENTLY FIND SIMILAR AND NEAR-DUPLICATE EMAILS AND FILES - A set of trigrams can be generated for each document in a plurality of documents processed by an e-discovery system. Each trigram in the set of trigrams for a given document is a sequence of three terms in the given document. A set of trigrams for each similar document is then determined based on the set of trigrams for the original document. To facilitate identification of the similar documents, a full text index is then generated for the plurality of documents and the set of trigrams for each document are indexed into the full text index, as individual terms. Queries can be generated into the full text index based on trigrams of a document to determine other similar or near-duplicate documents. After a set of potentially similar documents are identified, a separate distance criteria can be applied to evaluate the level of similarity between the two documents in an efficient way. | 08-16-2012 |
20120296891 | METHODS AND SYSTEMS FOR AUTOMATIC EVALUATION OF ELECTRONIC DISCOVERY REVIEW AND PRODUCTIONS - Techniques are provided for automatic sampling evaluation. An automatic sampling evaluation system enables users to evaluate convergence of one or more search processes. For example, given a set of searches that were validated by human review, a system can implement a retrieval process that samples one or more non-retrieved collections. Each individual document's similarity in the one or more non-retrieved collections is automatically evaluated to other documents in any retrieved sets. Given a goal of achieving a high recall, documents with high similarity can then be analyzed for additional noun phrases that may be used for a next iteration of a search. Convergence can be expected if the information gain in the new feedback loop is less than previous iterations, and if the additional documents identified are below a certain threshold document count. | 11-22-2012 |