Patent application number | Description | Published |
20090156009 | Method for manufacturing semiconductor device - Provided is a method of manufacturing a semiconductor device capable of providing a stable trench depth, including: forming, on a semiconductor substrate, a first film having a high etching selectivity with respect to the semiconductor substrate; forming, on the first film, a second film having a high etching selectivity with respect to the first film; etching a region of a part of the second film and the first film to expose a surface of the semiconductor substrate in the region; and etching the exposed surface of the semiconductor substrate to form a trench. | 06-18-2009 |
20090212357 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - Provided is a semiconductor device. A well region ( | 08-27-2009 |
20090212375 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - In a well region, an irregular structure is formed in a gate width direction, and a gate electrode is formed in concave portions and on top surfaces of convex portions via an insulating film. Upper and lower source regions are formed on one side of the gate electrode in a gate length direction, and upper and lower drain regions are formed on the other side thereof. By thus forming the lower source and drain regions in the source and drain regions, current concentration occurring in an upper portion of a channel region, which is generated as the gate length becomes shorter, may be suppressed and a current may be allowed to flow uniformly in the entire channel region, and hence an effective gate width is made wider owing to the irregular structure formed in the well region. Accordingly, an on-resistance of a semiconductor device is reduced to enhance driving performance. | 08-27-2009 |
20090230470 | Semiconductor device - Provided is a semiconductor device capable of easily setting a holding voltage with a low trigger voltage by locally forming a P-type diffusion layer between N-type source and drain diffusion layers of an NMOS transistor having a conventional drain structure used as an electrostatic protective element of the semiconductor device. | 09-17-2009 |
20100187608 | SEMICONDUCTOR DEVICE - Provided is a semiconductor device comprising: a PW layer formed at a surface of a semiconductor substrate; an NW layer formed at the surface of the semiconductor substrate to be in contact with the PW layer; a p+ base layer formed at the surface of the semiconductor substrate in the PW layer; an n+ collector layer formed at the surface of the semiconductor substrate in the NW layer; an n+ emitter layer located between the p+ base layer and the n+ collector layer and formed at the surface of the semiconductor substrate in the PW layer; and an n± layer formed between the n+ collector layer and the PW layer to be in contact with the n+ collector layer. | 07-29-2010 |
20110065247 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - Provided is a method for manufacturing a semiconductor device. A well region formed on a semiconductor substrate includes a plurality of trench regions, and a source electrode is connected to a source region formed on a substrate surface between the trench regions. Adjacently to the source region, a high concentration region is formed, which is brought into butting contact with the source electrode together with the source region, whereby a substrate potential is fixed. A drain region is formed at a bottom portion of the trench region, whose potential is taken to the substrate surface by a drain electrode buried inside the trench region. An arbitrary voltage is applied to a gate electrode, and the drain electrode, whereby carriers flow from the source region to the drain region and the semiconductor device is in an on-state. | 03-17-2011 |
20110079847 | Semiconductor Device - Provided is a semiconductor device capable of easily setting a holding voltage with a low trigger voltage by locally forming a P-type diffusion layer between N-type source and drain diffusion layers of an NMOS transistor having a conventional drain structure used as an electrostatic protective element of the semiconductor device. | 04-07-2011 |
20110156138 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - In a well region, an irregular structure is formed in a gate width direction, and a gate electrode is formed in concave portions and on top surfaces of convex portions via an insulating film. Upper and lower source regions are formed on one side of the gate electrode in a gate length direction, and upper and lower drain regions are formed on the other side thereof. By thus forming the lower source and drain regions in the source and drain regions, current concentration occurring in an upper portion of a channel region, which is generated as the gate length becomes shorter, may be suppressed and a current may be allowed to flow uniformly in the entire channel region, and hence an effective gate width is made wider owing to the irregular structure formed in the well region. Accordingly, an on-resistance of a semiconductor device is reduced to enhance driving performance. | 06-30-2011 |
20110221043 | Semiconductor device and manufacturing method therefor - Provided is a semiconductor device suitable for preventing film peeling due to dicing and preventing abnormal discharge. The semiconductor device includes a scribe region ( | 09-15-2011 |
20120187476 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - Trench portions ( | 07-26-2012 |
Patent application number | Description | Published |
20100289078 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - In order to further improve a driving performance without increasing an element area in a lateral MOS having a high driving performance, in which a gate width is increased per unit area by forming a plurality of trenches horizontally with respect to a gate length direction, the semiconductor device includes: a well region which is formed of a high resistance first conductivity type semiconductor at a predetermined depth from a surface of a semiconductor substrate; a plurality of trenches which extend from a surface to a midway depth in the well region; a gate insulating film which is formed on surfaces of concave and convex portions formed by the trenches; a gate electrode embedded inside the trenches; a gate electrode film which is formed on the surface of the substrate in contact with the gate electrode embedded inside the trenches in regions of the concave and convex portions, the regions excluding vicinities of both ends of the trenches; another gate electrode film which is embedded inside the trenches in the vicinities of the both ends of the trenches in contact with the gate electrode film so that a surface of the another gate electrode film is located at a position deeper than the surface of the semiconductor substrate; and a source region and a drain region which are formed as two low resistance second conductivity type semiconductor layers formed from a part of the semiconductor surface, the part being out of contact with the another gate electrode film, so as to be shallower than the depth of the well region. | 11-18-2010 |
20130119472 | SEMICONDUCTOR DEVICE - Provided is a semiconductor device comprising: a PW layer formed at a surface of a semiconductor substrate; an NW layer formed at the surface of the semiconductor substrate to be in contact with the PW layer; a p+ base layer formed at the surface of the semiconductor substrate in the PW layer; an n+ collector layer formed at the surface of the semiconductor substrate in the NW layer; an n+ emitter layer located between the p+ base layer and the n+ collector layer and formed at the surface of the semiconductor substrate in the PW layer; and an n± layer formed between the n+ collector layer and the PW layer to be in contact with the n+ collector layer. | 05-16-2013 |
20130277792 | SEMICONDUCTOR DEVICE - A semiconductor device having a clamp diode includes: a breakdown voltage adjusting first conductivity type low concentration region ( | 10-24-2013 |
20140217510 | SEMICONDUCTOR DEVICE - Provided is a semiconductor device which uses a comb-like N-type MOS transistor as an ESD protection element and is capable of uniformly operating the entire comb-like N-type MOS transistor. By adjusting a length L of a gate electrode of the N-type MOS transistor used as the ESD protection element in accordance with the distance from a contact for fixing a substrate potential, which is provided on a guard ring around an outer periphery, respective portion of N-type MOS transistor represented as a comb teeth uniformly enter snap-back operation, permitting avoidance of local concentration of current and obtainment of a desired ESD tolerance. | 08-07-2014 |