Patent application number | Description | Published |
20090154358 | AUTOMATIC ADJUSTMENT OF LOGICAL CHANNELS IN A FIBRE CHANNEL NETWORK - One embodiment of the present invention provides a system that facilitates automatic adjustment of logical channels in a Fibre Channel (FC) network. During operation, the system receives FC data frames. A respective data frame is associated with a logical channel. The bandwidth on an FC link can be allocated into a plurality of logical channels, and a respective logical channel is associated with a dedicated buffer and can transport a plurality of data flows with data frames of variable length. The system then identifies a slow data flow in a first logical channel. Next, the system assigns the slow data flow to a second logical channel, thereby preventing the slow data flow from slowing down other data flows in the first logical channel. The system subsequently forwards the data frames in the slow data flow on the second logical channel onto an outgoing link. | 06-18-2009 |
20100091780 | FRAME TRAFFIC BALANCING ACROSS TRUNK GROUPS - Embodiments of methods, apparatuses and/or systems for logical ports in trunking are disclosed. For example, a method of routing a flow of frames may include applying a correspondence between logical ports and physical ports of a switch. | 04-15-2010 |
20100095025 | VIRTUAL CHANNEL REMAPPING - Virtual channel enabled networking devices may map frames to specific virtual channels based upon frame characteristics (e.g. destination address, class of service). Devices and methods that provide a remapping of virtual channels are disclosed. In one embodiment, a network having virtual channel remapping may include: a first set of one or more switches that each support a first number of virtual channels, and a second set of one or more switches that each support a second number of virtual channels different from the first number of virtual channels. At least one switch from the second set is coupled to at least one switch from the first set and is configured to establish a correspondence (“map”) between the virtual channels supported by the first set and the virtual channels supported by the second set. | 04-15-2010 |
20110038263 | AUTOMATIC ADJUSTMENT OF LOGICAL CHANNELS IN A FIBRE CHANNEL NETWORK - One embodiment of the present invention provides a system that facilitates automatic adjustment of logical channels in a Fibre Channel (FC) network. During operation, the system receives FC data frames. A respective data frame is associated with a logical channel. The bandwidth on an FC link can be allocated into a plurality of logical channels, and a respective logical channel is associated with a dedicated buffer and can transport a plurality of data flows with data frames of variable length. The system then identifies a slow data flow in a first logical channel. Next, the system assigns the slow data flow to a second logical channel, thereby preventing the slow data flow from slowing down other data flows in the first logical channel. The system subsequently forwards the data frames in the slow data flow on the second logical channel onto an outgoing link. | 02-17-2011 |
20110041030 | STORAGE OF DATA AND SIGNATURE FORMED FROM DATA AND ADDRESS IN A MEMORY - A programmable device employs an address and data corruption logic for data written to a memory. A first signature is computed from the data stored in the memory and the address at which it is stored. The signature is stored with the data in the memory. When data is read from the memory, the first signature stored in the memory is also read and compared with a second signature computed from the data read from the memory and the address from which it is read. If the first and second signatures do not match, an error condition is indicated. | 02-17-2011 |
20110041031 | SEPARATE MEMORIES AND ADDRESS BUSSES TO STORE DATA AND SIGNATURE - A programmable device employs an address and data corruption logic for data written to a first memory. A first signature is computed from the data stored in the first memory and stored in a second memory. When data is read from the first memory, the first signature stored in the second memory is read and compared with a second signature computed from the data read from the first memory. If the first and second signatures do not match, an error condition is indicated. | 02-17-2011 |
20110066909 | PLUGGABLE TRANSCEIVER MODULE WITH ENHANCED CIRCUITRY - Pluggable transceiver modules with additional functions and circuitry contained within the module. In a first embodiment, additional circuitry is added to determine bit error rates at the point of the module itself. This allows a much better diagnostic evaluation of location of problem. In an alternate embodiment, various logic is placed in the module. In a first alternate embodiment encryption/decryption units are placed in the converter module so that encryption and decryption operations on the serial bitstream do not need to be performed in a switch. Existing switches can be used but the interconnecting links can still be encrypted. A second alternate embodiment includes compression/decompression units placed in the module to allow effective higher throughput on the selected links. | 03-17-2011 |
20110085444 | FLOW AUTODETERMINATION - Autodetermination circuitry examines packets transmitted internally to an egress port of a switching device in order to learn the associated flow. The autodetermination circuitry maintains a flow memory recording the highest traffic volume flows and unlearns the flows exhibiting lower traffic volumes to make room for other higher traffic volume flows. Accordingly, as some flows decrease in traffic volume and other flows increase in traffic volume, the flows decreasing below a threshold are dropped from a flow memory, and other flows increasing in volume above the threshold are added to the flow memory. In this manner, only the most likely offending flows are maintained in the flow memory. Accordingly, when congestion is detected, the switching device can identify one or more source devices contributing the most to the congestion and take steps to alleviate the congestion by decreasing the traffic volume originating from one or more of those sources. | 04-14-2011 |
20110216769 | Dynamic Path Selection - A switch/router dynamically selects a path from multiple available paths between a source destination pair for a frame. A hash function generates a hash value from frame parameters such as source ID, destination ID, exchange ID, etc. The hash value is given as an input to a plurality of range comparators where each range comparator has a range of values associated with it. If the hash value falls within a range associated with a range comparator, that range comparator generates an in-range signal. A path selector module detects which range comparator has generated the in-range signal, and determines a path associated with that range comparator from previously stored information. The frame is transmitted via the selected path. The ranges associated with each range comparator can be non-overlapping and unequal in size. The number of range comparators can be equal to a number of selected multiple paths. | 09-08-2011 |
20110231570 | Method and Apparatus for Mirroring Frames to a Remote Diagnostic System - Apparatuses and methods to mirror frames received at an input port or provided by an output port to a port not connected to the device performing the mirroring operation. A frame being sent to a diagnostic system has a mirror header added to allow the frame to be routed through any intervening switches in the same fabric. The final switch or the diagnostic system removes the mirror header. If the diagnostic system is attached in a different fabric, encapsulation and inter-fabric routing headers are added as needed to the frame containing the mirror header. This allows the frame to traverse multiple fabrics to reach the diagnostic system. The encapsulation and inter-fabric routing headers are removed as done normally. This allows a diagnostic system to be connected to any switch in the network, either in the same or a different fabric. | 09-22-2011 |
20110267952 | DYNAMIC LATENCY-BASED REROUTING - A switch creates and dynamically updates a latency map of a network to adjust routing of flows. Further, the network is monitored to detect latency issues and trigger a dynamic adjustment of routing based on the latency map. In this manner, a flow can be routed along a route (i.e., a faster route) that provides less latency than other available routes. The latency map can be generated based on latency probe packets that are issued from and returned to the source switch. By evaluating many such latent probe packets that have traveled along many available routes (e.g., corresponding to various ports of the switch), the switch or associated administrative logic can dynamically adjust the latency map to updated latency information of available routes. Therefore, responsive to a trigger, the source switch can dynamically adjust the routing of a flow based on latency issues discerned from the network. | 11-03-2011 |
20110307447 | Inline Wire Speed Deduplication System - Systems for performing inline wire speed data deduplication are described herein. Some embodiments include a device for inline data deduplication that includes one or more input ports for receiving an input data stream containing duplicates, one or more output ports for providing a data deduplicated output data stream, and an inline data deduplication engine coupled to said one or more input ports and said one or more output ports to process input data containing duplicates into output data which is data deduplicated, said inline data deduplication engine having an inline data deduplication bandwidth of at least 4 Gigabytes per second. | 12-15-2011 |
20110307659 | Hardware-Accelerated Lossless Data Compression - Systems for hardware-accelerated lossless data compression are described. At least some embodiments include data compression apparatus that includes a plurality of hash memories each associated with a different lane of a plurality of lanes (each lane including data bytes of a data unit being received by the compression apparatus), an array including array elements each including a plurality of validity bits (each validity bit within an array element corresponding to a different lane of the plurality of lanes), control logic that initiates a read of a hash memory entry if a corresponding validity bit indicates that said entry is valid, and an encoder that compresses at least the data bytes for the lane associated with the hash memory comprising the valid entry if said valid entry comprises data that matches the lane data bytes. | 12-15-2011 |
20120075999 | DYNAMIC LATENCY-BASED REROUTING - A switch creates and dynamically updates a latency map of a network to adjust routing of flows. Further, the network is monitored to detect latency issues and trigger a dynamic adjustment of routing based on the latency map. In this manner, a flow can be routed along a route (i.e., a faster route) that provides less latency than other available routes. The latency map can be generated based on latency probe packets that are issued from and returned to the source switch. By evaluating many such latent probe packets that have traveled along many available routes (e.g., corresponding to various ports of the switch), the switch or associated administrative logic can dynamically adjust the latency map to updated latency information of available routes. Therefore, responsive to a trigger, the source switch can dynamically adjust the routing of a flow based on latency issues discerned from the network. | 03-29-2012 |
20120076149 | Transmission bandwidth quality of service - A bandwidth limiting circuit provides limiting the bandwidth of a group of virtual channels at a transmitting port to a maximum value. A limiting circuit includes a register that is repeatedly incremented with a threshold value, which threshold value is related to the desired maximum bandwidth for the group. The register is decremented by the frame length, in bytes, of the frame transmitted from one of the virtual channels belonging to the group. A comparator enables frame transmission for the group if the register value is greater than zero. A bandwidth guarantee circuit provides at least the bandwidth specified by the limiting circuit. The guarantee circuit enables one of the groups for frame transmission based on a fairness algorithm when the outputs of comparators of each of the limiting circuit are low. | 03-29-2012 |
20120096310 | REDUNDANCY LOGIC - A network system provides network device having a secondary memory that mirrors the content of a primary memory maintaining data structure parameters entries. The integrity of each data structure parameter entry is tested as the entry is output from the primary memory, such as by using a parity test. If an error is detected in the entry, a corresponding entry from the second memory structure is select for use instead of the entry from the primary memory. The corresponding entries in each memory are then flushed, updated, synchronized, or overwritten from the each memory and processing continues using the new entries or other entries from the primary memory. In the rare instance that corresponding entries from both memories exhibit an error, then an error notification is issued. | 04-19-2012 |
20120144103 | Two-Port Memory Implemented With Single-Port Memory Blocks - A two-port memory having a read port, a write port and a plurality of identical single-port RAM banks. The capacity of one of the single-port RAM banks is used to resolve collisions between simultaneous read and write accesses to the same single-port RAM bank. A read mapping memory stores instance information that maps logical banks and a spare bank to the single-port RAM banks for read accesses. Similarly, a write mapping memory stores write instance information that maps logical banks and a spare bank to the single-port RAM banks for write accesses. If simultaneous read and write accesses are not mapped to the same single-port RAM bank, read and write are performed simultaneously. However, if a collision exists, the write access is re-mapped to a spare bank identified by the write instance information, allowing simultaneous read and write. Both read and write mapping memories are updated to reflect any re-mapping. | 06-07-2012 |
20120173935 | PLUGGABLE TRANSCEIVER MODULE WITH ENHANCED CIRCUITRY - Pluggable transceiver modules with additional functions and circuitry contained within the module. In a first embodiment, additional circuitry is added to determine bit error rates at the point of the module itself. This allows a much better diagnostic evaluation of location of problem. In an alternate embodiment, various logic is placed in the module. In a first alternate embodiment encryption/decryption units are placed in the converter module so that encryption and decryption operations on the serial bitstream do not need to be performed in a switch. Existing switches can be used but the interconnecting links can still be encrypted. A second alternate embodiment includes compression/decompression units placed in the module to allow effective higher throughput on the selected links. | 07-05-2012 |
20130031077 | Longest Prefix Match Scheme - A LPM search engine includes a plurality of exact match (EXM) engines and a moderately sized TCAM. Each EXM engine uses a prefix bitmap scheme that allows the EXM engine to cover multiple consecutive prefix lengths. Thus, instead of covering one prefix length L per EXM engine, the prefix bitmap scheme enables each EXM engine to cover entries having prefix lengths of L, L+1, L+2 and L+3, for example. As a result, fewer EXM engines are potentially underutilized, which effectively reduces quantization loss. Each EXM engine provides a search result with a determined fixed latency when using the prefix bitmap scheme. The results of multiple EXM engines and the moderately sized TCAM are combined to provide a single search result, representative of the longest prefix match. In one embodiment, the LPM search engine supports 32-bit IPv4 (or 128-bit IPv6) search keys, each having associated 15-bit level 3 VPN identification values. | 01-31-2013 |
20140153570 | MULTICAST SPRAY OVER LAG - Use of a hash operation based on selected information in the packet to select one of a set of enable vectors. The selected enable vector is then effectively ANDed with the link expansion vector to select the actual links to be used. The enable vectors vary by selecting a different link in the LAG port for each enable vector. Thus the hash is used to vary the link of the LAG port used to transmit the packet for that multicast packet. | 06-05-2014 |
20140212134 | AUTOMATIC ADJUSTMENT OF LOGICAL CHANNELS IN A FIBRE CHANNEL NETWORK - One embodiment of the present invention provides a system that facilitates automatic adjustment of logical channels in a Fibre Channel (FC) network. During operation, the system receives FC data frames. A respective data frame is associated with a logical channel. The bandwidth on an FC link can be allocated into a plurality of logical channels, and a respective logical channel is associated with a dedicated buffer and can transport a plurality of data flows with data frames of variable length. The system then identifies a slow data flow in a first logical channel. Next, the system assigns the slow data flow to a second logical channel, thereby preventing the slow data flow from slowing down other data flows in the first logical channel. The system subsequently forwards the data frames in the slow data flow on the second logical channel onto an outgoing link. | 07-31-2014 |