Kirichenko, US
Alexander F. Kirichenko, Pleasantville, NY US
Patent application number | Description | Published |
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20090086533 | SUPERCONDUCTING CIRCUIT FOR HIGH-SPEED LOOKUP TABLE - A high-speed lookup table is designed using Rapid Single Flux Quantum (RSFQ) logic elements and fabricated using superconducting integrated circuits. The lookup table is composed of an address decoder and a programmable read-only memory array (PROM). The memory array has rapid parallel pipelined readout and slower serial reprogramming of memory contents. The memory cells are constructed using standard non-destructive reset-set flip-flops (RSN cells) and data flip-flops (DFF cells). An n-bit address decoder is implemented in the same technology and closely integrated with the memory array to achieve high-speed operation as a lookup table. The circuit architecture is scalable to large two-dimensional data arrays. | 04-02-2009 |
20090237106 | DIGITAL PROGRAMMABLE PHASE GENERATOR - A programmable phase shifter is constructed of Rapid Single Flux Quantum (RSFQ) logic elements. The logic elements may include an RSFQ inverter and an RSFQ T flip-flop. A digital word comprising N bits is used to control the amount of phase shift and the phase shifter selectively imparts a respective phase shift for any of 2 | 09-24-2009 |
Alex F. Kirichenko, Pleasantville, NY US
Patent application number | Description | Published |
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20110167241 | SUPERCONDUCTING CIRCUIT FOR HIGH-SPEED LOOKUP TABLE - A high-speed lookup table is designed using Rapid Single Flux Quantum (RSFQ) logic elements and fabricated using superconducting integrated circuits. The lookup table is composed of an address decoder and a programmable read-only memory array (PROM). The memory array has rapid parallel pipelined readout and slower serial reprogramming of memory contents. The memory cells are constructed using standard non-destructive reset-set flip-flops (RSN cells) and data flip-flops (DFF cells). An n-bit address decoder is implemented in the same technology and closely integrated with the memory array to achieve high-speed operation as a lookup table. The circuit architecture is scalable to large two-dimensional data arrays. | 07-07-2011 |
Dmitri Kirichenko, Yorktown Heights, NY US
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20100148841 | Multiphase clock for superconducting electronics - A multiphase clock circuit in which bit errors are propagated only for the duration of the clock cycle in which a bit error occurs. The circuit recovers automatically from bit errors and is capable of operating at high frequency with high clock precision. The multiphase clock circuit can generate a plurality of clock pulse streams, each pulse stream at the same clock frequency, with fixed phase relationships among the streams. The multiphase clock circuit includes a master clock signal of frequency fc which is applied to a divide by N frequency divider circuit for producing a base clock signal of fc/N. The base clock signal is sequentially applied to the data input of a series chain of N clocked data flip-flops (DFFs) each of which is simultaneously clocked by a clock signal of frequency fc to produce N clock signals of base frequency fc/N separated from each other by a constant time delay T=1/fc. | 06-17-2010 |
20100149011 | SUPERCONDUCTING ANALOG-TO-DIGITAL CONVERTER - A superconducting bandpass sigma-delta Analog-to-Digital Converter (ADC) is disclosed. The ADC is characterized as being an N | 06-17-2010 |
20120157321 | Injection Locked Long Josephson Junction Pulse Source - A superconducting circuit, and a method, are disclosed for generating pulses with stable frequency. The circuit includes an annular Long Josephson Junction (LJJ) capable of producing electrical pulses of a desired frequency due to a steady bias current applied to the LJJ. The circuit further includes an electrical interface for injecting an RF signal of a first frequency into the annular LJJ, resulting in the desired frequency locking onto the first frequency. Typically the first frequency substantially equals the desired frequency. The injection of the RF signal further results in the decrease of the frequency jitter of the desired frequency. The pulses generated in the loop section of the LJJ are outputted through a tail section of the LJJ, and through transmission lines which couple to the tail section. | 06-21-2012 |
20120274494 | SUPERCONDUCTING ANALOG-TO-DIGITAL CONVERTER WITH CURRENT AMPLIFIED FEEDBACK - A superconducting bandpass sigma-delta modulator and a method for analog-to-digital signal conversion is disclosed. The superconducting bandpass sigma-delta modulator includes coupled resonators having a desired impedance ratio. A first resonator connects to a comparator, which comparator generates single-flux-quantum pulses. A feedback loop links from the comparator to a second resonator and includes a current amplifier. A digital RF receiver system is also disclosed. This system includes a second order bandpass sigma-delta modulator, which has a desired impedance ratio between resonators and a feedback loop with current amplification. The system further has an antenna configured to receive a GHz frequency radio transmission and to yield an analog signal which is accepted by the sigma-delta modulator. | 11-01-2012 |
Dmitri Kirichenko, Pleasantville, NY US
Patent application number | Description | Published |
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20090153381 | Superconductor Analog-to-Digital Converter - A superconducting Analog-to-Digital Converter (ADC) employing rapid-single-flux-quantum (RSFQ) logic is disclosed. The ADC has only superconductor active components, and is characterized as being an N | 06-18-2009 |
20100026537 | Superconductor Analog-to-Digital Converter - A superconducting Analog-to-Digital Converter (ADC) employing rapid-single-flux-quantum (RSFQ) logic is disclosed. The ADC has only superconductor active components, and is characterized as being an N | 02-04-2010 |
20100066576 | Superconductor Multi-Level Quantizer - A superconductor multi-level quantizer is disclosed, which quantizer includes a number N of Josephson junction (JJ) comparators connected in parallel to a common input node. The quantizer further includes at least one flux bias device. Each flux bias device is capable to adjust the flux threshold for at least one of the JJ comparators. The quantizer is so configured a feedback current from the output is capable to shift the flux threshold for each of the JJ comparators. | 03-18-2010 |
Kostyantyn Kirichenko, Alachua, FL US
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20090215985 | DIFFERENTIALLY PROTECTED ORTHOGONAL LANTHIONINE TECHNOLOGY - The present invention provides a method of synthesizing an intramolecularly bridged polypeptide comprising at least one intramolecular bridge. The present invention further provides a method of synthesizing an intramolecularly bridged polypeptide comprising two intramolecular bridges, wherein the two intramolecular bridges form two overlapping ring, two rings in series, or two embedded rings. The present invention also provides methods for synthesizing lantibiotics, including Nisin A. Additionally, the invention provides intramolecularly bridged polypeptides synthesized by the methods disclosed herein and differentially protected orthogonal lanthionines. | 08-27-2009 |
Taras A. Kirichenko, Austin, TX US
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20100244121 | STRESSED SEMICONDUCTOR DEVICE AND METHOD FOR MAKING - A method of making a semiconductor device on a semiconductor layer includes forming a gate dielectric and a first layer of gate material over the gate dielectric. The first layer is etched to remove a portion of the first layer of gate material over a first portion of the semiconductor layer and to leave a select gate portion. A storage layer is formed over the select gate portion and over the first portion of the semiconductor layer. A second layer of gate material is formed over the storage layer. The second layer of gate material is etched to remove a first portion of the second layer of gate material over a first portion of the select gate portion. A portion of the first portion of the select gate is etched out to leave an L-shaped select structure. The result is a memory cell with an L-shaped select gate. | 09-30-2010 |
20100248466 | METHOD FOR MAKING A STRESSED NON-VOLATILE MEMORY DEVICE - A method of making a semiconductor device on a semiconductor layer includes: forming a gate dielectric over the semiconductor layer; forming a layer of gate material over the gate dielectric; etching the layer of gate material to form a select gate; forming a storage layer that extends over the select gate and over a portion of the semiconductor layer; depositing an amorphous silicon layer over the storage layer; etching the amorphous silicon layer to form a control gate; and annealing the semiconductor device to crystallize the amorphous silicon layer. | 09-30-2010 |