Arai, Kawasaki
Hiroaki Arai, Kawasaki JP
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20130007558 | ERROR CORRECTING CODE DECODING DEVICE, DECODING METHOD, AND MOBILE STATION APPARATUS - An error correcting code decoding device includes a first decoding circuit, a word-length reduction circuit configured to reduce bit lengths of a first external values corresponding to a plurality of bits obtained after decoding process performed by the first decoding circuit a first predetermined number of times and to reduce bit lengths of words included in word string, and a second decoding circuit configured to decode the bit string by executing a decoding process a second predetermined number of times for calculating second external values and posterior values of the bits included in the bit string in accordance with the word string including the words having the reduced bit lengths using the first external values having the reduced bit lengths as second prior probabilities that corresponding bits among the plurality of bits are the predetermined value. | 01-03-2013 |
20140079161 | RECEIVER AND RECEIVING METHOD - A receiver including: a memory, and a processor configured to calculate a plurality of soft decision values based on a received symbol to which a plurality of bits are mapped, to select at least one first soft decision value of the plurality of soft decision values, to calculate at least one relative value of at least one second soft decision value of the plurality of soft decision values other than the at least one first soft decision value, based on the at least one first soft decision value, to store the at least one first soft decision value and the at least one relative value, in the memory, and to estimate the plurality of bits based on the at least one first soft decision value and the at least one relative value which are stored in the memory. | 03-20-2014 |
Kazuya Arai, Kawasaki JP
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20120067635 | Package substrate unit and method for manufacturing package substrate unit - A semiconductor chip mounting layer of a package substrate unit includes an insulation layer, a conductive seed metal layer formed on the top surface of the insulation layer, conductive pads formed on the top surface of the conductive seed metal layer, metal posts formed substantially in the central portion on the top surface of the conductive pads, and a solder resist layer that is formed to surround the conductive pads and the metal posts. | 03-22-2012 |
20120241206 | METHOD OF MANUFACTURING CIRCUIT BOARD, METHOD OF MANUFACTURING ELECTRONIC DEVICE, AND ELECTRONIC DEVICE - A method of manufacturing a circuit board includes forming a first electrode on a support substrate, covering the support substrate and the first electrode with a first insulating layer, polishing the first insulating layer to expose a first surface of the first electrode, forming a first wiring on the first insulating layer after exposing the first surface of the first electrode, the first wiring being connected to the first electrode, and removing the support substrate to expose a second surface of the first electrode after forming the first wiring. | 09-27-2012 |
Masaki Arai, Kawasaki JP
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20140196052 | COMPUTER SYSTEM - In the present invention, a management apparatus includes a unit configured to store management information including a throughput of each of a plurality of computers, a unit configured to acquire a request value which includes a throughput that is required for executing a program from a program execution computer to which execution of a program has been assigned among a plurality of computers, a selecting unit configured to select a computer of a throughput compliant with the request value from among a plurality of computers, and a switchover control unit configured to allocate the program allocated to the program execution computer to the selected computer. | 07-10-2014 |
20140359214 | VARIABLE UPDATING DEVICE AND VARIABLE UPDATING METHOD - A procedure, which is performed by a processor of a variable updating device, includes: (a) judging whether or not the cache set is a cache set selected in advance; (b) in a case in which the corresponding cache set is judged to be the cache set selected in advance, judging which of (1) a hit and (2) a miss has occurred; and (c) carrying out a first processing that, in a case in which it is judged that the miss has occurred, updates a miss variable that expresses a number of times that misses have occurred and stores the address information in the storage portion, and a second processing that, in a case in which it is judged that the hit has occurred, updates a hit variable that expresses a number of times that hits have occurred. | 12-04-2014 |
Masanori Arai, Kawasaki JP
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20130033712 | DETECTION METHOD AND DETECTION APPARATUS - A detection method of detecting a position of an uppermost substrate of a plurality of substrates stacked on each other includes applying illumination to a region covering a portion of an edge of the uppermost substrate and a portion of a lower substrate stacked with the uppermost substrate, identifying a position of the edge of the uppermost substrate based on a position of a step-like portion present in the region due to a step formed between the uppermost substrate and the lower substrate, and identifying a position of the uppermost substrate based on the position of the edge of the uppermost substrate. | 02-07-2013 |
20140022560 | DETECTION METHOD AND DETECTION APPARATUS - A detection method of detecting a position of an uppermost substrate of a plurality of substrates stacked on each other includes applying illumination to a region covering a portion of an edge of the uppermost substrate and a portion of a lower substrate stacked with the uppermost substrate, identifying a position of the edge of the uppermost substrate based on a position of a step-like portion present in the region due to a step formed between the uppermost substrate and the lower substrate, and identifying a position of the uppermost substrate based on the position of the edge of the uppermost substrate. | 01-23-2014 |
Massahiro Arai, Kawasaki JP
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20080288678 | STORAGE SYSTEM - Data transfer is performed to and from a host computer using a first block as the minimum unit. Data transfer is performed to and from a storage area using a second block as the minimum unit. A second block set of the storage area stores data obtained from performing data conversion processes that change the size of the data itself, with a first block set as the unit. Here a correspondence relationship is generated between the first block set and the second block set. In response to a read request from the host computer, a second block set, which corresponds to the first block set that includes the first block that is requested, is read, a reverse-conversion process is performed, and the data is sent to the host computer. | 11-20-2008 |
Natsuko Arai, Kawasaki JP
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20100306822 | Communication System, Line Providing Apparatus And Communication Method - A line providing apparatus has an acceptance processor accepting a line use request from the terminal apparatus, a contract determiner determines a state of conclusion of a first contract, a second contract or a combined contract obtained by substantially combining the first contract and the second contract at the terminal apparatus which is a source of the line use request accepted by the acceptance processor, and an assistance processor performing an assisting process for conclusion of a contract found not to be concluded according to a result of determination on the state of conclusion of the first contract, the second contract or the combined contract by the contract determiner, whereby the user of the terminal apparatus which does not yet conclude can sign the contract for the communication service or the information providing service through the terminal apparatus. | 12-02-2010 |
Tomoyuki Arai, Kawasaki JP
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20090153233 | BIAS CIRCUIT - A gm compensation current source controls current that runs through a current source transistor, source-grounded transistors that determine a gain so that mutual conductance gm of the source-grounded transistors is compensated and the gain is compensated. A 1/r current source runs current inversely proportional to variation of load resistors of an amplifier so that gate bias points of gate-grounded transistors that are connected to the source-grounded transistors remain constant, and deterioration of linearity at a drain terminal of a gate-grounded transistor is suppressed. | 06-18-2009 |
20090167435 | POWER CONTROL CIRCUIT AND POWER CONTROL METHOD - A power control circuit includes: a fine adjustment variable amplifying unit configured to amplify the input signal in accordance with a first gain set value; a coarse adjustment variable amplifying unit configured to amplify the input signal in accordance with a second gain set value; a branching unit configured to branch an output signal into a feedback signal; a comparing unit configured to compare a gain value between the input signal and the output signal with the required gain set value; a control unit configured to determine the first gain set value and the second gain set value based on the required gain set value; and an adjusting unit configured to adjust the first gain set value and the second gain set value so that the power value of the feedback signal becomes a power value corresponding to the required gain set value. | 07-02-2009 |
20100039178 | AMPLIFIER CIRCUIT - An amplifier circuit includes an amplifier unit and a current control circuit as means for achieving the aforementioned object. The amplifier unit includes a gain compensation MOS transistor compensating for gain of an output characteristic and a linearity compensation MOS transistor compensating for linearity of an output characteristic. A source of the gain compensation MOS transistor is connected to a drain of the linearity compensation MOS transistor. An input signal is applied to a gate of the linearity compensation MOS transistor. A drain of the gain compensation MOS transistor is set as an output. The current control circuit performs control so as to pass predetermined current between the drain and the source of the gain compensation MOS transistor and pass predetermined current between the drain and the source of the linearity compensation MOS transistor. | 02-18-2010 |
20100109777 | Amplifying Circuit - An amplifying circuit includes amplifying unit comprising a first transistor unit having a gate width that is controllable and is controlled based on a first control signal. | 05-06-2010 |
20100207692 | BIAS CIRCUIT AND CONTROL METHOD FOR BIAS CIRCUIT - A bias circuit for applying a bias voltage to a nonlinear amplification circuit, including a constant-current source; and a first, second, third, and fourth transistors, wherein a current mirror circuit is configured by the first transistor and the second transistor, and the bias voltage is outputted from the drain of the second transistor, gate lengths and gate widths of the first and second transistor are the same, gate lengths of the first to fourth transistor are the same, and gate lengths and gate widths of the first, second, third, and fourth transistor are configured so that k | 08-19-2010 |
Toshimasa Arai, Kawasaki JP
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20100177658 | Network Monitoring System and Path Extracting Method - A network monitoring system that monitors a communication network including plural communication apparatuses and includes an obtaining part for obtaining a transmission traffic amount and a reception traffic amount of each port of the plural communication apparatuses, a determining part for determining whether the transmission traffic amount is no less than a first threshold and whether the reception traffic amount is less than a second threshold for each port of the plural communication apparatuses, a storage part for storing connecting path data of the communication network therein, an extracting part for extracting a loop affected path, and an outputting part for outputting data of the loop affected path. | 07-15-2010 |
20120023378 | INFORMATION PROCESSING APPARATUS AND INFORMATION PROCESSING METHOD - An information processing apparatus receives a request transmitted from a client to a server and a response transmitted from the server to the client. The information processing apparatus includes a processor. The processor counts a first number of first requests having no corresponding response within a first time period, counts a second number of second requests having a corresponding response, and detects a failure in the server on the basis of the first number and the second number. | 01-26-2012 |
Yoshinori Arai, Kawasaki JP
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20130246444 | DEVICE, METHOD OF PROCESSING DATA, AND COMPUTER-READABLE RECORDING MEDIUM - A device includes a memory configured to store a program; and a processor coupled to the memory and configured to execute a process based on the program. The process includes: for input data made of a combination of pieces of unit data and including a plurality of consecutive records each including data of a plurality of items, when a sequence of type information indicating a kind of each piece of the unit data in the input data is divided into partial sequences each having a certain length, analyzing a break position of the records in the input data by determining, as a length of each of the records, the length of each of the partial sequences when sequences of type information in all the partial sequences correspond to each other. | 09-19-2013 |