Patent application number | Description | Published |
20090153230 | Low Voltage Charge Pump with Regulation - Techniques of providing a low output voltage, high current capability charge pump are given. The charge pump has multiple capacitors along with switching circuitry. In an initialization phase, the first plate of each of the capacitors is connected to receive a regulator voltage and the second plate of each capacitor is connected to ground. In a transfer phase, the capacitors are connected in series, where, for each capacitor after the first, the second plate is connected to the first plate of the preceding capacitor in the series. The output voltage of the pump is from the first plate of the last capacitor in the series. Regulation circuitry generates the regulator voltage from a reference voltage to have a value responsive to the output voltage level of the pump. | 06-18-2009 |
20090153231 | Diode Connected Regulation of Charge Pumps - A circuit including a charge pump and regulation circuitry is described. The output of the charge pump is connected to provide a first output signal that is connectable to drive a load. A diode is connected to provide a second output signal of lower voltage from the first output signal. The regulation circuitry is connected to the second output level and is connectable to the charge pump to regulate its output. The circuit also includes a current source connectable from the second line to ground, where control circuitry connects the current source to the second line when the first line is connected to the load. | 06-18-2009 |
20090161434 | Read, Verify Word Line Reference Voltage to Track Source Level - A non-volatile memory device has individual pages of memory cells to be sensed in parallel. The memory device includes a source level tracking circuit coupled to receive a predetermined word line voltage from a word line voltage supply and the voltage level at the aggregate source node of one or more pages and coupled to provide to word lines of the memory an output voltage during the sensing operation, where the source level tracking circuit includes an op amp whereby the output voltage is the word line voltage offset by an amount to track the voltage level at the aggregate node and compensate for source bias errors due to a finite resistance in the ground loop. | 06-25-2009 |
20090302930 | Charge Pump with Vt Cancellation Through Parallel Structure - A charge pump circuit for generating an output voltage is described. The charge pump includes an output generation section and a threshold voltage cancelation section, where these sections have the same structure including a first branch, which receives a first clock signal and provides a first output, and a second branch, which receives a second clock signal and provides a second output. The charge pump circuit also includes first and second transistors, where the first and second outputs of the output generation stage are respectively connected through the first and second transistors to provide the output voltage of the charge pump, and where the first and second outputs of the threshold voltage cancellation stage are respectively connected to the control gate the first and second transistors. | 12-10-2009 |
20090315616 | Clock Generator Circuit for a Charge Pump - A charge pump system is formed on an integrated circuit that can be connected to an external power supply. The system includes a charge pump and a clock generator circuit. The clock circuit is coupled to provide a clock output, at whose frequency the charge pump operates and generates an output voltage from an input voltage. The clock frequency is a decreasing function of the voltage level of the external power supply. This allows for reducing power consumption in the charge pump system formed on a circuit connectable to an external power supply. | 12-24-2009 |
20090322413 | Techniques of Ripple Reduction for Charge Pumps - A charge pump system for supplying an output voltage to a load is described. It includes a regulation circuit connected to receive the output voltage and derive an enable signal from it and multiple charge pump circuits connected in parallel to supply the output voltage. Each of the charge pump circuits is also connected to receive a clock signal and the enable signal. The system also includes one or more delay circuit elements, where a corresponding one or more, but less than all, of the charge pump circuits are connectable to receive the enable signal delayed by the corresponding delay circuit element. | 12-31-2009 |
20100019832 | Self-Adaptive Multi-Stage Charge Pump - A charge pump circuit for generating an output voltage is described. The charge pump includes multiple output generation stages connected in series and a corresponding set of multiple gate stages connected in series, where the output stages have the same structure as the corresponding gate stages. The switches that the provide the output of each output generation stage are controlled by the corresponding gate stage. The number of output stages that are active in boosting the voltage self-adapts according to the output level being regulated, with the later stages changing from a boosting operation to a filtering function with not being used to active boost the output. | 01-28-2010 |
20100073069 | On-Chip Bias Voltage Temperature Coefficient Self-Calibration Mechanism - Techniques and corresponding circuitry for deriving a supply a bias voltage for a memory cell array from a received reference voltage is presented. The circuit includes a voltage determination circuit, which is connected to receive the reference voltage and generate from it the bias voltage, a temperature sensing circuit, and a calibration circuit. The calibration circuit is connected to receive the bias voltage and to receive a temperature indication from the temperature sensing circuit and determine from the bias voltage and temperature indication a compensation factor that is supplied to the voltage determination circuit, which adjusts the bias voltage based upon the compensation factor. | 03-25-2010 |
20100074033 | Bandgap Voltage and Temperature Coefficient Trimming Algorithm - A circuit and corresponding method for providing a reference voltage are presented. The circuit includes a current source having a magnitude with positive temperature correlation connected to a node, and a diode element connected between the node and ground, where the reference voltage is provided from the node. The circuit also includes a variable resistance connected to receive an input indicative of the circuit temperature and through which the diode element is connected to the node. The value of the variable resistance is adjusted based upon the circuit temperature input. The circuit is useful for application as a peripheral circuitry, such as on a flash or other non-volatile memory and other circuits requiring an on-chip reference voltage source. | 03-25-2010 |
20100157681 | Read, Verify Word Line Reference Voltage to Track Source Level - A non-volatile memory device has individual pages of memory cells to be sensed in parallel. The memory device includes a source level tracking circuit coupled to receive a predetermined word line voltage from a word line voltage supply and the voltage level at the aggregate source node of one or more pages and coupled to provide to word lines of the memory an output voltage during the sensing operation, where the source level tracking circuit includes an op amp whereby the output voltage is the word line voltage offset by an amount to track the voltage level at the aggregate node and compensate for source bias errors due to a finite resistance in the ground loop. | 06-24-2010 |
20110018615 | Charge Pump with Current Based Regulation - A charge pump system using a current based regulation method, in addition to the typical voltage based regulation methods is presented. The current flow in the charge pump is determined independently of the output voltage. By sensing the current going through the charge pump while its output is being regulated to the target level, the strength of charge pump can be dynamically adjusted in term of regulation level, branch assignment, clock frequency, clock amplitude, and so on. Indirectly sensing the current going through pump (not in serial with output stage to allow additional IR drop) will allow the pumps to have matrix of V and I to better adjust the charge pump parameters for current saving and ripple reduction | 01-27-2011 |
20110018617 | Charge Pump with Reduced Energy Consumption Through Charge Sharing and Clock Boosting Suitable for High Voltage Word Line in Flash Memories - A charge pump circuit for generating an output voltage is described. Charge pump circuits typically have two branches. As the clocks supplying the branches of a charge pump circuit alternate, the output of each branch will alternately provide an output voltage, which are then combined to form the pump output. The techniques described here allow charge to be transferred between the two branches, so that as the capacitor of one branch discharges, it is used to charge up the capacitor in the other branch. An exemplary embodiment using a voltage doubler-type of circuit, with the charge transfer between the branches accomplished using a switch controller by a boosted version of the clock signal, which is provided by a one-sided voltage doubler | 01-27-2011 |
20110133820 | Multi-Stage Charge Pump with Variable Number of Boosting Stages - A charge pump circuit for generating an output voltage is described. The charge pump includes multiple output generation stages connected in series, where the number of stages operating in a boosting mode is variable in order to regulate the pump. The number of stages arranged in series stays the same, but the last one or more of the stages can be operated in a filtering mode, with the number of boosting stages being lower as the regulation level goes lower. This improves the power consumption and reduces noise at lower regulated output levels. | 06-09-2011 |
20110148509 | Techniques to Reduce Charge Pump Overshoot - A charge pump system for supplying an output voltage to a load is described. The charge pump system includes a charge pump connected to receive an input voltage generate from it the output voltage. The system also includes regulation circuitry connected to receive the output voltage and a reference voltage, where the regulation circuitry is connected to the charge pump to regulate the output voltage based upon the values of the reference voltage and the output voltage. During ramp up or a recovery operation the output voltage is initially regulated according to a first level and subsequently regulated to a second level higher than the first level, the second level corresponding to a desired regulated output voltage. | 06-23-2011 |
20110273227 | Bandgap Voltage and Temperature Coefficient Trimming Algorithm - A circuit and corresponding method for providing a reference voltage are presented. The circuit includes a current source having a magnitude with positive temperature correlation connected to a node, and a diode element connected between the node and ground, where the reference voltage is provided from the node. The circuit also includes a variable resistance connected to receive an input indicative of the circuit temperature and through which the diode element is connected to the node. The value of the variable resistance is adjusted based upon the circuit temperature input. The circuit is useful for application as a peripheral circuitry, such as on a flash or other non-volatile memory and other circuits requiring an on-chip reference voltage source. | 11-10-2011 |
20120008410 | Detection of Word-Line Leakage in Memory Arrays: Current Based Approach - Techniques and corresponding circuitry are presented for the detection of wordline leakage in a memory array. In an exemplary embodiment, a capacitive voltage divider is used to translate the high voltage drop to low voltage drop that can be compared with a reference voltage to determine the voltage drop due to leakage. An on-chip self calibration method can help assure the accuracy of this technique for detecting leakage limit. In other embodiments, the current drawn by a reference array, where a high voltage is applied to the array with all wordlines non-selected, is compared to the current drawn by an array where the high voltage is applied and one or more selected wordlines. In these current based embodiments, the reference array can be a different array, or the same array as that one selected for testing. | 01-12-2012 |
20120081172 | High Voltage Switch Suitable for Use in Flash Memory - A high voltage switch is presented that, rather than relying upon a charge pump to boost the voltage applied to the switches gate in order to compensate for the switch's threshold voltage, a combination of high voltage devices to eliminate the threshold voltage from the switch. This will save on the needed circuit area and reduce the current and, consequently, power consumption. In the exemplary embodiment, the switch circuit passes an input voltage from an input node to an output node in response to an enable signal. The switch includes a level shifter connected to the input node and is connected to receive the enable signal to provide the input voltage as output when the enable signal is asserted. The circuit also includes a first depletion type NMOS transistor that is connected between the input node and a first intermediate node and having a gate connected to receive the output of the level shifter, and a PMOS transistor that is connected between the first intermediate node and the output node and having a gate connected to receive an inverted form of the enable signal. | 04-05-2012 |
20120154023 | Charge Pump Systems with Reduction in Inefficiencies Due to Charge Sharing Between Capacitances - Improvements in the efficiency of two charge pump designs are presented. As a charge pump switches between modes, capacitances are charged. Due to charge sharing between capacitances, inefficiencies are introduced. Techniques for reducing these inefficiencies are presented for two different charge pump designs are presented. For a clock voltage doubler type of pump, a four phase clock scheme is introduced to pre-charge the output nodes of the pump's legs. For a pump design where a set of capacitances are connected in series to supply the output during the charging phase, one or more pre-charging phases are introduced after the reset phase, but before the charging phase. In this pre-charge phase, the bottom plate of a capacitor is set to the high voltage level prior to being connected to the top plate of the preceding capacitor in the series. | 06-21-2012 |
20120275225 | Variable Resistance Switch Suitable for Supplying High Voltage to Drive Load - A circuit for supplying a high voltage to load is described. An example of such a circuit could be used in the peripheral circuitry of a non-volatile memory device for supplying a program voltage from a charge pump to a selected word line. The circuit includes a charge pump that generates the high voltage and decoding circuitry that is connected to receive this high voltage and selectively apply it to a load. The decoding circuitry receives the high voltage through a switch, where the switch is of a variable resistance that progressively passes the high voltage in response to a control signal. In a particular example, the switch includes a transistor connected between the charge pump and the decoding circuitry, where the control gate of the transistor is connected to the output of a second charge pump that is connected to receive the high voltage and a settable clock signal as its inputs. | 11-01-2012 |
20130038381 | Charge Pump Systems with Reduction in Inefficiencies Due to Charge Sharing Between Capacitances - Improvements in the efficiency of two charge pump designs are presented. As a charge pump switches between modes, capacitances are charged. Due to charge sharing between capacitances, inefficiencies are introduced. Techniques for reducing these inefficiencies are presented for two different charge pump designs are presented. For a clock voltage doubler type of pump, a four phase clock scheme is introduced to pre-charge the output nodes of the pump's legs. For a pump design where a set of capacitances are connected in series to supply the output during the charging phase, one or more pre-charging phases are introduced after the reset phase, but before the charging phase. In this pre-charge phase, the bottom plate of a capacitor is set to the high voltage level prior to being connected to the top plate of the preceding capacitor in the series. | 02-14-2013 |
20140043897 | AGGREGATING DATA LATCHES FOR PROGRAM LEVEL DETERMINATION - In a nonvolatile memory array that stores randomized data, the program level—the number of states per cell stored in a population of memory cells—may be determined from the aggregated results of a single read step. A circuit for aggregating binary results of a read step includes parallel transistors with control gates connected to the data latches holding the binary results, so that current flow through the combined transistors depends on the binary results. | 02-13-2014 |
20140084936 | Charge Pump Based Over-Sampling ADC for Current Detection - Techniques are presented for determining current levels based on the behavior of a charge pump system while driving a load under regulation. While driving the load under regulation, the number of pump clocks during a set interval is counted. This can be compared to a reference that can be obtained, for example, from the numbers of cycles needed to drive a known load current over an interval of the duration. By comparing the counts, the amount of current being drawn by the load can be determined. This technique can be applied to determining leakage from circuit elements, such as word lines in a non-volatile memory. | 03-27-2014 |
20140085985 | Sigma Delta Over-Sampling Charge Pump Analog-To-Digital Converter - Techniques are presented for determining current levels based on the behavior of a charge pump system while driving a load under regulation. While driving the load under regulation, the number of pump clocks during a set interval is counted. This can be compared to a reference that can be obtained, for example, from the numbers of cycles needed to drive a known load current over an interval of the duration. By comparing the counts, the amount of current being drawn by the load can be determined. This technique can be applied to determining leakage from circuit elements, such as word lines in a non-volatile memory. The accuracy and level of resolution can be further increased through use of sigma delta noise shaping. | 03-27-2014 |
20140159682 | LDO/HDO Architecture Using Supplementary Current Source to Improve Effective System Bandwidth - An LDO/HDO circuit adds a supplementary current source to supply the output node. The current boosting section includes a digital comparator with a first input connected to the LDO's feedback loop and a second input connected to a reference level. The comparator then generates a digital output used to control the supplementary current source. This approach also can be used in a far-side implementation, where the local supply level for the load is boosted by the current source based a comparison of this local level and the output of the LDO. Miller capacitive compensation is also considered. Current in shunted to ground from a node in the Miller loop, where the level is controlled by the output of a digital comparator base on a comparison of the circuit's output voltage and a reference level. | 06-12-2014 |
20140159683 | Settling Time and Effective Band Width for Op-Amps Using Miller Capacitance Compensation - An LDO/HDO circuit adds a supplementary current source to supply the output node. The current boosting section includes a digital comparator with a first input connected to the LDO's feedback loop and a second input connected to a reference level. The comparator then generates a digital output used to control the supplementary current source. This approach also can be used in a far-side implementation, where the local supply level for the load is boosted by the current source based a comparison of this local level and the output of the LDO. Miller capacitive compensation is also considered. Current in shunted to ground from a node in the Miller loop, where the level is controlled by the output of a digital comparator base on a comparison of the circuit's output voltage and a reference level. | 06-12-2014 |
20140240005 | Pre-Charge Circuit with Reduced Process Dependence - A pre-charging circuit, such as can be used to pre-charge a data bus, is presented that is largely process independent. A push-pull type of arrangement is used, where the output of the pre-charge circuit is initially connected to a supply level through one transistor, then connect to ground by another transistor. These transistors can be controlled by one or more comparators that have as inputs a reference level and feedback from the output. The reference level is generated by a circuit that tracks the threshold voltage of the other devices in the circuit in order to reduce process dependency of the output level. The circuit can also include a device to provide an extra VDD assist to the output. | 08-28-2014 |
20140253057 | Compensation Scheme to Improve the Stability of the Operational Amplifiers - A right-half plane (RHP) zero (RHZ) compensation scheme to improve the stability of the operational amplifier. A resistance R | 09-11-2014 |
20140313836 | High Speed Signaling Techniques to Improve Performance of Integrated Circuits - Techniques are presented to improve the performance, accuracy and power consumption of on-chip voltage biasing and transmission for highly loaded RC networks (such as wordlines or bitlines in NAND or 3D memory arrays) that are otherwise limited by the physics of RC time constant. When transitioning the near-end voltage of the network, an under-drive or over-drive level is applied, combined with feedback control to estimate when the far-end voltage approaches the desired level. | 10-23-2014 |
20140368262 | Efficient Voltage Doubler - A charge pump circuit using a voltage doubler-type of circuitry for generating an output voltage is described. An output generating stage uses a voltage double structure, except that the transistors in each leg are not cross-coupled to the other leg, but instead are controlled by an auxiliary section. The auxiliary section has a voltage doubler structure, but is not used to drive the load, but instead provides the gate voltage for the precharge section using the same levels as used for the corresponding transistors in the auxiliary section. This arrangement can be particularly advantageous for applications using low supply voltages to address self-loading effect due to loading. As the auxiliary section does not drive the load, its elements can be sized smaller. Additional improvement can be obtained by using separate clock drivers for the auxiliary section to address secondary self-loading effect due to loading. | 12-18-2014 |
20140375293 | Capacitive Regulation of Charge Pumps Without Refresh Operation Interruption - In a charge pump system using a capacitive voltage divider, or other feedback circuit requiring periodic refreshing, in order to refresh the circuit, system operations would typically need to be suspended in order to refresh the capacitors if charge leakage begins to affect the output level. This can lead to delay and power inefficiencies. To overcome this, two feedback circuits are used so that while one is active, the other can have its capacitors' state refreshed. By alternating the two networks, delay can be avoided and power use reduced. | 12-25-2014 |
20150023100 | Dynamic Regulation of Memory Array Source Line - To maintain stability of memory array operations, a current source supplies a common source line of a memory. The magnitude of the regulation current from the source is dynamically determined based on the amount of current from the array itself through use of a feedback control signal provided by a current comparator circuit. The current comparison circuit can use either a digital or an analog implementation. | 01-22-2015 |