Patent application number | Description | Published |
20090144145 | MOBILE ADVERTISEMENT METHOD - The present invention relates to a mobile advertising method that performs mobile advertisement using a deep-packet inspection performed in a wireless Internet system and location information. An exemplary embodiment of the present invention includes grasping a purchasing tendency of a subscriber using deep packet inspection of an electronic surveillance system; and providing advertisement for desired goods to the subscriber by connecting the grasped purchasing tendency of the subscriber with a location-based service (LBS). Accordingly, the present invention can contribute to an increase in sales profits of the service provider to reduce the resistance and burden for the installation of the electronic surveillance system, and maximize the advertising effect of the advertiser. Further, the subscriber can receive required information on the basis of the current location. | 06-04-2009 |
20090158426 | TRACEBACK METHOD AND SIGNAL RECEIVING APPARATUS - The present invention provides a traceback method including: receiving data including router information according to a path of an attacker; filtering the data to hash the data, and storing the resultant hashed information; determining whether the data is normally received on the basis of the hashed information; and predicting a path loss on the basis of the determination result. Therefore, it is possible to perform an accurate IP traceback using a probabilistic packing marking method and a hash-based traceback method. | 06-18-2009 |
20100328448 | UNDERWATER CCD CAMERA FOR VISUAL TESTING OF REACTOR COOLING SYSTEM - Disclosed is an underwater CCD camera for visual testing of a reactor cooling system. The underwater CCD camera includes a CCD camera, a casing having a supporter supporting the CCD camera and a cooling pin on a top surface thereof, a Pb-glass window on a front side of the easing to shield the CCD camera from radiation and to reduce a temperature difference between the interior and exterior of the casing, a sealing O-ring preventing a coolant from being introduced into a gap between the Pb-glass window and the casing, a sealing nut providing a fastening force to bring the Pb-glass window into close contact with the sealing O-ring, a rear cap, a silicon O-ring preventing the coolant from being introduced into a gap between the rear cap and the casing, and a fastening nut providing a fastening force to prevent leakage between a camera cable and the casing. | 12-30-2010 |
20110153108 | METHOD AND DEVICE FOR REMOTE POWER MANAGEMENT - Provided is a method for remote power management capable of remotely controlling power consumption. The method for remote power management includes: allowing a power management device to generate power information on the basis of power consumption information collected from at least one electronic apparatus and transmit the generated power information to a user terminal through a wireless communication network; and to control an operation of the at least one electronic apparatus in accordance with a control command transmitted in response to the power information from the user terminal through the wireless communication network. | 06-23-2011 |
Patent application number | Description | Published |
20080284381 | PORTABLE ELECTRONIC DEVICE INCLUDING ELECTRIC GENERATOR - A portable electronic device includes a case; a revolution body rotatable with respect to the case; an electric generator converting rotational kinetic energy of the revolution body into electrical energy; a gear assembly transferring rotational force of the revolution body to the electric generator, and including at least one gear; and a secondary cell storing the electrical energy generated by the electric generator. | 11-20-2008 |
20090097447 | METHOD AND APPARATUS FOR ALLOCATING RESOURCES OF A CONTROL CHANNEL IN A MOBILE COMMUNICATION SYSTEM USING ORTHOGONAL FREQUENCY DIVISION MULTIPLEXING - A method is provided for allocating resources of a control channel in a mobile communication system using Orthogonal Frequency Division Multiplexing (OFDM). The method includes, when a time index and a frequency index of available Resource Elements (REs) are defined as l and k, respectively, dividing the available REs in a two-dimensional structure of (k, l); and time-first-allocating each RE to a plurality of RE groups while increasing the time index l for each frequency index k from an initial value up to a predetermined range. | 04-16-2009 |
20090231202 | ANTENNA STRUCTURE - An antenna structure of an information communication terminal, the antenna structure including: a frame having a three dimensional shape; an antenna pattern formed in the frame; and a circuit lumped element mounted on a surface of the antenna pattern. In the antenna structure, an antenna is directly provided on the frame such that a sufficient antenna characteristic can be ensured in a small space, thereby realizing a slim and miniaturized information communication terminal. | 09-17-2009 |
20120263143 | METHOD AND APPARATUS FOR ALLOCATING RESOURCES OF A CONTROL CHANNEL IN A MOBILE COMMUNICATION SYSTEM USING ORTHOGONAL FREQUENCY DIVISION MULTIPLEXING - A method is provided for allocating resources of a control channel in a mobile communication system using Orthogonal Frequency Division Multiplexing (OFDM). The method includes, when a time index and a frequency index of available Resource Elements (REs) are defined as | 10-18-2012 |
Patent application number | Description | Published |
20150163776 | METHOD AND APPARATUS FOR ALLOCATING RESOURCES OF A CONTROL CHANNEL IN A MOBILE COMMUNICATION SYSTEM USING ORTHOGONAL FREQUENCY DIVISION MULTIPLEXING - Methods and apparatuses are provided for wireless communication. Control symbols are mapped to a plurality of resource element groups (REGs) which is not assigned to a physical channel format indication channel (PCFICH) or a physical hybrid automatic repeat request indicator channel (PHICH). The REGs are allocated based on a time first manner. The mapped control symbols are transmitted on a packet dedicated control channel (PDCCH). A number of a plurality of resource elements (REs) in each of the REGs depends on an index of an orthogonal frequency division multiplexing (OFDM) symbol and a number of configured reference signals. | 06-11-2015 |
20150163777 | METHOD AND APPARATUS FOR ALLOCATING RESOURCES OF A CONTROL CHANNEL IN A MOBILE COMMUNICATION SYSTEM USING ORTHOGONAL FREQUENCY DIVISION MULTIPLEXING - Methods and apparatuses are provided for wireless communication. Control symbols are mapped to a plurality of resource element groups (REGs) which is not assigned to a physical channel format indication channel (PCFICH) or a physical hybrid automatic repeat request indicator channel (PHICH). The REGs are allocated based on a time first manner. The mapped control symbols are transmitted on a packet dedicated control channel (PDCCH). A number of the REGs in a physical resource block (PRB) on an orthogonal frequency division multiplexing (OFDM) symbol depends on an index of the OFDM symbol and a number of configured reference signals. | 06-11-2015 |
20150163778 | METHOD AND APPARATUS FOR ALLOCATING RESOURCES OF A CONTROL CHANNEL IN A MOBILE COMMUNICATION SYSTEM USING ORTHOGONAL FREQUENCY DIVISION MULTIPLEXING - Methods and apparatuses are provided for wireless communication. Control symbols are mapped to a plurality of resource element groups (REGs) which is not assigned to a physical channel format indication channel (PCFICH) or a physical hybrid automatic repeat request indicator channel (PHICH). The mapped control symbols are transmitted on a packet dedicated control channel (PDCCH). A number of a plurality of resource elements (REs) in each of the REGs depends on an index of an orthogonal frequency division multiplexing (OFDM) symbol and a number of configured reference signals. A number of the REGs in a physical resource block (PRB) on an OFDM symbol depends on the index of the OFDM symbol and the number of configured reference signals. | 06-11-2015 |
20150163787 | METHOD AND APPARATUS FOR ALLLOCATING RESOURCES OF A CONTROL CHANNEL IN A MOBILE COMMUNICATION SYSTEM USING ORTHOGONAL FREQUENCY DIVISION MULTIPLEXING - Methods and apparatuses are provided for wireless communication. Control symbols are mapped to a plurality of resource element groups (REGs) which is not assigned to a physical channel format indication channel (PCFICH) or a physical hybrid automatic repeat request indicator channel (PHICH). The mapped control symbols are transmitted on a packet dedicated control channel (PDCCH). A physical resource block (PRB) on a second orthogonal frequency division multiplexing (OFDM) symbol in a first slot in a subframe includes three REGs if one or two cell-specific reference signals are configured, and the PRB on the second OFDM symbol of the first slot in the subframe includes two REGs if four cell-specific reference signals are configured. | 06-11-2015 |
20150201407 | METHOD AND APPARATUS FOR ALLOCATING RESOURCES OF A CONTROL CHANNEL IN A MOBILE COMMUNICATION SYSTEM USING ORTHOGONAL FREQUENCY DIVISION MULTIPLEXING - Methods and apparatuses are provided for wireless communication. Control symbols are mapped to a plurality of resource element groups (REGs), which are not assigned to a physical channel format indication channel (PCFICH) or a Physical hybrid automatic repeat request indicator channel (PHICH). The REGs are allocated in a time first manner. The mapped control symbols are transmitted on a packet dedicated control channel (PDCCH). Each of the REGs in a first orthogonal frequency division multiplexing (OFDM) symbol of a first slot in a subframe comprises two resource elements (REs) for transmission of a cell-specific reference signal and four REs for transmission of a control signal. | 07-16-2015 |
Patent application number | Description | Published |
20090027979 | Semiconductor memory device and data sensing method thereof - A semiconductor memory device includes first and second edge drivers configured to generate sensing control signals, a memory cell array between first and second edge drivers, and pluralities of unit sense amplifiers detecting data from the memory cell array in response to the sensing control signals. | 01-29-2009 |
20090116297 | Redundancy program circuit and methods thereof - A redundancy program circuit and methods thereof. The redundancy program circuit may include a master fuse circuit with a master fuse outputting an operation enable signal to indicate a master fuse operating status, at least one control fuse circuit including at least one control fuse, the at least one control fuse circuit outputting an operating status signal for the at least one control fuse and a multiplexing unit configured to multiplex decoding address signal bits based on at least one of the operating status signal and the operation enable signal. | 05-07-2009 |
20090116319 | Redundancy program circuit and methods thereof - A redundancy program circuit and methods thereof. The redundancy program circuit may include a master fuse circuit with a master fuse outputting an operation enable signal to indicate a master fuse operating status, at least one control fuse circuit including at least one control fuse, the at least one control fuse circuit outputting an operating status signal for the at least one control fuse and a multiplexing unit configured to multiplex decoding address signal bits based on at least one of the operating status signal and the operation enable signal. | 05-07-2009 |
20090116327 | Redundancy program circuit and methods thereof - A redundancy program circuit and methods thereof. The redundancy program circuit may include a master fuse circuit with a master fuse outputting an operation enable signal to indicate a master fuse operating status, at least one control fuse circuit including at least one control fuse, the at least one control fuse circuit outputting an operating status signal for the at least one control fuse and a multiplexing unit configured to multiplex decoding address signal bits based on at least one of the operating status signal and the operation enable signal. | 05-07-2009 |
20100226187 | Semiconductor memory device - A semiconductor memory device includes a memory cell array having a plurality of memory cells coupled between a plurality of word lines and a plurality of bit line pairs, a bit line selection circuit configured to transmit data between a selected bit line pair and a local input/output line pair in response to a column selection signal, a local global input/output gate circuit configured to transmit data between the local input/output line pair and a global input/output line pair in response to a local global input/output selection signal, and a controller configured to drive the word lines, output the column selection signal having a first voltage level to the bit line selection circuit, and output the local global input/output selection signal having a second voltage level that is lower than the first voltage level to the local global input/output gate circuit, in response to an external address signal and an external command. | 09-09-2010 |
20110267915 | ANTI-FUSE, ANTI-FUSE CIRCUIT INCLUDING THE SAME, AND METHOD OF FABRICATING THE ANTI-FUSE - Provided are an anti-fuse, an anti-fuse circuit, and a method of fabricating the anti-fuse. The anti-fuse includes a semiconductor substrate, an isolation region, a channel diffusion region, a gate oxide layer, and a gate electrode. The semiconductor substrate includes a top surface and a bottom portion, the bottom portion of the semiconductor substrate having a first conductivity type. The isolation region is disposed inward from the top surface of the semiconductor substrate to a first depth. The channel diffusion region is disposed inward from the top surface of the semiconductor substrate to a second depth, the second depth located at a depth where the channel diffusion region meets an upper boundary of the bottom portion of the semiconductor substrate. The channel diffusion region is surrounded by the isolation region, the first depth is a greater distance from the top surface of the semiconductor substrate than the second depth, and the channel diffusion region has a second conductivity type opposite to the first conductivity type. The gate oxide layer is disposed on the channel diffusion region, and the gate electrode is disposed on the gate oxide layer to cover a top surface of the gate oxide layer. | 11-03-2011 |
20110292708 | 3D SEMICONDUCTOR DEVICE - A three-dimensional (3D) semiconductor device may include a stack of chips, including a master chip and one or more slave chips. I/O connections of slave chips need not be connected to channels on a motherboard, and only electrode pads of a master chip may be connected to the channels. Only the master chip may provide a load to the channels. A through-substrate via (TSV) boundary may be set on a data input path, a data output path, an address/command path, and/or a clock path of a semiconductor device in which the same type of semiconductor chips are stacked. | 12-01-2011 |
20120039140 | FUSE CIRCUIT AND SEMICONDUCTOR MEMORY DEVICE INCLUDING THE SAME - A fuse circuit includes a program unit, a sensing unit and a control unit. The program unit is programmed in response to a program signal, and outputs a program output signal in response to a sensing enable signal. The sensing unit includes a variable resistor unit that has a resistance that varies based on a control signal, and generates a sensing output signal based on the resistance of the variable resistor unit and the program output signal. The control unit generates the control signal having a value changed depending on operation modes, and performs a verification operation with respect to the program unit based on the sensing output signal to generate a verification result. The program unit may be re-programmed based on the verification result. | 02-16-2012 |
20120120733 | SEMICONDUCTOR DEVICE INCLUDING FUSE ARRAY AND METHOD OF OPERATION THE SAME - Provided are a semiconductor device including a fuse and a method of operating the same. The semiconductor device includes a fuse array, a first register unit, and a second register unit. The fuse array includes a plurality of rows and columns. The first register unit receives at least one row of fuse data from the fuse array. Fuse data of the at least one row of fuse data is received in parallel by the first register unit. The second register unit receives the fuse data at least one bit at a time from the first register unit. | 05-17-2012 |
20130003477 | SEMICONDUCTOR MEMORY DEVICE INCLUDING SPARE ANTIFUSE ARRAY AND ANTIFUSE REPAIR METHOD OF THE SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device including an antifuse cell array and a spare antifuse cell array are provided. An antifuse cell array includes a first set of antifuse cells arranged in a first direction and each one of the first set of antifuse cells is connected to a corresponding one of first through nth word lines. The spare antifuse cell array includes a first spare set of antifuse cells arranged in the first direction and each one of the first spare set of antifuse cells is connected to a corresponding one of first through kth spare word lines. A first operation control circuit is configured to program antifuses of the antifuse cell array and the spare antifuse cell array, and to read a status of each of the antifuses. The first operation control circuit is commonly connected to the first set of antifuse cells and the first spare set of antifuse cells. | 01-03-2013 |
20130061102 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device including a data bus inversion (DBI) determination unit, a first inverter, a cyclic redundancy check (CRC) calculation unit, a second inverter, and a DQ pin. The DBI determination unit is configured to determine whether to perform DBI based on first data on a main data line and configured to generate DBI data. The first inverter is configured to invert or non-invert the first data according to the DBI data to generate second data. The CRC calculation unit is configured to generate CRC data based on the second data and the DBI data. The second inverter is configured to invert or non-invert the first data according to the DBI data to generate third data. The DQ pin is configured to output the third data externally. | 03-07-2013 |
20140233292 | 3D SEMICONDUCTOR DEVICE - A three-dimensional (3D) semiconductor device may include a stack of chips, including a master chip and one or more slave chips. I/O connections of slave chips need not be connected to channels on a motherboard, and only electrode pads of a master chip may be connected to the channels. Only the master chip may provide a load to the channels. A through-substrate via (TSV) boundary may be set on a data input path, a data output path, an address/command path, and/or a clock path of a semiconductor device in which the same type of semiconductor chips are stacked. | 08-21-2014 |