Patent application number | Description | Published |
20080240719 | METHOD AND APPARATUS FOR ESTABLISHING SYSTEM DELAY TIME AND FRAME LENGTH IN TIME DIVISION DUPLEXING SYSTEM - A method of establishing a system delay time and a frame length in a Time Division Duplexing (TDD) system includes adjusting time lengths of an uplink (UL) frame, a downlink (DL) frame, a Transmit/receive Transition Gap (TTG), and a Receive/transmit Transition Gap (RTG); a Base Station (BS) transmitting a DL frame and receiving a UL frame; and a Mobile Station (MS) receiving the DL frame and transmitting the UL frame. | 10-02-2008 |
20080265764 | DISPLAY DEVICE AND METHOD AND APPARATUS FOR MANUFACTURING THE SAME - A display device includes a first substrate, a second substrate and a blocking member. The first substrate has a light emitting element. The second substrate faces the first substrate. The blocking member is arranged between the first and second substrates. The blocking member includes a first blocking layer and a second blocking layer. | 10-30-2008 |
20110104591 | Methods of Fabricating Halftone Phase Shift Blank Photomasks and Halftone Phase Shift Photomasks - Halftone phase shift photomasks are provided including a substrate configured to transmit light; a shift pattern on the substrate, the shift pattern including a pattern area on a center portion of the substrate and a blind area disposed on a periphery of the substrate, the shift pattern of the blind area having a greater thickness than a thickness that of the pattern area, and being configured to partially transmit the light; and a light shielding pattern formed on the shift pattern in the blind area and being configured to shield the light. Related methods are also provided herein. | 05-05-2011 |
20120217254 | Refrigerator - A refrigerator which provides a grocery manager interface through a display so that storage locations and periods and best before periods of foods stored in the refrigerator are easily judged, thereby effectively managing the stored foods. The refrigerator includes storage chambers to store foods, a display unit having a touch screen function, and a grocery manage interface to display food items corresponding to the foods stored in the storage chambers and to manage the displayed food items using a drag and drop method. | 08-30-2012 |
20120221123 | ELECTRICAL INSTRUMENT AND CONTROLLING CONTROL METHOD THEREOF - A method of controlling an electrical instrument to which a user inputs a reservation time using a rotary dial includes, upon reception of power rates by time periods from a power provider, confirming power rate levels by time periods based on the received power rates, displaying a color window including the power rate levels by time periods around the rotary dial, and displaying the reservation time input by the user through the rotary dial on the clock window. Accordingly, it is possible to provide a user interface that displays power rate information by time periods such that the user intuitively recognizes the power rate information and sets a reservation time on the basis of the power rate information. | 08-30-2012 |
20120230263 | WIRELESS NETWORK CHANNEL ALLOCATION METHOD FOR INTERFERENCE AVOIDANCE - A wireless network channel allocation method for interference avoidance in a wireless network includes determining whether some or all of the one or more channels are used by other sources, if some or all of the one or more channels are used by other sources, determining whether one of channels used by other sources is currently used by the wireless network, if one of the channels used by other sources is currently used by the wireless network, switching the channel currently used by the wireless network to any one of the one or more channels except for the channel currently used by the wireless network, and if one of the channels used by other sources is not currently used by the wireless network, storing information about the channels used by the other sources, wherein the switched channel is a channel which is not most recently used by other sources according to the stored information. | 09-13-2012 |
20120230378 | MODEM FOR NETWORK SYSTEM AND OPERATING METHOD THEREOF - A modem for network system which is mounted in an electric home appliance to communicate with an external service device, to which an additional modem may be connected, and to which one or more electric home appliances may be connected and an operating method thereof. The modem has a plurality of input/output ports, functions of which are changed using a switch so that an additional modem or an electric home appliance is connected to the modem. When two modems using the same interface are connected to an electric home appliance, connection of the modems to the electric home appliance is easily achieved via the existing ports without adding a new input/output interface to the electric home appliance. Also, when one or more electric home appliances jointly use a modem, additional connection of the electric home appliances is achieved using a switch without using an additional distributor. | 09-13-2012 |
20120237860 | REFLECTIVE EXTREME ULTRAVIOLET MASK AND METHOD OF MANUFACTURING THE SAME - A reflective EUV mask and a method of manufacturing the same, the reflective EUV mask including a mask substrate having an exposing region and a peripheral region, the mask substrate including a light scattering crystalline portion that scatters light incident to the peripheral region and that decreases reflectivity of the peripheral region; a reflective layer on an upper surface of the mask substrate, the reflective layer having a first opening that exposes the crystalline portion; and an absorbing layer pattern on an upper surface of the reflective layer, the absorbing layer pattern having a second opening in fluidic communication with the first opening. | 09-20-2012 |
20130101926 | Halftone Phase Shift Blank Photomasks and Halftone Phase Shift Photomasks - Halftone phase shift photomasks are provided including a substrate configured to transmit light; a shift pattern on the substrate, the shift pattern including a pattern area on a center portion of the substrate and a blind area disposed on a periphery of the substrate, the shift pattern of the blind area having a greater thickness than a thickness that of the pattern area, and being configured to partially transmit the light; and a light shielding pattern formed on the shift pattern in the blind area and being configured to shield the light. Related methods are also provided herein. | 04-25-2013 |
20130283721 | STEEL FRAME STRUCTURE USING U-SHAPED COMPOSITE BEAM - A steel frame structure includes brackets connected to columns to allow the columns to be connected to a girder. Each bracket includes a U-shaped plate having a bottom plate, side plates extended upwardly perpendicularly from both ends of the bottom plate, and base plates extended outwardly from the side plates, a vertical plate welded perpendicularly to the center of the bottom plate of the U-shaped plate in such a manner as to be parallel to the side plates, and a horizontal plate welded to the top end of the vertical plate in such a manner as to be parallel to the bottom plate of the U-shaped plate. The girder has a generally U-shaped section. | 10-31-2013 |
20150212433 | PELLICLE - A pellicle includes a first frame affixing a reticle, the first frame having a tapered locking groove, a second frame on the first frame, the second frame having a locking portion that is detachably combined with the tapered locking groove of the first frame, and a membrane affixed to the second frame. | 07-30-2015 |
Patent application number | Description | Published |
20090151441 | TIRE PRESSURE ADJUSTING SYSTEM OF VEHICLE AND METHOD OF CONTROLLING THE SAME - A tire pressure adjusting system of a vehicle includes: a sensor mounted in a tire, to measure pressure and/or temperature of air in the tire, and to send a signal corresponding to the pressure and/or temperature; a magnetic field generator mounted on the vehicle body near the tire, to receive the signal from the sensor, and to generate a magnetic field; a current generator mounted in the tire, to generate electricity by using the magnetic field; and an electric heating member mounted in the tire, to generate heat by using the electricity supplied from the current generator, thereby heating the air in the tire. A method of controlling tire pressure includes determining whether the pressure is too low; and, if the pressure is too low, heating air in the tire until the pressure is not too low. | 06-18-2009 |
20090160991 | UNIT PIXEL FOR USE IN CMOS IMAGE SENSOR - A unit pixel of a CMOS image sensor includes one PMOS for receiving light and generating electric signals and one NMOS that outputs the signals applied from the PMOS. Therefore, the pitch size of the pixel itself can be reduced, and the whole area by the image sensor can be also reduced. The present unit pixel improves image embodying characteristics even at low illumination, and does not require integration time, thereby enabling production of a moving picture at high speed. Further, the present unit pixel of the image sensor is formed using only a simple MOS process, which dramatically simplifies the fabrication steps. Therefore, process yield can be improved, while production cost savings can be realized. According to the present discussion, the unit pixel of a CMOS image sensor formed on a P type semiconductor substrate, includes an N type doped well, a PMOS for receiving light and generating electric signals, and an NMOS for outputting the signals from the PMOS. | 06-25-2009 |
20090170248 | METHOD FOR MANUFACTURING THIN FILM TRANSISTOR - A method for manufacturing a thin film transistor with improved current characteristics and high electron mobility. According to the method, when an amorphous silicon thin film is crystallized into a polycrystalline silicon thin film by metal-induced crystallization, annealing conditions of the amorphous silicon thin film and the amount of a metal catalyst doped into the amorphous silicon thin film are optimized to reduce the regions of a metal silicide distributed at grain boundaries of the polycrystalline silicon thin film. In addition, oxygen (O | 07-02-2009 |
20090219427 | IMAGE SENSOR AND IMAGE DATA PROCESSING METHOD - An image sensor and a method for processing image data, can reduce a large proportion of data signals corresponding to high illumination and a small proportion of data signals corresponding to low illumination in order to generate an image just like the original, by adjusting the reset sampling period pertaining to the data signals outputted from a unit pixel. The image sensor includes a first switch which is operated by a reset sampling signal for sampling reset voltage when a voltage drop in an image data signal occurs, in which the image data signal is applied from a picture element part, a first capacitor for storing the reset voltage applied from the first switch, a second switch which is operated by a data sampling signal for sampling data voltage after completion of the voltage drop in the image data signal, a second capacitor for storing the data voltage from the second switch, and an image data processing circuit equipped with a comparator for comparing the reset voltage with the data voltage. | 09-03-2009 |
20130056708 | UNIT PIXEL OF IMAGE SENSOR AND PHOTO DETECTOR THEREOF - A unit pixel of an image sensor and a photo detector are disclosed. The photo detector of the present invention configured to absorb light can include: a light-absorbing part configured to absorb light by being formed in a floated structure; an oxide film being in contact with one surface of the light-absorbing part; a source being in contact with one side of the other surface of the oxide film and separated from the light-absorbing part with the oxide film therebetween; a drain facing the source so as to be in contact with the other side of the other surface of the oxide film and separated from the light-absorbing part with the oxide film therebetween; and a channel interposed between the source and the drain and configured to form flow of an electric current between the source and the drain. | 03-07-2013 |
20130056709 | UNIT PIXEL OF IMAGE SENSOR AND PHOTO DETECTOR THEREOF - A unit pixel of an image sensor and a photo detector are disclosed. The photo detector can include: a substrate in which a V-shaped groove having a predetermined angle is formed; a light-absorbing part formed in a floated structure above the V-shaped groove and to which light is incident; an oxide film formed between the light-absorbing part and the V-shaped groove and in which tunneling occurs; a source formed adjacent to the oxide film on a slope of one side of the V-shaped groove and separated from the light-absorbing part by the oxide film; a drain formed adjacent to the oxide film on a slope of the other side of the V-shaped groove and separated from the light-absorbing part by the oxide film; and a channel interposed between the source and the drain along the V-shaped groove to form flow of an electric current between the source and the drain. | 03-07-2013 |
20130056806 | UNIT PIXEL OF COLOR IMAGE SENSOR AND PHOTO DETECTOR THEREOF - A unit pixel of an image sensor and a photo detector are disclosed. The photo detector of the present invention can include: a light-absorbing part configured to absorb light by being formed in a floated structure; an oxide film having one surface thereof being in contact with the light-absorbing part; a source being in contact with one side of the other surface of the oxide film and separated from the light-absorbing part with the oxide film therebetween; a drain facing the source so as to be in contact with the other side of the other surface of the oxide film and separated from the light-absorbing part with the oxide film therebetween; and a channel formed between the source and the drain and configured to form flow of an electric current between the source and drain. | 03-07-2013 |
20140021519 | UNIT PIXEL OF IMAGE SENSOR AND PHOTO DETECTOR THEREOF - A unit pixel of an image sensor and a photo detector are disclosed. The photo detector of the present invention configured to absorb light can include: a light-absorbing part configured to absorb light by being formed in a floated structure; an oxide film being in contact with one surface of the light-absorbing part; a source being in contact with one side of the other surface of the oxide film and separated from the light-absorbing part with the oxide film therebetween; a drain facing the source so as to be in contact with the other side of the other surface of the oxide film and separated from the light-absorbing part with the oxide film therebetween; and a channel interposed between the source and the drain and configured to form flow of an electric current between the source and the drain. | 01-23-2014 |
20140027829 | UNIT PIXEL OF IMAGE SENSOR AND PHOTO DETECTOR THEREOF - A unit pixel of an image sensor and a photo detector are disclosed. The photo detector of the present invention configured to absorb light can include: a light-absorbing part configured to absorb light by being formed in a floated structure; an oxide film being in contact with one surface of the light-absorbing part; a source being in contact with one side of the other surface of the oxide film and separated from the light-absorbing part with the oxide film therebetween; a drain facing the source so as to be in contact with the other side of the other surface of the oxide film and separated from the light-absorbing part with the oxide film therebetween; and a channel interposed between the source and the drain and configured to form flow of an electric current between the source and the drain. | 01-30-2014 |
20140355588 | HOME APPLIANCE AND HOME NETWORK SYSTEM USING THE SAME - A home network system has a home appliance, a portable terminal to receive a control command associated with the home appliance, and an access point to allow the home appliance or the portable terminal to be connected to a wide area network (WAN), wherein the access point notifies the home appliance of the connection of the portable terminal if the portable terminal connects to the access point, so that the home application detects that a user returns home and performs a certain operation as a user connects to the access point when returning home. | 12-04-2014 |
20150038103 | HOME APPLIANCE AND CONTROL METHOD THEREOF - A control method of a home appliance, the method including retrieving information about a communication device, authenticating the communication device, registering the authenticated communication device, receiving voice data from the registered communication device, outputting a voice signal corresponding to the received voice data to a user, receiving the voice signal from the user, and transmitting voice data corresponding to the received voice signal to the communication device. When the method is used, even if a user loses a communication device in a home, call is possible using a home appliance such as refrigerator. | 02-05-2015 |
Patent application number | Description | Published |
20110187629 | FLAT PANEL DISPLAY APPARATUS AND ORGANIC LIGHT-EMITTING DISPLAY APPARATUS - A flat panel display apparatus includes a substrate; a display unit which is formed on the substrate and displays an image; a metal sheet which faces towards the substrate; a sealant which fills the entire free space between the substrate and the metal sheet and seals the space between the substrate and the metal sheet; and a polymer layer which is disposed on a surface of the metal sheet and has a lower thermal expansion coefficient than the metal sheet. An organic light-emitting display (OLED) apparatus including a sealant which fills an entire space between a substrate and a metal sheet is also disclosed. | 08-04-2011 |
20110206887 | LAMINATION SHEET AND METHOD FOR MANUFACTURING THE SAME - A lamination sheet includes a base film; a laminated material layer applied on the base film; and a cover film disposed on the laminated material layer, wherein the laminated material layer is interposed between the base film and the cover film and one edge of the base film comprising a base film removing tab extending beyond one edge of the laminated material layer and the base film removing tab not overlapping the laminated material layer; one edge of the cover film comprising a cover film removing tab extending beyond one edge of the laminated material layer and the cover film removing tab not overlapping the laminated material layer; and at least a part of the base film removing tab is formed not to overlap the cover film removing tab. A method for manufacturing a lamination sheet is also provided. | 08-25-2011 |
20110248907 | DISPLAY APPARATUS - A display apparatus having an improved function for encapsulating a display unit, and comprising a substrate, wherein the display unit is disposed on the substrate; an encapsulation unit facing the display unit, the encapsulation unit comprising: a metal layer; and a composite member; and a sealing unit disposed between the substrate and the encapsulation unit and separated from the display unit so as to adhere the substrate to the encapsulation unit, wherein the composite member comprises a resin matrix and carbon fibers, and wherein the metal layer is disposed between the substrate and the composite member. | 10-13-2011 |
20110273077 | ORGANIC LIGHT EMITTING DISPLAY DEVICE AND METHOD OF MANUFACTURING THE SAME - Provided is an organic light emitting device, which is flexible and is capable of effectively preventing permeation of oxygen or moisture. The organic light emitting device includes a substrate; a metal sheet that faces the substrate; an organic light emitting unit that is interposed between the substrate and the metal sheet; an adhesive unit that is interposed between the substrate and the metal sheet to adhere the substrate and the metal sheet to each other and that is located around at least the organic light emitting unit; and an adhesive layer that is formed at a location on the metal sheet where the metal sheet contacts the adhesive unit and that is formed of a metal oxide or a metal nitride. | 11-10-2011 |
20120112212 | ORGANIC LIGHT EMITTING DIODE DISPLAY AND METHOD OF MANUFACTURING THE SAME - An organic light emitting diode (OLED) display is disclosed. In one embodiment, the OLED display includes first and second substrates, an OLED interposed between the first and second substrates and an external sealant formed between the first and second substrates and configured to i) substantially seal the first and second substrates and ii) substantially surround the OLED. The OLED display may further include a dam formed between the external sealant and the OLED and configured to substantially surround the OLED, and a getter formed between the external sealant and the dam. | 05-10-2012 |
20120146059 | Organic light emitting diode display - An organic light emitting diode (OLED) display includes: a substrate; an organic light emitting diode disposed on the substrate; a sealing member sealed with the substrate, interposing the organic light emitting diode therebetween; a pad portion disposed on the substrate, corresponding to an edge of the sealing member, and electrically connected with the organic light emitting diode; a conductive line portion formed on the sealing member and/or on the substrate, and applied with driving power supplied to the organic light emitting diode; and a conductive connection portion directly connecting the pad portion and the conductive line portion. | 06-14-2012 |
20120146487 | Organic Light Emitting Diode Display, Manufacturing Method and Manufacturing Equipment Thereof - A method for manufacturing an OLED display according to an exemplary embodiment comprises: forming a thermosetting adhesive layer having a getter receiving portion on a metal sheet; forming a display unit including a plurality of pixels on a substrate; forming a getter layer at an external side of the display unit on the substrate; adhering the thermosetting adhesive layer and the metal sheet to the substrate so as to locate the getter layer in the getter receiving unit; and hardening the thermosetting adhesive layer. The forming of the thermosetting adhesive layer includes layering a solid thermosetting adhesive sheet which has been patterned so as to have the getter receiving portion on the metal sheet. | 06-14-2012 |
20120161619 | ENCAPSULATION SHEET, FLAT PANEL DISPLAY DEVICE USING THE SAME, AND METHOD OF MANUFACTURING THE FLAT PANEL DISPLAY DEVICE - An encapsulation sheet, a flat panel display device, and a method of manufacturing a flat panel display device are disclosed. The method includes: forming a getter on a first sheet; forming a sealant having a space corresponding to the shape of the getter on a second sheet; forming an encapsulation sheet by folding the first sheet and the second sheet to enter the getter into the space; and attaching the encapsulation sheet on a substrate on which a display unit is formed. When the flat panel display device is manufactured using the above method, the folded sealant and the getter are simultaneously mounted on the substrate, and thus, a complicated conventional process of mounting the getter in a vacuum state is unnecessary. | 06-28-2012 |
20120169216 | ORGANIC LUMINESCENCE DISPLAY DEVICE HAVING GETTER PATTERN AND METHOD OF MANUFACTURING THE SAME - Provided is a method of manufacturing an organic luminescence display device, the method including: bringing a getter powder into direct contact with a first surface of an encapsulation substrate; irradiating a laser to a second surface of the encapsulation substrate correspondingly to a getter pattern area to melt the second surface of the encapsulation substrate; and bonding the getter powder to the molten second surface of the encapsulation substrate to form a getter pattern corresponding to the getter pattern area. Since the getter powder is directly bonded to the encapsulation substrate by laser irradiation, a fine getter pattern may be formed. | 07-05-2012 |
20120313499 | ORGANIC LIGHT EMITTING DIODE DISPLAY - Provided is an organic light emitting diode (OLED) display including: a substrate; an organic light emitting element disposed on the substrate; an encapsulation substrate disposed on the organic light emitting element; and an adhesive layer disposed on the substrate to cover the organic light emitting element and bonding the substrate including the organic light emitting element disposed therein with the encapsulation substrate. Herein, the adhesive layer is formed by laminating a filling adhesive sheet including at least one opening that is open in a vertical direction in a thickness of the adhesive layer with a heat dissipation adhesive sheet filling the opening, or by laminating a heat dissipation adhesive sheet including at least one opening that is open in a vertical direction in a thickness of the adhesive layer with a filling adhesive sheet filling the opening. | 12-13-2012 |
20120313508 | ORGANIC LIGHT EMITTING DIODE DISPLAY - Disclosed is an organic light emitting diode (OLED) display comprising a substrate; an organic light emitting element disposed on the substrate; an encapsulation substrate disposed on the organic light emitting element; and an adhesive layer formed on the substrate, covering the organic light emitting element, and bonding the substrate on which the organic light emitting element is formed with the encapsulation substrate. | 12-13-2012 |
20120326194 | ORGANIC LIGHT EMITTING DIODE DISPLAY AND MANUFACTURING METHOD THEREOF - An OLED display according to an exemplary embodiment includes: a substrate; an organic light emitting diode formed on the substrate; an overcoat covering the organic light emitting diode; and a patterned metal sheet attached on the overcoat and having a plurality of protrusion and depression portions. A plurality of protrusions may be formed in a bottom surface of the patterned metal sheet where the protrusion and depression portions of the patterned metal sheet and the overcoat face each other. | 12-27-2012 |
20120326603 | ORGANIC LIGHT EMITTING DIODE DISPLAY - An OLED display includes a pixel substrate including a pixel area at which an organic light emitting member is located, and a peripheral area surrounding the pixel area, a pixel protective layer located in the pixel area, a peripheral protective layer separated from the pixel protective layer and located in the peripheral area, a sealing substrate opposite to the pixel substrate, a moisture absorbent between the pixel substrate and the sealing substrate, and on and overlapping the peripheral protective layer, and a sealing member between the pixel substrate and the sealing substrate, and located at an outer side of the moisture absorbent. | 12-27-2012 |
20130026503 | LIGHT EMITTING DIODE DISPLAY AND MANUFACTURING METHOD THEREOF - An organic light emitting diode (OLED) display includes a substrate, an OLED on the substrate, and an encapsulation layer on the substrate with the OLED therebetween. The encapsulation layer includes a plurality of metal layers. Two of the plurality of metal layers are directly attached to each other. | 01-31-2013 |
20140062290 | ORGANIC LIGHT EMITTING DISPLAY APPARATUS AND METHOD OF MANUFACTURING THE SAME - An organic light emitting display apparatus includes a substrate, a display portion on the substrate, the display portion including a plurality of emission regions, each including an organic light emitting diode (OLED), and a plurality of non-emission regions protruding from between the plurality of emission regions, an encapsulation substrate facing the substrate, a sealing material bonding the substrate and the encapsulation substrate and sealing the display portion, and a filling material on a surface of the encapsulation substrate facing the display portion, the filling material being spaced apart from the OLED and being formed of a cured polyimide (PI). | 03-06-2014 |
20140287543 | ORGANIC LIGHT EMITTING DIODE DISPLAY - Disclosed is an organic light emitting diode (OLED) display comprising a substrate; an organic light emitting element disposed on the substrate; an encapsulation substrate disposed on the organic light emitting element; and an adhesive layer formed on the substrate, covering the organic light emitting element, and bonding the substrate on which the organic light emitting element is formed with the encapsulation substrate. | 09-25-2014 |
20150064820 | ORGANIC LIGHT EMITTING DIODE DISPLAY, MANUFACTURING METHOD AND MANUFACTURING EQUIPMENT THEREOF - A method for manufacturing an OLED display according to an exemplary embodiment comprises: forming a thermosetting adhesive layer having a getter receiving portion on a metal sheet; forming a display unit including a plurality of pixels on a substrate; forming a getter layer at an external side of the display unit on the substrate; adhering the thermosetting adhesive layer and the metal sheet to the substrate so as to locate the getter layer in the getter receiving unit; and hardening the thermosetting adhesive layer. The forming of the thermosetting adhesive layer includes layering a solid thermosetting adhesive sheet which has been patterned so as to have the getter receiving portion on the metal sheet. | 03-05-2015 |
Patent application number | Description | Published |
20110233778 | FORMATION OF LINER AND BARRIER FOR TUNGSTEN AS GATE ELECTRODE AND AS CONTACT PLUG TO REDUCE RESISTANCE AND ENHANCE DEVICE PERFORMANCE - The invention provides a method of forming a film stack on a substrate, comprising depositing a tungsten nitride layer on the substrate, subjecting the substrate to a nitridation treatment using active nitrogen species from a remote plasma, and depositing a conductive bulk layer directly on the tungsten nitride layer without depositing a tungsten nucleation layer on the tungsten nitride layer as a growth site for tungsten. | 09-29-2011 |
20110263115 | NMOS METAL GATE MATERIALS, MANUFACTURING METHODS, AND EQUIPMENT USING CVD AND ALD PROCESSES WITH METAL BASED PRECURSORS - Embodiments of the invention generally provide methods for depositing metal-containing materials and compositions thereof. The methods include deposition processes that form metal, metal carbide, metal silicide, metal nitride, and metal carbide derivatives by a vapor deposition process, including thermal decomposition, CVD, pulsed-CVD, or ALD. In one embodiment, a method for processing a substrate is provided which includes depositing a dielectric material having a dielectric constant greater than 10, forming a feature definition in the dielectric material, depositing a work function material conformally on the sidewalls and bottom of the feature definition, and depositing a metal gate fill material on the work function material to fill the feature definition, wherein the work function material is deposited by reacting at least one metal-halide precursor having the formula MX | 10-27-2011 |
20130146468 | CHEMICAL VAPOR DEPOSITION (CVD) OF RUTHENIUM FILMS AND APPLICATIONS FOR SAME - Methods for depositing ruthenium-containing films are disclosed herein. In some embodiments, a method of depositing a ruthenium-containing film on a substrate may include depositing a ruthenium-containing film on a substrate using a ruthenium-containing precursor, the deposited ruthenium-containing film having carbon incorporated therein; and exposing the deposited ruthenium-containing layer to a hydrogen-containing gas to remove at least some of the carbon from the deposited ruthenium-containing film. In some embodiments, the hydrogen-containing gas exposed ruthenium-containing film may be subsequently exposed to an oxygen-containing gas to at least one of remove at least some carbon from or add oxygen to the ruthenium-containing film. In some embodiments, the deposition and exposure to the hydrogen-containing gas and optionally, the oxygen-containing gas may be repeated to deposit the ruthenium-containing film to a desired thickness. | 06-13-2013 |
20140120712 | NMOS METAL GATE MATERIALS, MANUFACTURING METHODS, AND EQUIPMENT USING CVD AND ALD PROCESSES WITH METAL BASED PRECURSORS - Embodiments provide methods for depositing metal-containing materials. The methods include deposition processes that form metal, metal carbide, metal silicide, metal nitride, and metal carbide derivatives by a vapor deposition process, including thermal decomposition, CVD, pulsed-CVD, or ALD. A method for processing a substrate is provided which includes depositing a dielectric material forming a feature definition in the dielectric material, depositing a work function material conformally on the sidewalls and bottom of the feature definition, and depositing a metal gate fill material on the work function material to fill the feature definition, wherein the work function material is deposited by reacting at least one metal-halide precursor having the formula MX | 05-01-2014 |
Patent application number | Description | Published |
20110298062 | METAL GATE STRUCTURES AND METHODS FOR FORMING THEREOF - Metal gate structures and methods for forming thereof are provided herein. In some embodiments, a method for forming a metal gate structure on a substrate having a feature formed in a high k dielectric layer may include depositing a first layer within the feature atop the dielectric layer; depositing a second layer comprising cobalt or nickel within the feature atop the first layer; and depositing a third layer comprising a metal within the feature atop the second layer to fill the feature, wherein at least one of the first or second layers forms a wetting layer to form a nucleation layer for a subsequently deposited layer, wherein one of the first, second, or third layers forms a work function layer, and wherein the third layer forms a gate electrode. | 12-08-2011 |
20110312148 | CHEMICAL VAPOR DEPOSITION OF RUTHENIUM FILMS CONTAINING OXYGEN OR CARBON - Methods for depositing ruthenium-containing films are provided herein. In some embodiments, a method of depositing a ruthenium-containing film on a substrate may include depositing a ruthenium-containing film on a substrate using a ruthenium-containing precursor, the deposited ruthenium-containing film having carbon incorporated therein; and exposing the deposited ruthenium-containing film to an oxygen-containing gas to remove at least some of the carbon from the deposited ruthenium-containing film. In some embodiments, the oxygen-containing gas exposed ruthenium-containing film may be annealed in a hydrogen-containing gas to remove at least some oxygen from the ruthenium-containing film. In some embodiments, the deposition, exposure, and annealing may be repeated to deposit the ruthenium-containing film to a desired thickness. | 12-22-2011 |
20120012465 | METHODS FOR FORMING BARRIER/SEED LAYERS FOR COPPER INTERCONNECT STRUCTURES - Methods for forming barrier/seed layers for interconnect structures are provided herein. In some embodiments, a method of processing a substrate having an opening formed in a first surface of the substrate, the opening having a sidewall and a bottom surface, the method may include forming a layer comprising manganese (Mn) and at least one of ruthenium (Ru) or cobalt (Co) on the sidewall and bottom surface of the opening; and depositing a conductive material on the layer to fill the opening. In some embodiments, one of ruthenium (Ru) or cobalt (Co) is deposited on the sidewall and bottom surface of the opening. The materials may be deposited by chemical vapor deposition (CVD) or by physical vapor deposition (PVD). | 01-19-2012 |
20120141667 | METHODS FOR FORMING BARRIER/SEED LAYERS FOR COPPER INTERCONNECT STRUCTURES - Methods for forming barrier/seed layers for interconnect structures are provided herein. In some embodiments, a method of processing a substrate having an opening formed in a first surface of the substrate, the opening having a sidewall and a bottom surface, the method may include forming a layer comprising manganese (Mn) and at least one of ruthenium (Ru) or cobalt (Co) on the sidewall and the bottom surface of the opening, the layer having a first surface adjacent to the sidewall and bottom surface of the opening and a second surface opposite the first surface, wherein the second surface comprises predominantly at least one of ruthenium (Ru) or cobalt (Co) and wherein a predominant quantity of manganese (Mn) in the layer is not disposed proximate the second surface; and depositing a conductive material on the layer to fill the opening. | 06-07-2012 |
Patent application number | Description | Published |
20120330924 | METHOD AND SYSTEM FOR QUERYING AN ON DEMAND DATABASE SERVICE - Methods and systems are provided for querying a multi-tenant database. One exemplary method of generating an improved query plan to a database from an input query submitted to an on demand database service over a network involves determining guidance information appropriate to the input query based at least in part on an identity of a source of the input query, determining a database hint for processing the input query based at least in part on the guidance information, and providing the database hint to the database to form the improved query plan, thereby enabling the database to return an improved result responsive to the input query based at least in part upon the database hint. | 12-27-2012 |
20120330926 | STATISTICS MANAGEMENT FOR DATABASE QUERYING - Methods and systems are provided for querying a database. One exemplary method for obtaining data from an on-demand database supporting one or more tenants involves obtaining model database statistics based on expected utilization information for a tenant and providing the model database statistics to the on-demand database. The on-demand database utilizes the model database statistics to generate a query plan and executes the query plan to obtain data from the model database statistics. | 12-27-2012 |
20130018890 | CREATING A CUSTOM INDEX IN A MULTI-TENANT DATABASE ENVIRONMENT - Methods and systems are described for creating a custom index in a multi-tenant database environment. In one embodiment, a method includes obtaining query for a multi-tenant database that is recommended as a candidate for creating an additional filter, evaluating the query against criteria to determine whether to select the query for creating the additional filter, and creating the additional filter for the query, if the query is selected. | 01-17-2013 |
20140012817 | Statistics Mechanisms in Multitenant Database Environments - Statistics mechanisms in multitenant database environments. A master statistics file is maintained in a multitenant database system. The master statistics file has statistics corresponding to multiple tenants within the multitenant database system. Statistics for a selected table within the multitenant database system are generated. The selected table corresponding to a selected tenant of the multitenant database system. The master statistics file is updated based on the generated statistics for the selected table. | 01-09-2014 |
20140040235 | STATISTICS MANAGEMENT FOR DATABASE QUERYING - Methods and systems are provided for querying a database. One exemplary method for obtaining data from an on-demand database supporting one or more tenants involves obtaining model database statistics based on expected utilization information for a tenant and providing the model database statistics to the on-demand database. The on-demand database utilizes the model database statistics to generate a query plan and executes the query plan to obtain data from the model database statistics. | 02-06-2014 |
20140081950 | INNER QUERY JOINS - In an on demand database system, a query engine applies a custom index for inner queries. The query engine receives a query and determines that the query has an inner query nested within the primary query. The query engine identifies that a custom index exists for a client associated with the query, and applies the custom index to filter results for the query. The custom index includes a subset of information of a table that includes accounts for multiple different clients. By using the custom index, the query engine can filter the results more efficiently that if solely using the multiple client table. | 03-20-2014 |
Patent application number | Description | Published |
20130187273 | SEMICONDUCTOR DEVICES WITH COPPER INTERCONNECTS AND METHODS FOR FABRICATING SAME - Semiconductor devices having copper interconnects and methods for their fabrication are provided. In one embodiment, a semiconductor device is fabricated with a copper interconnect on substrate such as an FEOL processed substrate. The method includes forming a copper layer on a substrate. The copper layer is formed from grains. The copper layer is modified such that the modified copper layer has an average grain size of larger than about 0.05 microns. In the method, the modified copper layer is etched to form a line along the substrate and a via extending upwards from the line. | 07-25-2013 |
20130244422 | METHODS OF FORMING COPPER-BASED CONDUCTIVE STRUCTURES ON SEMICONDUCTOR DEVICES - Disclosed herein are various methods of forming copper-based conductive structures on semiconductor devices, such as transistors. In one example, the method involves performing a first etching process through a patterned metal hard mask layer to define an opening in a layer of insulating material, performing a second etching process through the opening in the layer of insulating material that exposes a portion of an underlying copper-containing structure, performing a wet etching process to remove the patterned metal hard mask layer, performing a selective metal deposition process through the opening in the layer of insulating material to selectively form a metal region on the copper-containing structure and, after forming the metal region, forming a copper-containing structure in the opening above the metal region. | 09-19-2013 |
20130270646 | INTEGRATED CIRCUITS HAVING IMPROVED METAL GATE STRUCTURES AND METHODS FOR FABRICATING SAME - Integrated circuits and methods for fabricating integrated circuits are provided. In an embodiment, a method for fabricating an integrated circuit includes forming a PFET trench in a PFET region and an NFET trench in an NFET region of an interlayer dielectric material on a semiconductor surface. The NFET trench is partially filled with an N-type work function metal layer to define an inner cavity. The PFET trench and the inner cavity in the NFET trench are partially filled with a P-type work function metal layer to define a central void in each trench. In the method, the central voids are filled with a metal fill to form metal gate structures. A single recessing process is then performed to recess portions of each metal gate structure within each trench to form a recess in each trench above the respective metal gate structure. | 10-17-2013 |
20130292744 | INTEGRATED CIRCUIT AND METHOD FOR FABRICATING THE SAME HAVING A REPLACEMENT GATE STRUCTURE - An integrated circuit includes a first replacement gate structure. The first replacement gate structure includes a layer of a first barrier material that is less than 20 Å in thickness and a layer of a p-type workfunction material. The replacement gate structure is less than about 50 nm in width. | 11-07-2013 |
20130299922 | INTEGRATED CIRCUIT AND METHOD FOR FABRICATING THE SAME HAVING A REPLACEMENT GATE STRUCTURE - Integrated circuits and methods of fabricating integrated circuits are provided herein. In an embodiment, a method of fabricating an integrated circuit includes depositing a layer of a high-k dielectric material; depositing a layer of a work function shifter material over a portion of the high-k dielectric material to form an overlapping region; heat treating the layer of the high-k dielectric material and the layer of the work function shifter material to as to form a transformed dielectric material via thermal diffusion that is a combination of the high-k dielectric and work function shifter materials in the overlapping region; and depositing a layer of a first replacement gate fill material to obtain multiple threshold voltages. | 11-14-2013 |
20140027910 | METHOD FOR REDUCING WETTABILITY OF INTERCONNECT MATERIAL AT CORNER INTERFACE AND DEVICE INCORPORATING SAME - A method for forming an interconnect structure includes forming a recess in a dielectric layer of a substrate, forming a first transition metal layer in the recess on corner portions of the recess, and forming a second transition metal layer in the recess over the first transition metal layer to line the recess. The method further includes filling the recess with a fill layer and annealing the substrate so that the first transition metal layer and the second transition metal layer form an alloy portion proximate the corner portions during the annealing, the alloy portion having a reduced wettability for a material of the fill layer than the second transition metal. Additionally, the method includes polishing the substrate to remove portions of the fill layer extending above the recess. | 01-30-2014 |
20140070283 | FIELD EFFECT TRANSISTOR AND METHOD OF FABRICATION - An improved field effect transistor and method of fabrication are disclosed. A barrier layer stack is formed in the base and sidewalls of a gate cavity. The barrier layer stack has a first metal layer and a second metal layer. A gate electrode metal is deposited in the cavity. The barrier layer stack is thinned or removed on the sidewalls of the gate cavity, to more precisely control the voltage threshold of the field effect transistor. | 03-13-2014 |
20140167264 | INTEGRATED CIRCUITS AND METHODS FOR FABRICATING INTEGRATED CIRCUITS WITH SILICIDE CONTACTS ON NON-PLANAR STRUCTURES - Integrated circuits and methods for fabricating integrated circuits are provided. In an embodiment, a method for fabricating an integrated circuit includes providing a semiconductor substrate and forming fins over the semiconductor substrate. Each fin is formed with sidewalls. The method further includes conformally depositing a metal film stack on the sidewalls of each fin. In the method, the metal film stack is annealed to form a metal silicide film over the sidewalls of each fin. | 06-19-2014 |
20140246734 | REPLACEMENT METAL GATE WITH MULITIPLE TITANIUM NITRIDE LATERS - A semiconductor comprising a multilayer structure which prevents oxidization of the titanium nitride layer that protects a high-K dielectric layer is provided. Replacement metal gates are over the multilayer structure. A sacrificial polysilicon gate structure is deposited first. The sacrificial polysilicon gate structure is then removed, and the various layers of the replacement metal gate structure are deposited in the space previously occupied by the sacrificial polysilicon gate structure. | 09-04-2014 |
20140291847 | METHODS OF FORMING A BARRIER SYSTEM CONTAINING AN ALLOY OF METALS INTRODUCED INTO THE BARRIER SYSTEM, AND AN INTEGRATED CIRCUIT PRODUCT CONTAINING SUCH A BARRIER SYSTEM - One illustrative method disclosed herein includes forming a trench/via in a layer of insulating material, forming a barrier system comprised of at least one barrier material and at least two metallic elements, and performing a heating process to form a metal alloy comprised of the at least two metallic elements in the barrier system. Also disclosed is a device that comprises a trench/via in a layer of insulating material, a barrier system positioned in the trench/via, wherein the barrier system comprises at least one barrier material and a metal alloy comprised of at least two metallic elements that are comprised of materials other than the at least one barrier material, and a conductive structure positioned in the trench/via above the barrier system. | 10-02-2014 |
20150061027 | METHODS OF FORMING GATE STRUCTURES FOR TRANSISTOR DEVICES FOR CMOS APPLICATIONS AND THE RESULTING PRODUCTS - One method for forming replacement gate structures for NMOS and PMOS transistors includes performing an etching process to remove a sacrificial gate structure for the NMOS and PMOS transistors to thereby define NMOS and PMOS gate cavities, depositing a gate insulation layer in the gate cavities, depositing a first metal layer on the gate insulation layer in the gate cavities, performing at least one process operation to form (1) an NMOS metal silicide material above the first metal layer within the NMOS gate cavity, the NMOS metal silicide material having a first amount of atomic silicon, and (2) a PMOS metal silicide material above the first metal layer within the PMOS gate cavity, the PMOS metal silicide material having a second amount of atomic silicon, and wherein the first and second amounts of atomic silicon are different, and forming gate cap layers within the NMOS and PMOS gate cavities. | 03-05-2015 |
20150126023 | METHODS OF FORMING GATE STRUCTURES WITH MULTIPLE WORK FUNCTIONS AND THE RESULTING PRODUCTS - One illustrative method disclosed herein includes removing sacrificial gate structures for NMOS and PMOS transistors to thereby define NMOS and PMOS gate cavities, forming a high-k gate insulation layer in the NMOS and PMOS gate cavities, forming a lanthanide-based material layer on the high-k gate insulation layer in the NMOS and PMOS gate cavities, performing a heating process to drive material from the lanthanide-based material layer into the high-k gate insulation layer so as to thereby form a lanthanide-containing high-k gate insulation layer in each of the NMOS and PMOS gate cavities, and forming gate electrode structures above the lanthanide-containing high-k gate insulation layer in the NMOS and PMOS gate cavities. | 05-07-2015 |
20150137373 | INTEGRATED CIRCUITS AND METHODS FOR FABRICATING INTEGRATED CIRCUITS WITH IMPROVED CONTACT STRUCTURES - Integrated circuits with improved contact structures and methods for fabricating integrated circuits with improved contact structures are provided. In an exemplary embodiment, a method for fabricating integrated circuits includes providing a device in and/or on a semiconductor substrate. Further, the method includes forming a contact structure in electrical contact with the device. The contact structure includes silicate barrier portions overlying the device, a barrier metal overlying the device and positioned between the silicate barrier portions, and a fill metal overlying the barrier metal and positioned between the silicate barrier portions. | 05-21-2015 |
20150311206 | METHODS OF FORMING GATE STRUCTURES FOR TRANSISTOR DEVICES FOR CMOS APPLICATIONS AND THE RESULTING PRODUCTS - An integrated circuit product includes an NMOS transistor having a gate structure that includes an NMOS gate insulation layer, a first NMOS metal layer positioned on the NMOS gate insulation layer, an NMOS metal silicide material positioned above the first NMOS metal layer, and a layer of a second metal material positioned above and in contact with the NMOS gate insulation layer, the first NMOS metal layer, and the NMOS metal silicide layer. The PMOS transistor has a gate structure that includes a PMOS gate insulation layer, a first PMOS metal layer positioned on the PMOS gate insulation layer, a PMOS metal silicide material positioned above the first PMOS metal layer, and a layer of the second metal material positioned above and in contact with the PMOS gate insulation layer, the first PMOS metal layer, and the PMOS metal silicide layer. | 10-29-2015 |
Patent application number | Description | Published |
20140124876 | METAL GATE STRUCTURE FOR MIDGAP SEMICONDUCTOR DEVICE AND METHOD OF MAKING SAME - A PFET-based semiconductor gate structure providing a midgap work function for threshold voltage control between that of a NFET and a PFET is created by including an annealed layer of relatively thick TiN to dominate and shift the overall work function down from that of PFET. The structure has a PFET base covered with a high-k dielectric, a layer of annealed TiN, a layer of unannealed TiN, a thin barrier over the unannealed TiN, and n-type metal over the thin barrier. | 05-08-2014 |
20140210088 | METHOD FOR REDUCING WETTABILITY OF INTERCONNECT MATERIAL AT CORNER INTERFACE AND DEVICE INCORPORATING SAME - A semiconductor device includes a recess defined in a dielectric layer, the recess having an upper sidewall portion extending to an upper corner of the recess and a lower sidewall portion below the upper sidewall portion. An interconnect structure is positioned in the recess. The interconnect structure includes a continuous liner layer having upper and lower layer portions positioned laterally adjacent to the upper and lower sidewall portions, respectively. The upper layer portion includes an alloy of a first transition metal and a second transition metal and the lower layer portion includes the second transition metal but not the first transition metal. The interconnect structure also includes a fill material substantially filling the recess, wherein the second transition metal has a higher wettability for the fill material than the alloy. | 07-31-2014 |
20140231922 | SEMICONDUCTOR GATE STRUCTURE FOR THRESHOLD VOLTAGE MODULATION AND METHOD OF MAKING SAME - A gate structure of a semiconductor device having a NFET and a PFET, includes a lower layer of a hafnium-based dielectric over the gates of the NFET and PFET, and an upper layer of a lanthanide dielectric. The dielectrics are annealed to mix them above the NFET resulting in a lowered work function, and corresponding threshold voltage reduction. An annealed, relatively thick titanium nitride cap over the mixed dielectric above the NFET gate also lowers the work function and threshold voltage. Above the TiN cap and the hafnium-based dielectric over the PFET gate, is another layer of titanium nitride that has not been annealed. A conducting layer of tungsten covers the structure. | 08-21-2014 |
20150021704 | FINFET WORK FUNCTION METAL FORMATION - An improved method and structure for fabrication of replacement metal gate (RMG) field effect transistors is disclosed. P-type field effect transistor (PFET) gate cavities are protected while N work function metals are deposited in N-type field effect transistor (NFET) gate cavities. | 01-22-2015 |
20150108577 | SELECTIVE GROWTH OF A WORK-FUNCTION METAL IN A REPLACEMENT METAL GATE OF A SEMICONDUCTOR DEVICE - Approaches for forming a replacement metal gate (RMG) of a semiconductor device, are disclosed. Specifically provided is a p-channel field effect transistor (p-FET) and an n-channel field effect transistor (n-FET) formed over a substrate, the p-FET and the n-FET each having a recess formed therein, a high-k layer and a barrier layer formed within each recess, a work-function metal (WFM) selectively grown within the recess of the n-FET, wherein the high-k layer, barrier layer, and WFM are each recessed to a desired height within the recesses, and a metal material (e.g., Tungsten) formed within each recess. By providing a WFM chamfer earlier in the process, the risk of mask materials filling into each gate recess is reduced. Furthermore, the selective WFM growth improves fill-in of the metal material, which lowers gate resistance in the device. | 04-23-2015 |
20150137273 | METHOD AND DEVICE FOR SELF-ALIGNED CONTACT ON A NON-RECESSED METAL GATE - A methodology for forming a self-aligned contact (SAC) that exhibits reduced likelihood of a contact-to-gate short circuit failure and the resulting device are disclosed. Embodiments may include forming a replacement metal gate, with spacers at opposite sides thereof, on a substrate, forming a recess in an upper surface of the spacers along outer edges of the replacement metal gate, and forming an aluminum nitride (AlN) cap over the metal gate and in the recess. | 05-21-2015 |
20150179640 | COMMON FABRICATION OF DIFFERENT SEMICONDUCTOR DEVICES WITH DIFFERENT THRESHOLD VOLTAGES - A multi-device semiconductor structure including a p-type logic device, a p-type memory device, a n-type logic device and a n-type memory device are provided on a bulk silicon substrate. Each of these devices includes a dielectric layer and either a n-type or a p-type work function layer disposed over the dielectric layer. Some of the various device types of the multi-device semiconductor structure are protected, and impurities, such as aluminum and/or nitrogen, are added to the exposed work function layers to achieve one or more other desired work functions with different threshold voltages. | 06-25-2015 |
20150194350 | THRESHOLD VOLTAGE TUNING USING SELF-ALIGNED CONTACT CAP - Methods of forming a PFET dielectric cap with varying concentrations of H | 07-09-2015 |
20150255331 | INTEGRATED CIRCUITS WITH A COPPER AND MANGANESE COMPONENT AND METHODS FOR PRODUCING SUCH INTEGRATED CIRCUITS - Integrated circuits with copper and magnesium components and methods for producing such integrated circuits are provided. A method of producing the integrated circuits includes forming an aperture in an interlayer dielectric. A seed layer is formed in the aperture, where the seed layer includes manganese and copper, and where the seed layer has a copper concentration gradient. A core is formed overlying the seed layer, where the core includes copper. | 09-10-2015 |
20150255339 | METHODS OF FORMING A METAL CAP LAYER ON COPPER-BASED CONDUCTIVE STRUCTURES ON AN INTEGRATED CIRCUIT DEVICE - One method includes forming a barrier layer in a trench/opening in an insulating material, forming a first region of a copper material above the barrier layer, forming a metal layer in the trench/opening on the first region of copper material, forming a second region of copper material on the metal layer, performing at least one CMP process to remove any materials positioned above a planarized upper surface of the layer of insulating material outside of the trench/opening so as to thereby define a structure comprised of the metal layer positioned between the first and second regions of copper material, forming a dielectric cap layer above the layer of insulating material and above the structure, and performing a metal diffusion anneal process to form a metal cap layer adjacent at least the upper surface of a conductive copper structure. | 09-10-2015 |
20150311308 | ALTERNATIVE GATE DIELECTRIC FILMS FOR SILICON GERMANIUM AND GERMANIUM CHANNEL MATERIALS - Embodiments of the present invention provide a high-K dielectric film for use with silicon germanium (SiGe) or germanium channel materials, and methods of fabrication. As a first step of this process, an interfacial layer (IL) is formed on the semiconductor substrate providing reduced interface trap density. However, an ultra-thin layer is used as a barrier film to avoid germanium diffusion in high-k film and oxygen diffusion from the high-k film to the interfacial layer (IL), therefore, dielectric films such as aluminum oxide (Al | 10-29-2015 |
20150318398 | METHODS OF FORMING EPI SEMICONDUCTOR MATERIAL IN A TRENCH FORMED ABOVE A SEMICONDUCTOR DEVICE AND THE RESULTING DEVICES - One method disclosed includes, among other things, forming a gate structure above an active region of a semiconductor substrate, wherein a first portion of the gate structure is positioned above the active region and second portions of the gate structure are positioned above an isolation region formed in the substrate, forming a sidewall spacer adjacent opposite sides of the first portion of the gate structure so as to define first and second continuous epi formation trenches comprised of the spacer that extend for less than the axial length of the gate structure, and forming an epi semiconductor material on the active region within each of the first and second continuous epi formation trenches. | 11-05-2015 |
20150325473 | INTEGRATED CIRCUITS WITH METAL-TITANIUM OXIDE CONTACTS AND FABRICATION METHODS - Devices and methods for forming semiconductor devices with metal-titanium oxide contacts are provided. One intermediate semiconductor device includes, for instance: a substrate, at least one field-effect transistor disposed on the substrate, a first contact region positioned over at least a first portion of the at least one field-effect transistor between a spacer and an interlayer dielectric, and a second contact region positioned over at least a second portion of the at least one field-effect transistor between a spacer and an interlayer dielectric. One method includes, for instance: obtaining an intermediate semiconductor device and forming at least one contact on the intermediate semiconductor device. | 11-12-2015 |
20150340497 | METHODS OF INCREASING SILICIDE TO EPI CONTACT AREAS AND THE RESULTING DEVICES - One method disclosed includes, among other things, forming a gate structure above an active region of a semiconductor substrate, performing an epitaxial deposition process to form an epi semiconductor material on the active region in the source/drain region of the device, performing an etching process on the epi semiconductor material to remove a portion of the epi semiconductor material so as to define at least one epi recess in the epi semiconductor material, forming a metal silicide layer on the upper surface of the epi semiconductor material and in the at least one epi recess in the epi semiconductor material, and forming a conductive structure that is conductively coupled to the metal silicide layer. | 11-26-2015 |
20160035631 | Atomic Layer Deposition of HfAlC as a Metal Gate Workfunction Material in MOS Devices | 02-04-2016 |
20160042954 | REPLACEMENT METAL GATE AND FABRICATION PROCESS WITH REDUCED LITHOGRAPHY STEPS - Embodiments of the present invention provide a replacement metal gate and a fabrication process with reduced lithography steps. Using selective etching techniques, a layer of fill metal is used to protect the dielectric layer in the trenches, eliminating the need for some lithography steps. This, in turn, reduces the overall cost and complexity of fabrication. Furthermore, additional protection is provided during etching, which serves to improve product yield. | 02-11-2016 |
20160049399 | GATE STRUCTURES FOR SEMICONDUCTOR DEVICES WITH A CONDUCTIVE ETCH STOP LAYER - One illustrative gate structure of a transistor device disclosed herein includes a high-k gate insulation layer and a work function metal layer positioned on the high-k gate insulation layer. The device further includes a first bulk metal layer positioned on the work function metal layer. The device further includes a second bulk metal layer. The first and second bulk metal layers have upper surfaces that are at substantially the same height level, and the first and second bulk metal layers are made of substantially the same material. The device further includes a conductive etch stop layer between the first and second bulk metal layers. | 02-18-2016 |
20160056253 | INTEGRATED CIRCUITS WITH DIFFUSION BARRIER LAYERS AND PROCESSES FOR PREPARING INTEGRATED CIRCUITS INCLUDING DIFFUSION BARRIER LAYERS - Integrated circuits with a diffusion barrier layers, and processes for preparing integrated circuits including diffusion barrier layers are provided herein. An exemplary integrated circuit includes a semiconductor substrate comprising a semiconductor material, a compound gate dielectric overlying the semiconductor substrate, and a gate electrode overlying the compound gate dielectric. In this embodiment, the compound gate dielectric includes a first dielectric layer, a diffusion barrier layer overlying the first dielectric layer; and a second dielectric layer overlying the diffusion barrier layer; wherein the diffusion barrier layer is made of a material that is less susceptible to diffusion of the semiconductor material than the first dielectric layer, less susceptible to diffusion of oxygen than the second dielectric layer, or both. | 02-25-2016 |
20160079168 | INTEGRATED CIRCUITS WITH METAL-TITANIUM OXIDE CONTACTS AND FABRICATION METHODS - Devices and methods for forming semiconductor devices with metal-titanium oxide contacts are provided. One intermediate semiconductor device includes, for instance: a substrate, at least one field-effect transistor disposed on the substrate, a first contact region positioned over at least a first portion of the at least one field-effect transistor between a spacer and an interlayer dielectric, and a second contact region positioned over at least a second portion of the at least one field-effect transistor between a spacer and an interlayer dielectric. One method includes, for instance: obtaining an intermediate semiconductor device and forming at least one contact on the intermediate semiconductor device. | 03-17-2016 |
20160099333 | FIELD EFFECT TRANSISTOR AND METHOD OF FABRICATION - An improved field effect transistor and method of fabrication are disclosed. A barrier layer stack is formed in the base and sidewalls of a gate cavity. The barrier layer stack has a first metal layer and a second metal layer. A gate electrode metal is deposited in the cavity. The barrier layer stack is thinned or removed on the sidewalls of the gate cavity, to more precisely control the voltage threshold of the field effect transistor. | 04-07-2016 |