Patent application number | Description | Published |
20130261224 | POLYMERIZATION PROCESS AND RAMAN ANALYSIS FOR OLEFIN-BASED POLYMERS - The invention provides a process for monitoring and/or adjusting a dispersion polymerization of an olefin-based polymer, the process comprising monitoring the concentration of the carbon-carbon unsaturations in the dispersion using Raman Spectroscopy. The invention also provides a process for polymerizing an olefin-based polymer, the process comprising polymerizing one or more monomer types, in the presence of at least one catalyst and at least one solvent, to form the polymer as a dispersed phase in the solvent; and monitoring the concentration of the carbon-carbon unsaturations in the dispersion using Raman Spectroscopy. | 10-03-2013 |
20130281643 | OLEFIN-BASED POLYMERS AND DISPERSION POLYMERIZATIONS - The invention provides a polymerization process comprising polymerizing a reaction mixture comprising one or more monomer types, at least one catalyst, and at least one solvent, to form a polymer dispersion, and wherein the at least one catalyst is soluble in the at least one solvent, and wherein the polymer forms a dispersed phase in the solvent, and wherein the at least one solvent is a hydrocarbon. The invention provides a composition comprising an ethylene-based polymer comprising at least the following properties: a) a weight average molecular weight (Mw(abs)) greater than, or equal to, 60,000 g/mole; and b) a molecular weight distribution (Mw(abs)/Mn(abs)) greater than, or equal to, 2.3. | 10-24-2013 |
20140264258 | MULTI-HETEROJUNCTION NANOPARTICLES, METHODS OF MANUFACTURE THEREOF AND ARTICLES COMPRISING THE SAME - Disclosed herein is a semiconducting nanoparticle comprising a one-dimensional semiconducting nanoparticle having a first end and a second end; where the second end is opposed to the first end; and two first endcaps, one of which contacts the first end and the other of which contacts the second end respectively of the one-dimensional semiconducting nanoparticle; where the first endcap that contacts the first end comprises a first semiconductor and where the first endcap extends from the first end of the one-dimensional semiconducting nanoparticle to form a first nanocrystal heterojunction; where the first endcap that contacts the second end comprises a second semiconductor; where the first endcap extends from the second end of the one-dimensional semiconducting nanoparticle to form a second nanocrystal heterojunction; and where the first semiconductor and the second semiconductor are chemically different from each other. | 09-18-2014 |
20140264259 | MULTI-HETEROJUNCTION NANOPARTICLES, METHODS OF MANUFACTURE THEREOF AND ARTICLES COMPRISING THE SAME - Disclosed herein is a semiconducting nanoparticle comprising a one-dimensional semiconducting nanoparticle having a first end and a second end; where the second end is opposed to the first end; a first node that comprises a first semiconductor; where the first node contacts a radial surface of the one-dimensional semiconducting nanoparticle producing a first heterojunction at the point of contact; and a second node that comprises a second semiconductor; where the second node contacts the radial surface of the one-dimensional semiconducting nanoparticle producing a second heterojunction at the point of contact; where the first heterojunction is compositionally different from the second heterojunction. | 09-18-2014 |
20140364561 | ETHYLENE-BASED POLYMERS PREPARED BY DISPERSION POLYMERIZATION - The invention provides a composition comprising an ethylene-based polymer comprising at least the following properties: a) a weight average molecular weight (Mw(abs)) greater than, or equal to, 60,000 g/mole; and b) a molecular weight distribution (Mw(abs)/Mn(abs)) greater than, or equal to, 2.3. | 12-11-2014 |
20150243837 | MULTI-HETEROJUNCTION NANOPARTICLES, METHODS OF MANUFACTURE THEREOF AND ARTICLES COMPRISING THE SAME - Disclosed herein is a semiconducting nanoparticle comprising a one-dimensional semiconducting nanoparticle having a first end and a second end; a first endcap contacting one of the first end or the second end; where the first endcap comprises a first semiconductor and where the first endcap extends from the one-dimensional nanoparticle to form a first nanocrystal heterojunction; and a second endcap that contacts the first endcap; where the second endcap comprises a second semiconductor and where the second endcap extends from the first endcap to form a second nanocrystal heterojunction; and where the first semiconductor is different from the second semiconductor. | 08-27-2015 |
20150349194 | NANOSTRUCTURE MATERIAL METHODS AND DEVICES - In one aspect, structures are provided comprising: a substrate having a first surface and a second surface; and a polymeric layer disposed on the first surface of the substrate, the polymeric layer comprising a polymer and a plurality of light-emitting nanocrystals; the polymeric layer having a patterned surface, the patterned surface having a patterned first region having a first plurality of recesses and a patterned second region having a second plurality of recesses, wherein the plurality of recesses in each region has a first periodicity in a first direction, and a second periodicity in a second direction which intersects the first direction, wherein the first periodicity of the first region is different from the first periodicity of the second region. | 12-03-2015 |
20150349212 | NANOSTRUCTURE MATERIAL METHODS AND DEVICES - In one aspect, structures are provided comprising: a substrate having a first surface and a second surface; and a polymeric layer disposed on the first surface of the substrate, the polymeric layer comprising a polymer and a plurality of light-emitting nanocrystals; the polymeric layer having a patterned surface, the patterned surface having a patterned first region having a first plurality of recesses and a patterned second region having a second plurality of recesses, wherein the plurality of recesses in each region has a first periodicity in a first direction, and a second periodicity in a second direction which intersects the first direction, wherein the first periodicity of the first region is different from the first periodicity of the second region. | 12-03-2015 |
20150364645 | MULTI-HETEROJUNCTION NANOPARTICLES, METHODS OF MANUFACTURE THEREOF AND ARTICLES COMPRISING THE SAME - Disclosed herein is a semiconducting nanoparticle comprising a one-dimensional semiconducting nanoparticle having a first end and a second end; where the second end is opposed to the first end; and two first endcaps, one of which contacts the first end and the other of which contacts the second end respectively of the one-dimensional semiconducting nanoparticle; where the first endcap that contacts the first end comprises a first semiconductor and where the first endcap extends from the first end of the one-dimensional semiconducting nanoparticle to form a first nanocrystal heterojunction; where the first endcap that contacts the second end comprises a second semiconductor; where the first endcap extends from the second end of the one-dimensional semiconducting nanoparticle to form a second nanocrystal heterojunction; and where the first semiconductor and the second semiconductor are chemically different from each other. | 12-17-2015 |
Patent application number | Description | Published |
20100228943 | ACCESS MANAGEMENT TECHNIQUE FOR STORAGE-EFFICIENT MAPPING BETWEEN IDENTIFIER DOMAINS - Access management techniques have been developed to specify and facilitate mappings between I/O and host domains in ways that are storage-efficient and which can provide flexibility in the form, granularity and/or extent of mappings, attributes and access controls coded relative to a particular I/O domain. Indeed, different identifier and/or operation translation models may be employed on a per logical device (or even a per sub-window) basis. In general, the flexibility and efficiency afforded using some embodiments of the present invention can be desirable, particularly as numbers of I/O domains increase, such as in the case of virtualization system implementations in which a multiplicity of logical I/O devices may be represented using underlying physical resources. | 09-09-2010 |
20100228945 | ACCESS MANAGEMENT TECHNIQUE WITH OPERATION TRANSLATION CAPABILITY - Access management techniques have been developed to specify and facilitate mappings between I/O and host domains in ways that provide flexibility in the form, granularity and/or extent of mappings, attributes and access controls coded relative to a particular I/O domain. In some embodiments of the present invention, operation translations coded relative to a particular logical I/O device, domain or sub-window seek to optimize functionality, isolation or some other figure of merit without regard to needs or limitations of another. In this way, operation translations need not be uniform and need not reduce supported operation semantics to correspond to that of a lowest common denominator I/O device. In some embodiments, the form of mappings (e.g., of operation translations) may be specialized on a per-logical-device basis (or even a per-sub-window basis), thereby offering individual logical I/O devices (or sub-windows thereof) immediate, indexed, and/or untranslated operation mapping frameworks appropriate to their individual requirements or needs. In general, flexibilities and efficiencies afforded in some embodiments of the present invention can be desirable, particularly as the diversity of I/O device types and richness of transaction semantics supported in interconnect fabrics increase. Some embodiments may be leveraged in support of sophisticated system partitions or I/O virtualizations. | 09-09-2010 |
20100268990 | TRACING SUPPORT FOR INTERCONNECT FABRIC - Complex on-chip interconnect fabrics, particularly those that include point-to-point interconnects and coherent routing networks, can present significant challenges for conventional trace techniques that may be applied in an effort to efficiently provide an external debugger with visibility into on-chip interconnect transactions. Embodiments described herein generate and supply separate in-circuit-trace messages including address messages and data messages, which are sent out (i.e., off-chip) to external debug tools generally without delay and coincident with the distinct, but related, trace events within address and data paths of the interconnect fabric. These separate message instances embed appropriate tag and mark values to allow the message instances to be post-processed and correlated by the external debug tools so as to reconstruct the transaction information for operations performed in the on-chip interconnect. | 10-21-2010 |
20100318713 | Flow Control Mechanisms for Avoidance of Retries and/or Deadlocks in an Interconnect - Flow control mechanisms avoid or eliminate retries of transactions in a coherency interconnect. A class of transaction (CoT) framework is defined whereby individual transactions are associated with CoT labels consistent with chains of dependencies that exist between transactions initiated by any of the cooperating devices that participate in a given operation. In general, coherency protocols create dependencies that, when mapped to physical resources, can result in cycles in a graph of dependencies and deadlock. To support architectural mechanisms for deadlock avoidance, CoT labels are applied to individual transactions consistent with a precedence order of those transactions both (i) with respect to the operations of which such transactions are constituent parts and (ii) as amongst the set of such operations supported in the coherency interconnect. CoT labels applied to respective transactions constitute a CoT framework that may be used by coherency managers to efficiently support concurrent in-flight transactions without retry. | 12-16-2010 |
Patent application number | Description | Published |
20080222389 | INTERPROCESSOR MESSAGE TRANSMISSION VIA COHERENCY-BASED INTERCONNECT - A method includes communicating a first message between processors of a multiprocessor system via a coherency interconnect, whereby the first message includes coherency information. The method further includes communicating a second message between processors of the multiprocessor system via the coherency interconnect, whereby the second message includes interprocessor message information. A system includes a coherency interconnect and a processor. The processor includes an interface configured to receive messages from the coherency interconnect, each message including one of coherency information or interprocessor message information. The processor further includes a coherency management module configured to process coherency information obtained from at least one of the messages and an interrupt controller configured to generate an interrupt based on interprocessor message information obtained from at least one of the messages. | 09-11-2008 |
20090019232 | SPECIFICATION OF COHERENCE DOMAIN DURING ADDRESS TRANSLATION - A processing system includes a plurality of coherency domains and a plurality of coherency agents. Each coherency agent is associated with at least one of the plurality of coherency domains. At a select coherency agent of the plurality of coherency agents, an address translation for a coherency message is performed using a first memory address to generate a second memory address. A select coherency domain of the plurality of coherency domains associated with the coherency message is determined at the select coherency agent based on the address translation. The coherency message and a coherency domain identifier of the select coherency domain are provided by the select coherency agent to a coherency interconnect for distribution to at least one of the plurality of coherency agents based on the coherency domain identifier. | 01-15-2009 |
20090164737 | SYSTEM AND METHOD FOR PROCESSING POTENTIALLY SELF-INCONSISTENT MEMORY TRANSACTIONS - A processor provides memory request and a coherency state value for a coherency granule associated with a memory request. The processor further provides either a first indicator or a second indicator depending on whether the coherency state value represents a cumulative coherency state for a plurality of caches of the processor. The first indicator and the second indicator identify the coherency state value as representing a cumulative coherency state or a potentially non-cumulative coherency state, respectively. If the second indicator is provided, a transaction management module determines whether to request the cumulative coherency state for the coherency granule in response to receiving the second indicator. The transaction management module then provides an indicator of the request for the cumulative coherency state to the processor in response to determining to request the cumulative coherency state. Otherwise, the transaction management module processes the memory transaction without requesting the cumulative coherency state. | 06-25-2009 |
20150026410 | LEAST RECENTLY USED (LRU) CACHE REPLACEMENT IMPLEMENTATION USING A FIFO - A method and apparatus for calculating a victim way that is always the least recently used way. More specifically, in an m-set, n-way set associative cache, each way a cache set comprises a valid bit that indicates that the way contains valid data. The valid bit is set when a way is written and cleared upon being invalidated, e.g., via a snoop address, The cache system comprises a cache LRU circuit which comprises an LRU logic unit associated with each cache set. The LRU logic unit comprises a FIFO of n-depth (in certain embodiments, the depth corresponds to the number of ways in the cache) and m-width. The FIFO performs push, pop and collapse functions. Each entry in the FIFO contains the encoded way number that was last accessed. | 01-22-2015 |
20160085478 | Piggy-Back Snoops For Non-Coherent Memory Transactions Within Distributed Processing Systems - Piggy-back snoops are used for non-coherent memory transactions in distributed processing systems. Coherent and non-coherent memory transactions are received from a plurality of processing cores within a distributed processing system. Non-coherent snoop information for the non-coherent memory transactions is combined with coherent snoop information for the coherent memory transactions to form expanded snoop messages. The expanded snoop messages are then output to a snoop bus interconnect during snoop cycles for the distributed processing system. As such, when the processing cores monitor the snoop bus interconnect, the processing cores receive the non-coherent snoop information along with coherent snoop information within the same snoop cycle. While this piggy-backing of non-coherent snoop information with coherent snoop information uses an expanded snoop bus interconnect, usage of the coherent snoop bandwidth is significantly reduced thereby improving overall performance of the distributed processing system. | 03-24-2016 |
20160085706 | Methods And Systems For Controlling Ordered Write Transactions To Multiple Devices Using Switch Point Networks - Ordered write transactions from requester devices to multiple target devices are controlled using switch point networks. The requester device and the multiple target devices for the write transactions are coupled to a network of interconnected switch points. Write requests are generated for a plurality of parcels associated with a block of data to be written. The write requests have a particular order associated with an order in which the parcels are to be written, and these write requests are provided to the switch point interconnection network in the particular order. At least one of the switch points is then used to control the flow of write requests to the multiple target devices such that the particular order is maintained. In one embodiment, the target devices are memory devices, and the particular order is based upon the AXI (Advanced eXtensible Interface) protocol. | 03-24-2016 |