Patent application number | Description | Published |
20080200001 | METHOD OF PRODUCING A TRANSISTOR - Method of producing a transistor, comprising in particular the steps of: | 08-21-2008 |
20080220594 | Fabrication method of a mixed substrate and use of the substrate for producing circuits - The fabrication method of a mixed substrate comprising a tensile strained silicon-on-insulator portion and a compressive strained germanium-on-insulator portion comprises a first step of producing a strained silicon-on-insulator base substrate comprising first and second tensile strained silicon zones. After the base substrate has been produced, the method comprises the successive steps of masking the first tensile strained silicon zone forming the tensile strained silicon-on-insulator portion of the substrate, of performing germanium enrichment treatment of the second tensile strained silicon zone of the base substrate until a compressive strained germanium layer is obtained forming said compressive strained germanium-on-insulator portion of the substrate, and of removing the masking. | 09-11-2008 |
20080254591 | Method for Making a Thin-Film Element - A method for making a thin-film element includes epitaxially growing a first crystalline layer on a second crystalline layer of a support where the second crystalline layer is a material different from the first crystalline layer, the first crystalline layer having a thickness less than a critical thickness. A dielectric layer is formed on a side of the first crystalline layer opposite to the support to form a donor structure. The donor structure is assembled with a receiver layer and the support is removed. | 10-16-2008 |
20090017602 | METHOD FOR MANUFACTURING A SEMICONDUCTOR-ON-INSULATOR SUBSTRATE FOR MICROELECTRONICS AND OPTOELECTRONICS - The method includes the following steps:
| 01-15-2009 |
20090096028 | Transistor of the I-MOS Type Comprising Two Independent Gates and Method of Using Such a Transistor - The transistor comprises a source ( | 04-16-2009 |
20090120568 | METHOD OF TRANSFERRING A THIN FILM ONTO A SUPPORT - A method of transferring a thin film onto a first support, includes supplying a structure comprising a film of which at least one part originates from a solid substrate of a first material and which is solidly connected to a second support having a thermal expansion coefficient that is different from that of the first material and close to that of the first support, forming an embrittled area inside the film that defines the thin film to be transferred, affixing the film that is solidly connected to the second support to the first support, and breaking the film at the embrittled area. | 05-14-2009 |
20090161405 | DATA STORAGE MEDIUM AND ASSOCIATED METHOD - A data storage medium includes | 06-25-2009 |
20090170295 | MANUFACTURING METHOD FOR A SEMI-CONDUCTOR ON INSULATOR SUBSTRATE COMPRISING A LOCALISED Ge ENRICHED STEP - The invention relates to a manufacturing method of a semi-conductor on insulator substrate from an SOI substrate comprising a surface layer of silicon on an electrically insulating layer, called buried insulating layer, wherein a layer of Si | 07-02-2009 |
20090294822 | CIRCUIT WITH TRANSISTORS INTEGRATED IN THREE DIMENSIONS AND HAVING A DYNAMICALLY ADJUSTABLE THRESHOLD VOLTAGE VT - A microelectronic device comprising:
| 12-03-2009 |
20090317931 | METHOD OF FABRICATING AN ELECTROMECHANICAL DEVICE INCLUDING AT LEAST ONE ACTIVE ELEMENT - The invention relates to a method of fabricating an electromechanical device including an active element, wherein the method comprises the following steps: | 12-24-2009 |
20090321887 | METHOD OF FABRICATING AN ELECTROMECHANICAL STRUCTURE INCLUDING AT LEAST ONE MECHANICAL REINFORCING PILLAR - The invention relates to a method of fabricating an electromechanical structure presenting a first substrate ( | 12-31-2009 |
20090325335 | HETEROGENEOUS SUBSTRATE INCLUDING A SACRIFICIAL LAYER, AND A METHOD OF FABRICATING IT - The invention relates to a method of making a component from a heterogeneous substrate comprising first and second portions in at least one monocrystalline material, and a sacrificial layer constituted by at least one stack of at least one layer of monocrystalline Si situated between two layers of monocrystalline SiGe, the stack being disposed between said first and second portions of monocrystalline material, wherein the method consists in etching said stack by making:
| 12-31-2009 |
20100029031 | METHOD OF FABRICATING A MEMS/NEMS ELECTROMECHANICAL COMPONENT - The invention relates to a method of fabricating and electromechanical device on at least one substrate, the device including at least one active element and wherein the method comprises:
| 02-04-2010 |
20100075461 | METHOD FOR TRANSFERRING CHIPS ONTO A SUBSTRATE - The invention relates to a method for making a stack of at least two stages of circuits, each stage comprising a substrate and at least one component ( | 03-25-2010 |
20100244197 | EPITAXIAL METHODS AND STRUCTURES FOR REDUCING SURFACE DISLOCATION DENSITY IN SEMICONDUCTOR MATERIALS - The invention provides methods and structures for reducing surface dislocations of a semiconductor layer, and can be employed during the epitaxial growth of semiconductor structures and layers comprising III-nitride materials. Embodiments involve the formation of a plurality of dislocation pit plugs to prevent propagation of dislocations from an underlying layer of material into a following semiconductor layer of material. | 09-30-2010 |
20110001184 | METHOD OF ADJUSTING THE THRESHOLD VOLTAGE OF A TRANSISTOR BY A BURIED TRAPPING LAYER - An electronic subassembly and associated method for the production of an electronic subassembly include a semiconductor layer bearing at least a first transistor having an adjustable threshold voltage is joined to an insulator layer and a in which a first trapping zone is formed at a predetermined first depth. The first trapping zone extends at least beneath a channel of the first transistor and includes traps of greater density than the density of traps outside the first trapping zone, in such a way that the semiconductor layer and the first trapping zone are capacitively coupled. The useful information from the first transistor includes the charge transport within this transistor. A second trapping zone can be formed that extends at least beneath a channel of a second transistor that is formed by a second implantation with an energy and/or a dose and/or atoms that differ from those used to form the first trapping zone. | 01-06-2011 |
20110147849 | INTEGRATED CIRCUIT WITH ELECTROSTATICALLY COUPLED MOS TRANSISTORS AND METHOD FOR PRODUCING SUCH AN INTEGRATED CIRCUIT - An integrated circuit including:
| 06-23-2011 |
20110201177 | METHOD IN THE MICROELECTRONICS FIELDS OF FORMING A MONOCRYSTALLINE LAYER - A process for forming a thin film of a given material includes providing a first substrate having, on the surface, an amorphous and/or polycrystalline film of the given material and a second substrate is bonded to the first substrate by hydrophobic direct bonding (molecular adhesion), the second substrate having a single-crystal reference film of a given crystallographic orientation on the surface thereof. A heat treatment is applied at least to the amorphous and/or polycrystalline film, where the heat treatment causes at least a portion of the amorphous and/or polycrystalline film to undergo solid-phase recrystallization along the crystallographic orientation of the reference film, where the reference film acts as a recrystallization seed. The at least partly recrystallized film is then separated from at least a portion of the reference film. | 08-18-2011 |
20110207293 | METHOD OF PRODUCING A HYBRID SUBSTRATE HAVING A CONTINUOUS BURIED EECTRICALLY INSULATING LAYER - A method for producing a hybrid substrate includes preparing a first substrate including a mixed layer and an underlying electrically insulating continuous layer, the mixed layer made up of first single-crystal areas and second adjacent amorphous areas, the second areas making up at least part of the free surface of the first substrate. A second substrate is bonded to the first substrate, the second substrate including on the surface thereof, a reference layer with a predetermined crystallographic orientation. The first substrate is bonded to the second substrate by hydrophobic molecular bonding of at least the amorphous areas. A recrystallisation of at least part of the amorphous areas to solid phase is carried out according to the crystallographic orientation of the reference layer, and the two substrates are separated at the bonding interface. | 08-25-2011 |
20120187541 | EPITAXIAL METHODS FOR REDUCING SURFACE DISLOCATION DENSITY IN SEMICONDUCTOR MATERIALS - The invention provides methods and structures for reducing surface dislocations of a semiconductor layer, and can be employed during the epitaxial growth of semiconductor structures and layers comprising III-nitride materials. Embodiments involve the formation of a plurality of dislocation pit plugs to prevent propagation of dislocations from an underlying layer of material into a following semiconductor layer of material. | 07-26-2012 |
20120205614 | METHOD FOR MANUFACTURING A VERY-HIGH-RESOLUTION SCREEN USING A NANOWIRE-BASED EMITTING ANISOTROPIC CONDUCTIVE FILM - A method for producing an emissive pixel screen includes forming an active pixel matrix along which an electrode forming layer runs and having pixels arranged according to a distribution, forming an anisotropic substrate that includes a set of light emitting diodes constituted by parallel nanowires and arranged in an insulating matrix transversely with respect to a substrate thickness and having a density higher than a density of the pixels irrespective of the pixel distribution, connecting the substrate to the active pixel matrix by connecting only sub-groups of the parallel nanowires by a first end to separate pixel electrodes defined in the electrode forming layer according to the distribution of the pixels in the matrix, and connecting the sub-groups, by another end, to a common electrode, and delimiting the sub-groups by rendering the nanowires of the substrate that are arranged between the sub-groups emissively inactive. | 08-16-2012 |
20120206216 | ACOUSTIC WAVE DEVICE INCLUDING A SURFACE WAVE FILTER AND A BULK WAVE FILTER, AND METHOD FOR MAKING SAME - An acoustic wave device comprising at least one surface acoustic wave filter and one bulk acoustic wave filter, the device including, on a substrate comprising a second piezoelectric material: a stack of layers including a first metal layer and a layer of a first monocrystalline piezoelectric material, wherein the stack of layers is partially etched so as to define a first area in which the first and second piezoelectric materials are present and a second area in which the first piezoelectric material is absent; a second metallization at the first area for defining the bulk acoustic wave filter integrating the first piezoelectric material, and a third metallization at the second area for defining the surface acoustic wave filter integrating the second piezoelectric material. | 08-16-2012 |
20130273683 | Method of Fabricating An Electromechanical Structure Including at Least One Mechanical Reinforcing Pillar - The invention provides a method of fabricating an electromechanical structure presenting a first substrate including a layer of monocrystalline material covered in a sacrificial layer that presents a free surface, the structure presenting a mechanical reinforcing pillar in the sacrificial layer, the method including etching a well region in the sacrificial layer to define a mechanical pillar; depositing a first functionalization layer of the first material to at least partially fill the well region and cover the free surface of the sacrificial layer around the well region; depositing a second material different from the first material for terminating the filling of the well region to thereby cover the first functionalization layer around the well region, planarizing the filler layer, the pillar being formed by the superposition of the first material and second material in the well region; and releasing the electromechanical structure by removing at least partially the sacrificial layer. | 10-17-2013 |