Patent application number | Description | Published |
20090001415 | MULTI-GATE TRANSISTOR WITH STRAINED BODY - A semiconductor device comprises a semiconductor body having a top surface and laterally opposite sidewalls formed on a substrate, wherein the semiconductor body comprises a silicon alloy core having a top surface and laterally opposite sidewalls formed on a silicon fin structure, and a silicon shell layer formed on the top surface and the laterally opposite sidewalls of the silicon alloy core, wherein the silicon alloy core imparts a strain on the silicon shell layer. The semiconductor device further comprises a gate dielectric layer formed on the top surface and the laterally opposite sidewalls of the semiconductor body and a gate electrode formed on the gate dielectric layer. | 01-01-2009 |
20090242998 | PENETRATING IMPLANT FOR FORMING A SEMICONDUCTOR DEVICE - A semiconductor device and method to form a semiconductor device is described. The semiconductor includes a gate stack disposed on a substrate. Tip regions are disposed in the substrate on either side of the gate stack. Halo regions are disposed in the substrate adjacent the tip regions. A threshold voltage implant region is disposed in the substrate directly below the gate stack. The concentration of dopant impurity atoms of a particular conductivity type is approximately the same in both the threshold voltage implant region as in the halo regions. The method includes a dopant impurity implant technique having sufficient strength to penetrate a gate stack. | 10-01-2009 |
20100079924 | Method of patterning a metal on a vertical sidewall of an excavated feature, method of forming an embedded MIM capacitor using same, and embedded memory device produced thereby - A method of patterning a metal ( | 04-01-2010 |
20100151669 | FORMING ABRUPT SOURCE DRAIN METAL GATE TRANSISTORS - A gate structure may be utilized as a mask to form source and drain regions. Then the gate structure may be removed to form a gap and spacers may be formed in the gap to define a trench. In the process of forming a trench into the substrate, a portion of the source drain region is removed. Then the substrate is filled back up with an epitaxial material and a new gate structure is formed thereover. As a result, more abrupt source drain junctions may be achieved. | 06-17-2010 |
20100155887 | Common plate capacitor array connections, and processes of making same - A process of forming a semiconductive capacitor device for a memory circuit includes forming a first capacitor cell recess and a second capacitor cell recess that are spaced apart by a capacitor cell boundary of a first height. The process includes lowering the first height of the capacitor cell boundary to a second height. A common plate capacitor bridges between the first recess and the second recess over the boundary above the second height and below the first height. | 06-24-2010 |
20110134583 | METHOD OF PATTERNING A METAL ON A VERTICAL SIDEWALL OF AN EXCAVATED FEATURE, METHOD OF FORMING AN EMBEDDED MIM CAPACITOR USING SAME, AND EMBEDDED MEMORY DEVICE PRODUCED THEREBY - A method of patterning a metal ( | 06-09-2011 |
20110147888 | METHODS TO FORM MEMORY DEVICES HAVING A CAPACITOR WITH A RECESSED ELECTRODE - Methods to form memory devices having a MIM capacitor with a recessed electrode are described. In one embodiment, a method of forming a MIM capacitor with a recessed electrode includes forming an excavated feature defined by a lower portion that forms a bottom and an upper portion that forms sidewalls of the excavated feature. The method includes depositing a lower electrode layer in the feature, depositing an electrically insulating layer on the lower electrode layer, and depositing an upper electrode layer on the electrically insulating layer to form the MIM capacitor. The method includes removing an upper portion of the MIM capacitor to expose an upper surface of the electrode layers and then selectively etching one of the electrode layers to recess one of the electrode layers. This recess isolates the electrodes from each other and reduces the likelihood of a current leakage path between the electrodes. | 06-23-2011 |
20110215422 | PENETRATING IMPLANT FOR FORMING A SEMICONDUCTOR DEVICE - A semiconductor device and method to form a semiconductor device is described. The semiconductor includes a gate stack disposed on a substrate. Tip regions are disposed in the substrate on either side of the gate stack. Halo regions are disposed in the substrate adjacent the tip regions. A threshold voltage implant region is disposed in the substrate directly below the gate stack. The concentration of dopant impurity atoms of a particular conductivity type is approximately the same in both the threshold voltage implant region as in the halo regions. The method includes a dopant impurity implant technique having sufficient strength to penetrate a gate stack. | 09-08-2011 |
20110260244 | RECESSED CHANNEL ARRAY TRANSISTOR (RCAT) IN REPLACEMENT METAL GATE (RMG) LOGIC FLOW - Embodiments of the invention relate to a method of fabricating logic transistors using replacement metal gate (RMG) logic flow with modified process to form recessed channel array transistors (RCAT) on a common semiconductor substrate. An embodiment comprises forming an interlayer dielectric (ILD) layer on a semiconductor substrate, forming a first recess in the ILD layer of a first substrate region, forming a recessed channel in the ILD layer and in the substrate of a second substrate region, depositing a first conformal high-k dielectric layer in the first recess and a second conformal high-k dielectric layer in the recessed channel, and filling the first recess with a first gate metal and the recessed channel with a second gate metal. | 10-27-2011 |
20120161215 | RECTANGULAR CAPACITORS FOR DYNAMIC RANDOM ACCESS MEMORY (DRAM) AND DUAL-PASS LITHOGRAPHY METHODS TO FORM THE SAME - A rectangular capacitor for dynamic random access memory (DRAM) and a dual-pass lithography method to form the same are described. For example, a capacitor includes a trench disposed in a first dielectric layer disposed above a substrate. A cup-shaped metal plate is disposed along the bottom and sidewalls of the trench. A second dielectric layer is disposed on and conformal with the cup-shaped metal plate. A trench-fill metal plate is disposed on the second dielectric layer. The second dielectric layer isolates the trench-fill metal plate from the cup-shaped metal plate. The capacitor has a rectangular or near-rectangular shape from a top-down perspective. | 06-28-2012 |
20120161280 | CAPACITOR WITH RECESSED PLATE PORTION FOR DYNAMIC RANDOM ACCESS MEMORY (DRAM) AND METHOD TO FORM THE SAME - A capacitor includes a trench disposed in a first dielectric layer disposed above a substrate. A first metal plate is disposed along the bottom and sidewalls of the trench. A second dielectric layer is disposed on and conformal with the first metal plate. A portion of the first metal plate directly adjacent to the second dielectric layer is recessed relative to the sidewalls of the second dielectric layer. A second metal plate is disposed on and conformal with the second dielectric layer. A portion of the second metal plate directly adjacent to the second dielectric layer is recessed relative to the sidewalls of the second dielectric layer. A third dielectric layer is disposed above the first metal plate, the second dielectric layer, and the second metal plate, and disposed between the first metal plate and the second dielectric layer and between the second metal plate and the second dielectric layer. | 06-28-2012 |
20120223413 | SEMICONDUCTOR STRUCTURE HAVING A CAPACITOR AND METAL WIRING INTEGRATED IN A SAME DIELECTRIC LAYER - Semiconductor structures having capacitors and metal wiring integrated in a same dielectric layer are described. For example, a semiconductor structure includes a plurality of semiconductor devices disposed in or above a substrate. One or more dielectric layers are disposed above the plurality of semiconductor devices. Metal wiring is disposed in each of the dielectric layers. The metal wiring is electrically coupled to one or more of the semiconductor devices. A metal-insulator-metal (MIM) capacitor is disposed in one of the dielectric layers, adjacent to the metal wiring of the at least one of the dielectric layers. The MIM capacitor is electrically coupled to one or more of the semiconductor devices. | 09-06-2012 |
20120235274 | SEMICONDUCTOR STRUCTURE HAVING AN INTEGRATED DOUBLE-WALL CAPACITOR FOR EMBEDDED DYNAMIC RANDOM ACCESS MEMORY (EDRAM) AND METHOD TO FORM THE SAME - Semiconductor structures having integrated double-wall capacitors for eDRAM and methods to form the same are described. For example, an embedded double-wall capacitor includes a trench disposed in a first dielectric layer disposed above a substrate. The trench has a bottom and sidewalls. A U-shaped metal plate is disposed at the bottom of the trench, spaced apart from the sidewalls. A second dielectric layer is disposed on and conformal with the sidewalls of the trench and the U-shaped metal plate. A top metal plate layer is disposed on and conformal with the second dielectric layer. | 09-20-2012 |
20130224926 | PENETRATING IMPLANT FOR FORMING A SEMICONDUCTOR DEVICE - A semiconductor device and method to form a semiconductor device is described. The semiconductor includes a gate stack disposed on a substrate. Tip regions are disposed in the substrate on either side of the gate stack. Halo regions are disposed in the substrate adjacent the tip regions. A threshold voltage implant region is disposed in the substrate directly below the gate stack. The concentration of dopant impurity atoms of a particular conductivity type is approximately the same in both the threshold voltage implant region as in the halo regions. The method includes a dopant impurity implant technique having sufficient strength to penetrate a gate stack. | 08-29-2013 |
20130234290 | METHOD OF PATTERNING A METAL ON A VERTICAL SIDEWALL OF AN EXCAVATED FEATURE, METHOD OF FORMING AN EMBEDDED MIM CAPACITOR USING SAME, AND EMBEDDED MEMORY DEVICE PRODUCED THEREBY - A method of patterning a metal ( | 09-12-2013 |
20130270676 | METAL-INSULATOR-METAL (MIM) CAPACITOR WITH INSULATOR STACK HAVING A PLURALITY OF METAL OXIDE LAYERS - Metal-insulator-metal (MIM) capacitors with insulator stacks having a plurality of metal oxide layers are described. For example, a MIM capacitor for a semiconductor device includes a trench disposed in a dielectric layer disposed above a substrate. A first metal plate is disposed along the bottom and sidewalls of the trench. An insulator stack is disposed above and conformal with the first metal plate. The insulator stack includes a first metal oxide layer having a first dielectric constant and a second metal oxide layer having a second dielectric constant. The first dielectric constant is higher than the second dielectric constant. The MIM capacitor also includes a second metal plate disposed above and conformal with the insulator stack. | 10-17-2013 |
20130271938 | FORMATION OF DRAM CAPACITOR AMONG METAL INTERCONNECT - Techniques are disclosed for integrating capacitors among the metal interconnect for embedded DRAM applications. In some embodiments, the technique uses a wet etch to completely remove the interconnect metal (e.g., copper) that is exposed prior to the capacitor formation. This interconnect metal removal precludes that metal from contaminating the hi-k dielectric of the capacitor. Another benefit is increased height (surface area) of the capacitor, which allows for increased charge storage. In one example embodiment, an integrated circuit device is provided that includes a substrate having at least a portion of a DRAM bit cell circuitry, an interconnect layer on the substrate and including one or more metal-containing interconnect features, and a capacitor at least partly in the interconnect layer and occupying space from which a metal-containing interconnect feature was removed. The integrated circuit device can be, for example, a processor or a communications device. | 10-17-2013 |
20130292797 | FULLY ENCAPSULATED CONDUCTIVE LINES - Fully encapsulated conductive lines are generally described. For example, a first dielectric layer is formed on a substrate. Copper wiring is disposed below a top surface of the first dielectric layer. A barrier metal layer is formed over the copper wiring, the barrier metal layer flush with the top surface of the first dielectric layer, and a second dielectric layer is formed on the barrier metal layer and the top surface of the first dielectric layer. Other embodiments are also disclosed and claimed. | 11-07-2013 |
20140001598 | ATOMIC LAYER DEPOSITION (ALD) OF TAALC FOR CAPACITOR INTEGRATION | 01-02-2014 |
20140057408 | RECTANGULAR CAPACITORS FOR DYNAMIC RANDOM ACCESS MEMORY (DRAM) AND DUAL-PASS LITHOGRAPHY METHODS TO FORM THE SAME - A rectangular capacitor for dynamic random access memory (DRAM) and a dual-pass lithography method to form the same are described. For example, a capacitor includes a trench disposed in a first dielectric layer disposed above a substrate. A cup-shaped metal plate is disposed along the bottom and sidewalls of the trench. A second dielectric layer is disposed on and conformal with the cup-shaped metal plate. A trench-fill metal plate is disposed on the second dielectric layer. The second dielectric layer isolates the trench-fill metal plate from the cup-shaped metal plate. The capacitor has a rectangular or near-rectangular shape from a top-down perspective. | 02-27-2014 |
20150255533 | SEMICONDUCTOR STRUCTURE HAVING A CAPACITOR AND METAL WIRING INTEGRATED IN A SAME DIELECTRIC LAYER - Semiconductor structures having capacitors and metal wiring integrated in a same dielectric layer are described. For example, a semiconductor structure includes a plurality of semiconductor devices disposed in or above a substrate. One or more dielectric layers are disposed above the plurality of semiconductor devices. Metal wiring is disposed in each of the dielectric layers. The metal wiring is electrically coupled to one or more of the semiconductor devices. A metal-insulator-metal (MIM) capacitor is disposed in one of the dielectric layers, adjacent to the metal wiring of the at least one of the dielectric layers. The MIM capacitor is electrically coupled to one or more of the semiconductor devices. | 09-10-2015 |