Patent application number | Description | Published |
20090147015 | Aperture Compression for Multiple Data Streams - A hardware-based aperture compression system permits addressing large memory spaces via a limited bus aperture. Streams are assigned dynamic base addresses (BAR) that are maintained in registers on sources and destinations. Requests for addresses lying between BAR and BAR plus the size of the bus aperture are sent with BAR subtracted off by the source and added back by the destination. Requests for addresses outside that range are handled by transmitting a new, adjusted BAR before sending the address request. | 06-11-2009 |
20090160865 | Efficient Video Decoding Migration For Multiple Graphics Processor Systems - Embodiments of the invention as described herein provide a solution to the problems of conventional methods as stated above. In the following description, various examples are given for illustration, but none are intended to be limiting. Embodiments include a frame processor module in a graphics processing system that examines the intra-coded and inter-coded frames in an encoded video stream and initiates migration of decoding and rendering functions to a second graphics processor from a first graphics processor based on the location of intra-coded frames in a video stream and the composition of intermediate inter-coded frames. | 06-25-2009 |
20090160867 | Autonomous Context Scheduler For Graphics Processing Units - Embodiments directed to an autonomous graphics processing unit (GPU) scheduler for a graphics processing system are described. Embodiments include an execution structure for a host CPU and GPU in a computing system that allows the GPU to execute command threads in multiple contexts in a dynamic rather than fixed order based on decisions made by the GPU. This eliminates a significant amount of CPU processing overhead required to schedule GPU command execution order, and allows the GPU to execute commands in an order that is optimized for particular operating conditions. The context list includes parameters that specify task priority and resource requirements for each context. The GPU includes a scheduler component that determines the availability of system resources and directs execution of commands to the appropriate system resources, and in accordance with the priority defined by the context list. | 06-25-2009 |
20090167032 | PORTABLE COMPUTING DEVICE WITH INTEGRAL CURRENT GENERATOR AND METHOD OF USING THE SAME - A portable mobile device includes a first component and a second component movably connected to the first component. The first and second component are configured to be movable with respect to each other during the normal operation of the portable computing device. The portable computing device further includes a current generator connected to the first component and/or the second component. The current generator is operable to generate a current when the first component and the second component move with respect to each other in an engaged mode. A method for generating a current is also disclosed. | 07-02-2009 |
20090248941 | Peer-To-Peer Special Purpose Processor Architecture and Method - A peer-to-peer special purpose processor architecture and method is described. Embodiments include a plurality of special purpose processors coupled to a central processing unit via a host bridge bus, a direct bus directly coupling each of the plurality of special purpose processors to at least one other of the plurality of special purpose processors and a memory controller coupled to the plurality of special purpose processors, wherein the at least one memory controller determines whether to transmit data via the host bus or the direct bus, and whether to receive data via the host bus or the direct bus. | 10-01-2009 |
20100088452 | Internal BUS Bridge Architecture and Method in Multi-Processor Systems - An internal bus bridge architecture and method is described. Embodiments include a system with multiple bus endpoints coupled to a bus root via a host bus bridge that is internal to at least one bus endpoint. In addition, the bus endpoints are directly coupled to each other. Embodiments are usable with known bus protocols. | 04-08-2010 |
20100088453 | Multi-Processor Architecture and Method - Embodiments of a multi-processor architecture and method are described herein. Embodiments provide alternatives to the use of an external bridge integrated circuit (IC) architecture. For example, an embodiment multiplexes a peripheral bus such that multiple processors can use one peripheral interface slot without requiring an external bridge IC. Embodiments are usable with known bus protocols. | 04-08-2010 |
20100091028 | Texture Level Tracking, Feedback, and Clamping System for Graphics Processors - Embodiments include a texture mapping processor incorporating a dynamic level of detail map for use in a graphics processing system. Level of detail values are defined, with 0 being the finest and corresponding to the largest mipmap level. Each bound texture in a graphics object is assigned an identifier. This identifier is used as an index into a minimum-LOD value tracking table that is updated whenever a texel is fetched. A texture processing module controls when the tracking table is initialized and read back, and which identifiers are tracked. The minimum-LOD values in the tracking table are accompanied by a coarse region access mask to associate a minimum LOD value with a specific region of the image or object. A clamping table contains LOD clamp values for each region and a region code that specifies the coarseness of the LOD associated with each region of the texture. | 04-15-2010 |
20100141664 | Efficient GPU Context Save And Restore For Hosted Graphics - A computer graphics processing system provides efficient migrating of a GPU context as a result of a context switching operation. More specifically, the efficient migrating provides a graphics processing unit with context switch module which accelerates loading and otherwise accessing context data representing a snapshot of the state of the GPU. The snapshot includes its mapping of GPU content of external memory buffers. | 06-10-2010 |
20110304713 | INDEPENDENTLY PROCESSING PLANES OF DISPLAY DATA - Independently processing planes of display data is provided by a method of outputting a video stream. The method includes retrieving from memory a first plane of display data having a first set of display parameters and post-processing the first plane of display data to adjust the first set of display parameters. The method further includes retrieving from memory a second plane of display data having a second set of display parameters and post-processing the second plane of display data independently of the first plane of display data. The method further includes blending the first plane of display data with the second plane of display data to form blended display data and outputting the blended display data. | 12-15-2011 |
20120038657 | GPU TEXTURE TILE DETAIL CONTROL - Systems and associated methods for processing textures in a graphical processing unit (GPU) are disclosed. Textures may be managed on a per region (e.g., tile) basis, which allows efficient use of texture memory. Moreover, very large textures may be used. Techniques provide for both texture streaming, as well as sparse textures. A GPU texture unit may be used to intelligently clamp LOD based on a shader specified value. The texture unit may provide feedback to the shader to allow the shader to react conditionally based on whether clamping was used, etc. Per region (e.g., per-tile) independent mipmap stacks may be used to allow very large textures. | 02-16-2012 |
20120105473 | LOW-LATENCY FUSING OF VIRTUAL AND REAL CONTENT - A system that includes a head mounted display device and a processing unit connected to the head mounted display device is used to fuse virtual content into real content. In one embodiment, the processing unit is in communication with a hub computing device. The processing unit and hub may collaboratively determine a map of the mixed reality environment. Further, state data may be extrapolated to predict a field of view for a user in the future at a time when the mixed reality is to be displayed to the user. This extrapolation can remove latency from the system. | 05-03-2012 |
20120159090 | SCALABLE MULTIMEDIA COMPUTER SYSTEM ARCHITECTURE WITH QOS GUARANTEES - Versions of a multimedia computer system architecture are described which satisfy quality of service (QoS) guarantees for multimedia applications such as game applications while allowing platform resources, hardware resources in particular, to scale up or down over time. Computing resources of the computer system are partitioned into a platform partition and an application partition, each including its own central processing unit (CPU) and, optionally, graphics processing unit (GPU). To enhance scalability of resources up or down, the platform partition includes one or more hardware resources which are only accessible by the multimedia application via a software interface. Additionally, outside the partitions may be other resources shared by the partitions or which provide general purpose computing resources. | 06-21-2012 |
20130147815 | MULTI-PROCESSOR ARCHITECTURE AND METHOD - Embodiments of a multi-processor architecture and method are described herein. Embodiments provide alternatives to the use of an external bridge integrated circuit (IC) architecture. For example, an embodiment multiplexes a peripheral bus such that multiple processors can use one peripheral interface slot without requiring an external bridge IC. Embodiments are usable with known bus protocols. | 06-13-2013 |
20150074313 | INTERNAL BUS ARCHITECTURE AND METHOD IN MULTI-PROCESSOR SYSTEMS - An internal bus architecture and method is described. Embodiments include a system with multiple bus endpoints coupled to a bus. In addition, the bus endpoints are directly coupled to each other. Embodiments are usable with known bus protocols. | 03-12-2015 |