Patent application number | Description | Published |
20110012822 | LIQUID CRYSTAL DISPLAY - A liquid crystal display including a liquid crystal display panel including a plurality of data lines, a plurality of gate lines intersecting the data lines, and liquid crystal cells respectively formed at intersections of the data lines and the gate lines, and divided into a first area, a second area and a third area, a first data integrated circuit (IC) that drives the first area, a second data IC that drives the second area, a third data IC that drives the third area, and a timing controller that analyzes an input digital video data, generates a first selection signal and a second selection signal for controlling whether charge sharing is used, and independently controls the first, second, and third data ICs using the first and second selection signals, wherein the second area is divided into a first block adjoining the first area, a third block adjoining the third area and a second block located between the first block and the third block; and the first selection signal controls whether the charge sharing is used for the first and third data ICs, and the second selection signal controls whether the charge sharing is used for the second block and controls a charging delay variation so that the charging delay variation is lessened between the second block and the first area or between the second block and the third area in the first or third block. | 01-20-2011 |
20130235055 | DISPLAY DEVICE AND METHOD FOR CONTROLLING PANEL SELF REFRESH OPERATION THEREOF - A display device includes a source unit; and a sink unit connected with the source unit via an embedded display port interface for signal transmission between the source and sink units and to enable a panel self refresh (PSR) mode for reducing power, wherein, for an input still image, the source unit applies power to a frame buffer of the sink unit and transmits the still image to the sink unit, wherein the sink unit determines whether the still image can be losslessly compressed and stored in the frame buffer, outputs a first control signal if the still image can be losslessly compressed and stored in the frame buffer, and outputs a second control signal if the still image cannot be losslessly compressed and stored, and wherein the source unit activates the PSR mode for the first control signal, and deactivates the PSR mode for the second control signal. | 09-12-2013 |
Patent application number | Description | Published |
20100148829 | LIQUID CRYSTAL DISPLAY AND METHOD OF DRIVING THE SAME - A liquid crystal display and a method of driving the same are disclosed. The liquid crystal display includes a timing controller, N source drive integrated circuits (ICs), where N is an integer equal to or greater than 2, N pairs of data bus lines, each of which connects the timing controller to each of the N source drive ICs in a point-to-point manner, a lock check line that connects a first source drive IC of the N source drive ICs to the timing controller and cascade-connects the N source drive ICs to one another, a feedback check line that connects a last source drive IC of the N source drive ICs to the timing controller. | 06-17-2010 |
20100149082 | Liquid crystal display and method of driving the same - A liquid crystal display and a method of driving the same are disclosed. The liquid crystal display includes a timing controller, N source drive integrated circuits (ICs), where N is an integer equal to or greater than 2, N pairs of data bus lines, each of which connects the timing controller to each of the N source drive ICs in a point-to-point manner, a lock check line that connects a first source drive IC of the N source drive ICs to the timing controller and cascade-connects the N source drive ICs to one another, and a feedback lock check line that connects a last source drive IC of the N source drive ICs to the timing controller. | 06-17-2010 |
20100156879 | LIQUID CRYSTAL DISPLAY AND METHOD OF DRIVING THE SAME - A liquid crystal display and a method of driving the same are provided. The liquid crystal display includes a first source drive IC group outputting a first feedback lock signal in response to one of a power voltage input through a first lock signal input terminal and a lock signal from the timing controller, a second source drive IC group outputting a second feedback lock signal in response to one of the power voltage input through a second lock signal input terminal, the lock signal from the timing controller, and a lock signal transferred from the first source drive IC group, and a comparator that compares the first feedback lock signal with the second feedback lock signal and supplies a comparison result to the timing controller. | 06-24-2010 |
20120098813 | LIQUID CRYSTAL DISPLAY - A liquid crystal display comprises: a first data drive circuit that supplies a data voltage to data lines present in a first portion and a third portion on the screen of a liquid crystal display panel in response to a first source output enable signal; and a second data drive circuit that supplies the data voltage to data lines present in a second portion and a fourth portion on the screen of the liquid crystal display panel in response to a second source output enable signal. The first source output enable signal controls the data voltage output timing and charge sharing timing of the first data drive circuit. The second source output signal controls the data output timing and charge sharing timing of the second data drive circuit in a different way from the first data drive circuit. | 04-26-2012 |
20140118235 | DISPLAY DEVICE AND METHOD FOR DRIVING THE SAME - A display device and a method for driving the same are discussed. The display device includes a display panel including data lines, gate lines crossing the data lines, and pixels, and source driver integrated circuits (ICs) which are connected to a timing controller through data line pairs, recover control information of a control data packet input from the timing controller, and supply a data voltage to the data lines. The timing controller sets the number of control data packets transmitted in a horizontal blank period to be less than the number of control data packets transmitted in a period except the horizontal blank period. The source driver ICs read the number of control data packets based on start information transmitted prior to the control data packet. | 05-01-2014 |