Patent application number | Description | Published |
20100030933 | NON-VOLATILE MEMORY STORAGE DEVICE AND OPERATION METHOD THEREOF - A non-volatile memory storage device has a non-volatile memory, e.g., a flash memory, and a controller coupled to the non-volatile memory. The controller comprises a plurality of control circuits and an arbitration circuit. Each control circuit is configured to generate a request to update the chip-enable (CE) signals for non-volatile memory, and the arbitration circuit is configured to determine when the requests are acknowledged. The arbitration circuit generates acknowledge signals to the control circuits when all of the requests of the control circuits have been received by the arbitration circuit. The CE signals for non-volatile memory are updated when requests are acknowledged. | 02-04-2010 |
20100293309 | Production Tool For Low-Level Format Of A Storage Device - A production tool for low-level format of a storage device is disclosed. The production tool includes an input connector connectable and an output connector, both of which conform to an interface standard. At least a redundant pin of the input connector is unconnected with a corresponding redundant pin of the output connector, and the redundant pin of the output connector is electrically connected to receive a provided predetermined signal, the presence of which indicating a low-level format mode. | 11-18-2010 |
20110055659 | Method and System of Dynamic Data Storage for Error Correction in a Memory Device - A method of dynamic data storage for error correction in a memory device is disclosed. Data for storage is received, and the received data is then encoded and associated error correction code (ECC) is generated. The encoded data is stored in a portion of a data partition of the memory device, wherein percentage of the stored data in the data partition is determined according to an amount of corrected errors associated with the data partition or is predetermined. | 03-03-2011 |
20110131459 | Memory Device with Protection Capability and Method of Accessing Data Therein - The present invention is directed to a memory device with protection capability and a method of accessing data therein. A spreader encrypts input user data according to an entered password, and the encrypted data is then stored in a storage area. A despreader performs reverse process of the spreader on the stored data according to the entered password. | 06-02-2011 |
Patent application number | Description | Published |
20130240923 | HIGH BRIGHTNESS LIGHT EMITTING DIODE STRUCTURE AND THE MANUFACTURING METHOD THEREOF - A light-emitting diode structure comprising: a substrate; a light-emitting semiconductor stack on the substrate, wherein the light-emitting semiconductor stack comprises a first semiconductor layer, a second semiconductor layer with different polarity from the first semiconductor layer, and a light-emitting layer between the first semiconductor layer and the second semiconductor layer; a first electrical pad on the substrate, wherein the first electrical pad is apart from the light-emitting semiconductor stack and electrically connects to the first semiconductor layer; and a second electrical pad on the substrate, wherein the second electrical pad is apart from the light-emitting semiconductor stack and electrically connects to the second semiconductor layer, wherein the first electrical pad and the second electrical pad are not higher than the light-emitting semiconductor stack. | 09-19-2013 |
20140124807 | Light Emitting Device - A light-emitting device, comprising: a substrate; a semiconductor stacking layer comprising a first type semiconductor layer on the substrate, an active layer on the first semiconductor layer, and a second semiconductor layer on the active layer; and an electrode structure on the second semiconductor layer, wherein the electrode structure comprises a bonding layer, a conductive layer, and a first barrier layer between the bonding layer and the conductive layer; wherein the conductive layer has higher standard oxidation potential than that of the bonding layer. | 05-08-2014 |
20140124819 | LIGHT-EMITTING DEVICE - A light-emitting device comprises a first semiconductor layer; and a transparent conductive oxide layer comprising a diffusion region having a first metal material and a non-diffusion region devoid of the first metal material, wherein the non-diffusion region is closer to the first semiconductor layer than the diffusion region. | 05-08-2014 |
20150060909 | LIGHT-EMITTING DEVICE AND THE MANUFACTURING METHOD THEREOF - A light-emitting device comprises: a first semiconductor layer; a transparent conductive oxide layer including a diffusion region having a first metal material and a non-diffusion region devoid of the first metal material, wherein the non-diffusion region is closer to the first semiconductor layer than the diffusion region; and a metal layer formed on the transparent conductive oxide layer, wherein the metal layer is pervious to a light emitted from the active layer and comprises a pattern. | 03-05-2015 |
Patent application number | Description | Published |
20100109124 | METHOD OF FORMING A METAL-INSULATOR-METAL CAPACITOR - A method of forming a metal-insulator-metal capacitor has the following steps. A stack dielectric structure is formed by alternately depositing a plurality of second dielectric layers and a plurality of third dielectric layers. A wet etch selectivity of the second dielectric layer relative to said third dielectric layer is of at least 5:1. An opening is formed in the stack dielectric structure, and then a wet etch process is employed to remove relatively-large portions of the second dielectric layers and relatively-small portions of the third dielectric layers to form a plurality of lateral recesses in the second dielectric layers along sidewalls of the opening. A bottom electrode layer is formed to extend along the serrate sidewalls, a capacitor dielectric layer is formed on the bottom electrode layer, and a top electrode layer is formed on the capacitor dielectric layer. | 05-06-2010 |
20100127316 | STRUCTURE FOR PROTECTING METAL-INSULATOR-METAL CAPACITOR IN MEMORY DEVICE FROM CHARGE DAMAGE - A dynamic random access memory (DRAM) device has a metal-insulator-metal (MIM) capacitor electrically connected to a PN junction diode through a metal bridge for protecting the MIM capacitor from charge damage generated in back end of line (BEOL) plasma process. | 05-27-2010 |
20130292794 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING - A semiconductor device includes a semiconductor substrate, an isolation structure disposed in the semiconductor substrate, a conductive layer disposed over the isolation structure, a capacitor disposed over the isolation structure, the capacitor including a top electrode, a bottom electrode, and a dielectric disposed between the top electrode and the bottom electrode, and a first contact electrically coupling the conductive layer and the bottom electrode, the bottom electrode substantially engaging the first contact on at least two faces. | 11-07-2013 |
20140091271 | RESISTANCE VARIABLE MEMORY STRUCTURE AND METHOD OF FORMING THE SAME - A semiconductor structure includes a resistance variable memory structure. The semiconductor structure also includes a dielectric layer. A portion of the resistance variable memory structure is over the dielectric layer. The resistance variable memory structure includes a first electrode embedded in the dielectric layer. A resistance variable layer disposed over the first electrode and a portion of the dielectric layer. A second electrode disposed over the resistance variable layer. | 04-03-2014 |
20140091272 | RESISTANCE VARIABLE MEMORY STRUCTURE AND METHOD OF FORMING THE SAME - A semiconductor structure includes a resistance variable memory structure. The semiconductor structure also includes a conductive structure. The resistance variable memory structure is over the conductive structure. The resistance variable memory structure includes a first electrode over the conductive structure. A resistance variable layer is disposed over the first electrode. A cap layer is disposed over the resistance variable layer. The cap layer includes a first metal material. A second electrode disposed over the cap layer. The second electrode includes a second metal material different from the first metal material. | 04-03-2014 |
20140120689 | METHOD OF FABRICATING SEMICONDUCTOR DEVICE - A method of fabricating a semiconductor device includes forming a first insulating layer over a semiconductor substrate, a contact plug within the first insulating layer, an etch stop layer over the first insulating layer, and a second insulating layer over the etch stop layer. The second insulating layer has an opening over the contact plug. A first metal layer, a dielectric material, and a second metal layer are deposited in the opening. The first metal layer engages the contact plug and is free of direct contact with the first insulating layer. | 05-01-2014 |
20140131650 | RESISTANCE VARIABLE MEMORY STRUCTURE - A semiconductor structure includes a resistance variable memory structure. The semiconductor structure also includes a dielectric layer. The resistance variable memory structure is over the dielectric layer. The resistance variable memory structure includes a first electrode disposed over the dielectric layer. The first electrode has a sidewall surface. A resistance variable layer has a first portion which is disposed over the sidewall surface of the first electrode and a second portion which extends from the first portion away from the first electrode. A second electrode is over the resistance variable layer. | 05-15-2014 |
20140166961 | RESISTIVE RANDOM ACCESS MEMORY (RRAM) AND METHOD OF MAKING - The present disclosure provides a resistive random access memory (RRAM) cells and methods of making the same. The RRAM cell includes a transistor and an RRAM structure electrically connected to the transistor. The RRAM structure includes a bottom electrode having a via portion and a top portion, a resistive material layer over the bottom electrode and having a same width as the top portion of the bottom electrode, and a top electrode over the resistive material layer and having a smaller width than the resistive material layer. | 06-19-2014 |
20140175365 | RESISTIVE RANDOM ACCESS MEMORY (RRAM) STRUCTURE AND METHOD OF MAKING THE RRAM STRUCTURE - The present disclosure provides a resistive random access memory (RRAM) cell. The RRAM cell includes a transistor, a bottom electrode adjacent to a drain region of the transistor and coplanar with the gate, a resistive material layer on the bottom electrode, a top electrode on the resistive material layer, and a conductive material connecting the bottom electrode to the drain region. | 06-26-2014 |
20140175366 | RESISTANCE VARIABLE MEMORY STRUCTURE AND METHOD OF FORMING THE SAME - A semiconductor structure includes a resistance variable memory structure. The semiconductor structure also includes a dielectric layer. The resistance variable memory structure is over the dielectric layer. The resistance variable memory structure includes a first electrode disposed over the dielectric layer. The first electrode has a sidewall surface. A resistance variable layer has a first portion which is disposed over the sidewall surface of the first electrode and a second portion which extends from the first portion away from the first electrode. A second electrode is over the resistance variable layer. | 06-26-2014 |
20140264233 | RESISTANCE VARIABLE MEMORY STRUCTURE AND METHOD OF FORMING THE SAME - A semiconductor structure includes a memory region. A memory structure is disposed on the memory region. The memory structure includes a first electrode, a resistance variable layer, protection spacers and a second electrode. The first electrode has a top surface and a first outer sidewall surface on the memory region. The resistance variable layer has a first portion and a second portion. The first portion is disposed over the top surface of the first electrode and the second portion extends upwardly from the first portion. The protection spacers are disposed over a portion of the top surface of the first electrode and surround at least the second portion of the resistance variable layer. The protection spacers are configurable to protect at least one conductive path in the resistance variable layer. The protection spacers have a second outer sidewall surface substantially aligned with the first outer sidewall surface of the first electrode. The second electrode is disposed over the resistance variable layer. | 09-18-2014 |
20140264234 | RESISTANCE VARIABLE MEMORY STRUCTURE AND METHOD OF FORMING THE SAME - A semiconductor structure includes a memory region. A memory structure is disposed on the memory region. The memory structure includes a first electrode, a resistance variable layer, a protection material and a second electrode. The first electrode has a top surface on the memory region. The resistance variable layer has at least a first portion and a second portion. The first portion is disposed over the top surface of the first electrode and the second portion extends upwardly from the first portion. The protection material surrounds the second portion of the resistance variable layer. The protection material is configurable to protect at least one conductive path in the resistance variable layer. The second electrode is disposed over the resistance variable layer. | 09-18-2014 |
20140264749 | SEMICONDUCTOR DEVICE - A semiconductor device includes a first insulating layer, a contact plug formed in the first insulating layer, a first etch stop layer over the first insulating layer, a second etch stop layer over the first etch stop layer, a second insulating layer over the second etch stop layer and having a contact opening over the contact plug, and a conductive layer disposed in the contact opening and over the contact plug. The contact opening is substantially free of the second etch stop layer, and the first etch stop layer is present in the contact opening. | 09-18-2014 |
Patent application number | Description | Published |
20110032129 | INTEGRATED CIRCUITS, LIQUID CRYSTAL DISPLAY (LCD) DRIVERS, AND SYSTEMS - An integrated circuit includes a digital-to-analog converter (DAC) circuit including at least one first channel type DAC and at least one second channel type DAC. The integrated circuit includes a plurality of sample and hold (S/H) circuits. Each of the S/H circuits is coupled with one of the DAC circuit. The S/H circuits are capable of receiving signals from the DAC circuit and outputting the signals in parallel. | 02-10-2011 |
20110261084 | DAC ARCHITECTURE FOR LCD SOURCE DRIVER - A two-stage digital-to-analog converter for outputting an analog voltage in response to a M-bit digital input code includes a two-bit serial charge redistribution digital-to-analog converter having a high reference voltage input node for receiving a high reference voltage and a low reference voltage input node for receiving a low reference voltage, and a voltage selector. The voltage selector sets the high reference voltage and low reference voltage to selected levels depending on at least a portion of the M-bit digital input code. | 10-27-2011 |
20110261085 | TWO-STAGE DAC ACHITECTURE FOR LCD SOURCE DRIVER UTILIZING ONE-BIT PIPE DAC - A two-stage digital-to-analog converter for outputting an analog voltage in response to a M-bit digital input code includes a one-bit serial charge redistribution digital-to-analog converter having a high reference voltage input node for receiving a high reference voltage and a low reference voltage input node for receiving a low reference voltage, and a voltage selector. The voltage selector sets the high reference voltage and low reference voltage to selected levels depending on at least a portion of the M-bit digital input code. | 10-27-2011 |
20110261086 | TWO-STAGE DAC ARCHITECTURE FOR LCD SOURCE DRIVER UTILIZING ONE-BIT SERIAL CHARGE REDISTRIBUTION DAC - A two-stage digital-to-analog converter for outputting an analog voltage in response to a M-bit digital input code includes a one-bit serial charge redistribution digital-to-analog converter having a high reference voltage input node for receiving a high reference voltage and a low reference voltage input node for receiving a low reference voltage. A voltage selector sets the high reference voltage and low reference voltage to selected levels depending on at least a portion of the M-bit digital input code. | 10-27-2011 |
20120218132 | INTEGRATED CIRCUITS, LIQUID CRYSTAL DISPLAY (LCD) DRIVERS, AND SYSTEMS - An integrated circuit includes a digital-to-analog converter (DAC) circuit including at least one first channel type DAC and at least one second channel type DAC. The integrated circuit includes a plurality of sample and hold (S/H) circuits. Each of the S/H circuits is coupled with the DAC circuit. The S/H circuits are capable of receiving signals from the DAC circuit and outputting the signals in parallel. | 08-30-2012 |
20120218235 | Systems And Methods Providing Active And Passive Charge Sharing In A Digital To Analog Converter - A method for converting a multi-bit digital value to an analog value. The method includes, in a first conversion cycle, converting a first set of digital bits to a first analog voltage using passive charge-sharing. The method also includes, in a second conversion cycle, converting a second set of digital bits to a second analog voltage added to the first analog voltage using active charge-sharing. The first set of digital bits and the second set of digital bits are different bits of the multi-bit digital value. | 08-30-2012 |
Patent application number | Description | Published |
20110186856 | LIGHT EMITTING ELEMENT AND METHOD FOR MANUFACTURING THE SAME - A method for manufacturing a light emitting element includes providing a substrate, forming a buffer layer on the substrate, forming a GaN layer on the buffer layer, forming a rough layer on the GaN layer at low temperature, and forming an epitaxial layer on the rough layer, wherein a refraction index of the epitaxial layer exceeds a refraction index of the rough layer. Thus, most light scatters at the rough layer, and then emits upwardly to a light emitting surface, enhancing light extraction efficiency thereof. An epitaxial process of the method is processed in situ in an MOCVD reactor. | 08-04-2011 |
20120043523 | LIGHT EMITTING DIODE AND MANUFACTURING METHOD THEREOF - A light emitting diode comprises a substrate, a buffer layer, a semiconductor layer and a semiconductor light emitting layer. The buffer layer is disposed on the substrate. The semiconductor layer is disposed on the buffer layer. The semiconductor light emitting layer is disposed on the semiconductor layer. A plurality of voids is defined within the semiconductor layer. Each void encloses air therein. A method for manufacturing the light emitting diode is also provided. Light generated by the semiconductor light emitting layer toward the substrate is reflected by the voids to emit out of the light emitting diode. | 02-23-2012 |
20120256162 | LIGHT EMITTING DIODE AND MANUFACTURING METHOD THEREOF - A light emitting diode includes a substrate, an N-type semiconductor layer arranged on the substrate, an active layer, and a P-type semiconductor layer. The active layer includes a first barrier layer, a second barrier layer, and a quantum well structure layer arranged between the first and second barrier layers. The quantum well structure layer includes an InN layer, a GaN layer and an InGaN layer arranged on the first barrier layer in sequence. The InN layer has an upper surface connected to the GaN layer. The upper surface is rough. The InGaN layer has a concentration of In atoms in some regions of the InGaN layer which is higher that that in other regions thereof. The P-type semiconductor layer is arranged on the second barrier layer. | 10-11-2012 |
20130092951 | GALLIUM NITRIDE-BASED SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A gallium nitride-based semiconductor device includes a composite substrate and a gallium nitride layer. The composite substrate includes a silicon substrate and a filler. The silicon substrate includes a first surface and a second surface opposite to the first surface, and the first surface defines a number of grooves therein. The filler is filled into the number of grooves on the first surface of the silicon substrate. A thermal expansion coefficient of the filler is bigger than that of the silicon substrate. The gallium nitride layer is formed on the second surface of the silicon substrate. | 04-18-2013 |
20130248922 | FLIP-CHIP SEMICONDUCTOR OPTOELECTRONIC DEVICE AND METHOD FOR FABRICATING THE SAME - A method for fabricating flip-chip semiconductor optoelectronic devices initially flip-chip bonds a semiconductor optoelectronic chip attached to an epitaxial substrate to a packaging substrate. The epitaxial substrate is then separated using lift-off technology. | 09-26-2013 |
20130285216 | SEMICONDUCTOR STRUCTURE HAVING LOW THERMAL STRESS - A semiconductor structure includes a Si substrate, a supporting layer and a blocking layer formed on the substrate and an epitaxy layer formed on the supporting layer. The supporting layer defines a plurality of grooves therein to receive the blocking layer. The epitaxy layer is grown from the supporting layer. A plurality of slots is defined in the epitaxy layer and over the blocking layer. The epitaxy layer includes an N-type semiconductor layer, a light-emitting layer and a P-type semiconductor layer. | 10-31-2013 |
20130313515 | LIGHT EMITTING DIODE WITH MULTIPLE QUANTUM WELL STRUCTURE - An exemplary light emitting diode includes a first type semiconductor layer, a second type semiconductor layer, and a multi quantum well layer sandwiched between the first and second type semiconductor layers. The multi quantum well layer includes a first barrier layer, a second barrier layer, two well layers sandwiched between the first and second barrier layers, and a third barrier layer sandwiched between the two well layers. The first and second barrier layers each have an energy level of conduction band higher than that of the third barrier layer. The first and second barrier layers each have an energy level of valence band higher than that of the third barrier layer. | 11-28-2013 |
20140014899 | MULTI-QUANTUM WELL STRUCTURE AND LIGHT EMITTING DIODE HAVING THE SAME - A multi-quantum well structure includes two first barrier layers, two well layers sandwiched between the two first barrier layers, and a doped second barrier layer sandwiched between the two well layers. The second barrier layer has its conduction band and forbidden band gradually transiting to those of one of the well layers, and a dopant concentration of the second barrier layer gradually changes along a direction from one well layer to the other. The invention also relates to a light emitting diode structure having the multi-quantum well structure. | 01-16-2014 |
20140021486 | LIGHT EMITTING DIODE AND MANUFACTURING METHOD THEREOF - A light emitting diode (LED) includes a substrate and an eputaxial layer on the substrate. The epitaxial layer includes a N-type GaN-based layer, a light emitting layer, and a P-type GaN-based layer. The LED further includes a first electrode on the N-type GaN-based layer and a second electrode on the P-type GaN-based layer. The P-type GaN-based layer has a inactive portion, and the second electrode is located and covers the inactive portion. | 01-23-2014 |
20140065743 | METHOD OF MANUFACTURING LIGHT EMITTING DIODE DIE - An exemplary method of manufacturing a light emitting diode (LED) die includes steps: providing a preformed LED structure, the LED structure including a first substrate, and a nucleation layer, a buffer layer, an N-type layer, a muti-quantum well layer and an P-type layer formed successively on the first substrate; forming at least one insulation block on the P-type layer; forming a mirror layer on the on the P-type layer and covering the insulation block; forming a conductive second substrate on the mirror layer; removing the first substrate, the nucleation layer and the buffer layer and exposing a bottom surface of the N-type layer; and disposing one N-electrode on the exposed surface of the N-type layer. The N-electrode is located corresponding to the insulation block. | 03-06-2014 |
20140073077 | METHOD FOR EPITAXIAL GROWTH OF LIGHT EMITTING DIODE - A method for epitaxial growth of a light emitting diode, includes following steps: providing a substrate; forming a buffer layer on the substrate; forming a first epitaxial layer on the buffer layer in a first temperature; forming a second epitaxial layer on the first epitaxial layer in a second temperature lower than the first temperature, thereby forming a first rough surface on the second epitaxial layer; etching the second epitaxial layer and the first epitaxial layer until a second rough surface is formed on the first epitaxial layer; forming a mask layer on the rough surface of the first epitaxial layer; partly etching the mask layer to form a plurality of protrusions with the first epitaxial layer exposed thereamong; and forming an N-type epitaxial layer, an active layer and a P-type epitaxial layer on the first epitaxial layer in sequence. | 03-13-2014 |
20140131727 | LIGHT EMITTING DIODE CHIP AND METHOD FOR MANUFACTURING THE SAME - A method for manufacturing a light emitting diode chip includes following steps: providing a sapphire substrate, the sapphire substrate having a plurality of protrusions on an upper surface thereof; forming an un-doped GaN layer on the upper surface of the sapphire substrate, the un-doped GaN layer having an upper part covering top ends of the protrusions; forming a distributed bragg reflective layer on the un-doped GaN layer until the distributed bragg reflective layer totally covering the protrusions and the un-doped GaN layer; etching the distributed bragg reflective layer and the upper part of the un-doped GaN layer to expose the top ends of the protrusions; and forming an n-type GaN layer, an active layer, and a p-type GaN layer sequentially on the top ends of the protrusions and the distributed bragg reflective layer. An LED chip formed by the method described above is also provided. | 05-15-2014 |
20140134774 | METHOD FOR MAKING LIGHT EMITTING DIODE CHIP - A method for making a light emitting diode chip includes following steps: providing a sapphire substrate, the sapphire substrate having a plurality of protrusions on an upper surface thereof; forming an un-doped GaN layer on the upper surface of the sapphire substrate, the un-doped GaN layer partly covering the protrusions to expose a part of each of the protrusions; etching the un-doped GaN layer to expose a top end of each of the protrusions; and forming an n-type GaN layer, an active layer, and a p-type GaN layer sequentially on the top ends of the protrusions and the un-doped GaN layer. | 05-15-2014 |
20140141553 | METHOD FOR MANUFACTURING LIGHT EMITTING DIODE CHIP - A method for manufacturing a light emitting diode chip includes following steps: providing a sapphire substrate, the sapphire substrate having a plurality of protrusions on an upper surface thereof; forming an un-doped GaN layer on the upper surface of the sapphire substrate, the un-doped GaN layer totally covering the protrusions; forming a plurality of semiconductor islands on an upper surface of the un-doped GaN layer by self-organized growth, gaps being formed between two adjacent semiconductor islands to expose a part of the upper surface of the un-doped GaN layer; forming an n-type GaN layer on the exposed part of the upper surface of the un-doped GaN layer, the n-type GaN layer being laterally grown to totally cover the semiconductor islands; forming an active layer on an upper surface of the n-type GaN layer; and forming a p-type GaN layer on the active layer. | 05-22-2014 |
20140170925 | METHOD FOR MANUFACTURING LIQUID CRYSTAL DISPLAY PANEL - A method of manufacturing an LCD panel includes following steps: providing a first translucent panel, the first translucent panel including an upper surface and a lower surface opposite to the upper surface, a middle of the top surface depressed inwardly and thereby defining a recess; providing glue on the upper surface, and the glue being located outside of the recess, the glue capable of being solidified when irradiated by UV light; providing a second translucent panel which covers the upper surface of the first translucent panel; a room being cooperatively defined by the recess of the first translucent panel and the second translucent panel; filling the room with liquid crystal; and providing a UV LED light source which is moved around lateral sides of the first and second translucent panels to irradiate the glue, thereby solidifying the glue. | 06-19-2014 |
20140183445 | LIGHT EMITTING DIODE CHIP AND METHOD FOR MANUFACTURING THE SAME - An LED package includes a substrate, a buffer layer formed on the substrate, an epitaxial structure formed on the buffer layer, and a plurality of carbon nanotube bundles formed in the epitaxial structure. | 07-03-2014 |
20150034965 | LIGHT EMITTING DIODE AND METHOD FOR MANUFACTURING SAME - An LED includes a substrate and a semiconductor structure mounted on the substrate. A plurality of first holes and a plurality of second holes are defined in the semiconductor structure. The second holes are located above the first holes and communicate with the first holes. A method for manufacturing the LED is also provided. | 02-05-2015 |