Park, Ichon-Shi
Byoung Kwon Park, Ichon-Shi KR
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20120106271 | SEMICONDUCTOR MEMORY APPARATUS - Various embodiments of a semiconductor memory apparatus are disclosed. In one exemplary embodiment, the semiconductor memory apparatus may include: a redundancy signal generation unit configured to compare mat information set by fuse cutting with address information inputted from outside and generate a plurality of redundancy signals; a mat designation signal generation unit configured to generate a plurality of mat designation signals in response to the plurality of redundancy signals and a plurality of mat address signals; and a mat control signal generation group configured to enable one of the mat control signals in response to the plurality of mat designation signals. | 05-03-2012 |
Byung-Ii Park, Ichon-Shi KR
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20090059696 | Multi-port memory device - There is provided a column repair technology of a semiconductor memory device. The semiconductor memory device includes: a normal bus connection part for transmitting/receiving data between global data buses and local data buses of each bank; a redundant bus connection part for transmitting/receiving data between global data buses and local data buses of each bank; a fuse set having a physical position information of a fail column; and a switching part for selectively connecting outputs of the normal bus connection part and the redundant bus connection part to the global data buses, which corresponds to the fail column, in response to the physical position information of the fail column. The column redundancy scheme can be applied to semiconductor memory devices having such a structure that a lot of column selection lines are enabled with respect to one column address and can also be applied to a case when a fail column address is not present. Therefore, the redundancy efficiency can be improved and an increase of the chip area can be prevented. | 03-05-2009 |
Chang Kun Park, Ichon-Shi KR
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20100090736 | DELAY LOCKED LOOP CIRCUIT AND MEMORY DEVICE HAVING THE SAME - A DLL circuit includes a multiphase clock signal generating unit configured to produce a plurality of multiphase clock signals by delaying a reference clock signal for a unit delay time and to produce an enable signal that is enabled when one of the plurality of the multiphase clock signals synchronizes with the reference clock signal at a frequency, and a multiphase clock signal selecting unit configured to delay one of the plurality of the multiphase clock signals for a predetermined time in response to a first control signal, to compare a phase of a delayed multiphase clock signal with a phase of the reference clock signal, and to output one of the plurality of the multiphase clock signals as a delayed clock signal, wherein a phase of the delayed clock signal synchronizes with the phase of the reference clock signal when the enable signal is enabled. | 04-15-2010 |
Heat Bit Park, Ichon-Shi KR
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20110161753 | SEMICONDUCTOR MEMORY APPARATUS INCLUDING DATA COMPRESSION TEST CIRCUIT - A semiconductor memory apparatus having stacked first and second chips includes a first chip test signal generation unit disposed in the first chip and configured to generate a first chip test signal in response to a first chip compression data determination signal in a test mode, a second chip test signal generation unit disposed in the second chip and configured to generate a second chip test signal in response to a second chip compression data determination signal in the test mode, and a final data determination unit configured to generate a final test to signal in response to the first and second chip test signals in the test mode. | 06-30-2011 |
20110242907 | SEMICONDUCTOR MEMORY APPARATUS AND READ/WRITE CONTROL METHOD THEREOF - A semiconductor memory apparatus includes: a read/write control unit configured to generate a write control signal and a read control signal using internal signals generated through separate signal paths in response to a write command and a read command respectively; and a plurality of ranks configured to perform a write operation or read operation according to the write control signal or the read control signal. | 10-06-2011 |
20120105124 | SEMICONDUCTOR APPARATUS, METHOD FOR DELAYING SIGNAL THEREOF, STACKED SEMICONDUCTOR MEMORY APPARATUS, AND METHOD FOR GENERATING SIGNAL THEREOF - The semiconductor apparatus includes a reference delay value check unit configured to receive a source signal and delay the source signal to generate a reference delay signal; a process delay value check unit configured to receive the source signal and delay the source signal to generate a process delay signal; and a signal generation unit configured to receive the reference delay signal and the process delay signal, receive an input signal, and variably delay the input signal based on the reference delay signal and the process delay signal to generate an output signal. | 05-03-2012 |
20130315015 | SEMICONDUCTOR APPARATUS, METHOD FOR DELAYING SIGNAL THEREOF, STACKED SEMICONDUCTOR MEMORY APPARATUS, AND METHOD FOR GENERATING SIGNAL THEREOF - The semiconductor apparatus includes a reference delay value check unit configured to receive a source signal and delay the source signal to generate a reference delay signal; a process delay value check unit configured to receive the source signal and delay the source signal to generate a process delay signal; and a signal generation unit configured to receive the reference delay signal and the process delay signal, receive an input signal, and variably delay the input signal based on the reference delay signal and the process delay signal to generate an output signal. | 11-28-2013 |
Hyung-Soon Park, Ichon-Shi KR
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20090117739 | METHOD FOR FORMING PATTERN IN SEMICONDUCTOR DEVICE - A method for forming a pattern in a semiconductor device includes forming an etch-target layer over a substrate, wherein the substrate includes a first region having a smaller pattern than the first region, forming a sacrificial layer and a passivation layer over the etch-target layer, etching the passivation layer and the sacrificial layer to form stack structures including a sacrificial pattern and a passivation pattern, forming spacers over sidewalls of the stack structures, forming a mask pattern covering the second region, removing a portion of the passivation pattern in the first region exposed by the mask pattern to expose a portion of the sacrificial pattern in the first region, removing the exposed portion of the sacrificial pattern in the first region, and etching the etch-target layer to form an etch-target pattern using the spacers in the first and second regions and the stack structure formed between the spacers in the second region. | 05-07-2009 |
Hyun-Sik Park, Ichon-Shi KR
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20090163010 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE - A method for fabricating a semiconductor device includes forming a plurality of gate patterns including a tungsten electrode over a substrate, performing a plasma oxidation process to form a capping layer on the surfaces of the gate patterns, forming an etch barrier layer over the substrate where the capping layer is formed, forming an interlayer dielectric layer to fill gap between the gate patterns, and etching the interlayer dielectric layer between the gate patterns to form a contact hole. | 06-25-2009 |
Jae Boum Park, Ichon-Shi KR
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20110291747 | VOLTAGE GENERATION CIRCUIT - A voltage generation circuit includes: a first and second rectification circuits; and one or more amplification units connected between the first and second rectification circuits and configured to amplify an output of the first rectification circuit and provide the amplified output to the second rectification circuit. The second rectification circuit generates a reference voltage. | 12-01-2011 |
Jae-Gun Park, Ichon-Shi KR
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20120044767 | NON-VOLATILE MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME - A non-volatile memory device includes a plurality of unit cells. Each unit cell includes lower and upper electrodes over a substrate, a conductive organic material layer between the lower and the upper electrodes, and a nanocrystal layer located within the conductive organic material layer, wherein the nanocrystal layer includes a plurality of nanocrystals surrounded by an amorphous barrier. A read operation is performed when an input voltage is in a first voltage range. A first write operation is performed when the input voltage is in a second voltage range higher than the first voltage range. A second write operation is performed when the input voltage is in a third voltage range higher than the second voltage range. An erase operation is performed when the input voltage is higher than the third voltage range. | 02-23-2012 |
Jea-Gun Park, Ichon-Shi KR
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20090040805 | NON-VOLATILE MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME - A non-volatile memory device includes lower and upper electrodes over a substrate, a conductive organic material layer between the lower and the upper electrodes, and a nanocrystal layer located within the conductive organic material layer, wherein the nanocrystal layer includes a plurality of nanocrystals surrounded by an amorphous barrier, wherein the device has a multi-level output current according to a voltage level of an input voltage coupled to the lower and the upper electrodes during a data read operation. | 02-12-2009 |
Jong-Bum Park, Ichon-Shi KR
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20080224264 | CAPACITOR AND METHOD FOR FABRICATING THE SAME - A capacitor includes a lower electrode, a first dielectric layer formed over the lower electrode, a second dielectric layer formed over the first dielectric layer, wherein the second dielectric layer includes an amorphous high-k dielectric material, a third dielectric layer formed over the second dielectric layer, and an upper electrode formed over the third dielectric layer. | 09-18-2008 |
20100255217 | METHOD FOR FORMING A CAPACITOR DIELECTRIC AND METHOD FOR MANUFACTURING CAPACITOR USING THE CAPACITOR DIELECTRIC - A method for forming a capacitor dielectric includes depositing a tantalum oxide layer over a substrate, performing a post-treatment on the tantalum oxide layer to provide the tantalum oxide layer with a tetragonal phase, and depositing a zirconium oxide layer over the tantalum oxide layer such that the zirconium oxide layer has a tetragonal phase. | 10-07-2010 |
20110116209 | CAPACITOR AND METHOD FOR FABRICATING THE SAME - A capacitor includes a lower electrode, a first dielectric layer formed over the lower electrode, a second dielectric layer formed over the first dielectric layer, wherein the second dielectric layer includes an amorphous high-k dielectric material, a third dielectric layer formed over the second dielectric layer, and an upper electrode formed over the third dielectric layer. The third dielectric layer can be thicker than the first dielectric layer. | 05-19-2011 |
20130058007 | METHOD FOR FORMING A CAPACITOR DIELECTRIC AND METHOD FOR MANUFACTURING A CAPACITOR USING THE CAPACITOR DIELECTRIC - A method for forming a capacitor dielectric includes depositing a zirconium oxide layer, performing a post-treatment on the zirconium oxide layer such that the zirconium oxide layer has a tetragonal phase, and depositing a tantalum oxide layer over the zirconium oxide layer such that the tantalum oxide layer has a tetragonal phase. | 03-07-2013 |
Jum-Yong Park, Ichon-Shi KR
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20090117739 | METHOD FOR FORMING PATTERN IN SEMICONDUCTOR DEVICE - A method for forming a pattern in a semiconductor device includes forming an etch-target layer over a substrate, wherein the substrate includes a first region having a smaller pattern than the first region, forming a sacrificial layer and a passivation layer over the etch-target layer, etching the passivation layer and the sacrificial layer to form stack structures including a sacrificial pattern and a passivation pattern, forming spacers over sidewalls of the stack structures, forming a mask pattern covering the second region, removing a portion of the passivation pattern in the first region exposed by the mask pattern to expose a portion of the sacrificial pattern in the first region, removing the exposed portion of the sacrificial pattern in the first region, and etching the etch-target layer to form an etch-target pattern using the spacers in the first and second regions and the stack structure formed between the spacers in the second region. | 05-07-2009 |
Jung-Hee Park, Ichon-Shi KR
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20090159562 | METHOD FOR FABRICATING MAGNETIC TUNNEL JUNCTION DEVICE - A method for fabricating a magnetic tunnel junction device includes forming a first magnetic layer, a dielectric layer, a second magnetic layer and a capping layer, selectively etching the capping layer and the second magnetic layer to form a first pattern, forming a short prevention layer on a sidewall of the first pattern, and etching the dielectric layer and the first magnetic layer using the capping layer and the short prevention layer as an etch barrier to form a second pattern. | 06-25-2009 |
Jung-Woo Park, Ichon-Shi KR
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20110003448 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE HAVING VERTICAL-TYPE CHANNEL - A method for fabricating a semiconductor device includes the following steps. A device isolation layer with a trench type is etched in a predetermined portion of a substrate to define an active region. Predetermined portions where gate lines traverse in the device isolation layer are etched to a certain depth to form a plurality of first recesses. A pair of gate lines filling the first recesses and traversing over the active region is formed. Portions of the active region which storage nodes contact on one sides of the gate lines are etched to form a plurality of second recesses. An ion-implantation process is performed to form a plurality of first junction regions beneath the second recesses and to form a second junction region in a portion of the active region between the gate lines such that the second junction region contacts bit lines. | 01-06-2011 |
20110198688 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE HAVING VERTICAL-TYPE CHANNEL - A semiconductor device includes an active region including a surface region and a first recess formed below the surface region, the active region extending along a first direction; a device isolation structure provided on an edge of the active region; a gate line traversing over the surface region of the active region along a second direction orthogonal to the first direction; a second recess formed in the device isolation structure to receive a given portion of the gate line into the second recess; a first junction region formed in the active region beneath the first recess and on a first side of the gate line; and a second junction region formed on a second side of the gate line and above the first junction region. The first and second junction regions define a vertical-type channel that extends along lateral and vertical directions. | 08-18-2011 |
20130264635 | SEMICONDUCTOR DEVICE HAVING VERTICAL-TYPE CHANNEL - A semiconductor device includes an active region including a surface region and a first recess formed on both sides of the surface region, the active region extending along a first direction; a device isolation structure surrounding the active region; a pair of gate lines extending along the surface region of the active region in a second direction perpendicular to the first direction; a plurality of second recesses formed in the device isolation structure beneath the gate lines and including given portions of the gate lines filled into the second recesses; a plurality of first junction regions formed in the active region beneath the first recesses; and a second junction region formed in the surface region between the gate lines, wherein the second junction region defines at least two vertical-type channels below the gate line with the plurality of first junction regions. | 10-10-2013 |
Kee Teok Park, Ichon-Shi KR
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20110291681 | SEMICONDUCTOR APPARATUS - A semiconductor apparatus includes: a first power line coupled to a first power transfer pad; a second power line coupled to a second power transfer pad; and a test option unit coupled to the first and second power lines and configured to couple the first and second power lines. | 12-01-2011 |
20120105124 | SEMICONDUCTOR APPARATUS, METHOD FOR DELAYING SIGNAL THEREOF, STACKED SEMICONDUCTOR MEMORY APPARATUS, AND METHOD FOR GENERATING SIGNAL THEREOF - The semiconductor apparatus includes a reference delay value check unit configured to receive a source signal and delay the source signal to generate a reference delay signal; a process delay value check unit configured to receive the source signal and delay the source signal to generate a process delay signal; and a signal generation unit configured to receive the reference delay signal and the process delay signal, receive an input signal, and variably delay the input signal based on the reference delay signal and the process delay signal to generate an output signal. | 05-03-2012 |
20130315015 | SEMICONDUCTOR APPARATUS, METHOD FOR DELAYING SIGNAL THEREOF, STACKED SEMICONDUCTOR MEMORY APPARATUS, AND METHOD FOR GENERATING SIGNAL THEREOF - The semiconductor apparatus includes a reference delay value check unit configured to receive a source signal and delay the source signal to generate a reference delay signal; a process delay value check unit configured to receive the source signal and delay the source signal to generate a process delay signal; and a signal generation unit configured to receive the reference delay signal and the process delay signal, receive an input signal, and variably delay the input signal based on the reference delay signal and the process delay signal to generate an output signal. | 11-28-2013 |
Ki-Seon Park, Ichon-Shi KR
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20090134445 | SEMICONDUCTOR DEVICE WITH DIELECTRIC STRUCTURE AND METHOD FOR FABRICATING THE SAME - A semiconductor device with a dielectric structure and a method for fabricating the same are provided. A capacitor in the semiconductor device includes: a bottom electrode formed on a substrate; a first dielectric layer made of titanium dioxide (TiO | 05-28-2009 |
20100240188 | METHOD FOR FABRICATING CAPACITOR - A method for fabricating a capacitor includes: forming a storage node contact plug over a substrate; forming an insulation layer having an opening exposing a surface of the storage node contact plug over the storage contact plug; forming a conductive layer for a storage node over the insulation layer and the exposed surface of the storage node contact plug through two steps performed at different temperatures; performing an isolation process to isolate parts of the conductive layer; and sequentially forming a dielectric layer and a plate electrode over the isolated conductive layer. | 09-23-2010 |
Mun Phil Park, Ichon-Shi KR
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20110271157 | TEST CIRCUIT AND SEMICONDUCTOR MEMORY APPARATUS INCLUDING THE SAME - A test circuit of a semiconductor memory apparatus includes: a first fail detection unit configured to detect a fail of a memory cell group of a first memory block by combining a plurality of first test data signals outputted from the memory cell group of the first memory block; a second fail detection unit configured to detect a fail of a memory cell group of a second memory block by combining a plurality of second test data signals outputted from the memory cell group of the second memory block; a common fail detection unit configured to detect a fail of the memory cell groups of the first and second memory blocks by combining the plurality of first test data signals and the plurality of second test data signals; and a fail determination unit configured to output detection results of the first and second fail detection units or a detection result of the common is fail detection unit according to the detection results of the first and second fail detection units. | 11-03-2011 |
20120106273 | SEMICONDUCTOR MEMORY APPARATUS - Various embodiments of a semiconductor memory apparatus are disclosed. In one exemplary embodiment, the semiconductor memory apparatus may include: a column control signal generator configured to generate a column control signal for a pair of bit lines corresponding to a data mask during a data mask operation; and a bit line sense amplifier configured to sense and amplify a voltage difference between the pair of bit lines and electrically couple the pair of bit lines to a pair of segment input/output lines in response to the column control signal. | 05-03-2012 |
Nak Kyu Park, Ichon-Shi KR
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20110267910 | SEMICONDUCTOR INTEGRATED CIRCUIT INCLUDING COLUMN REDUNDANCY FUSE BLOCK - A semiconductor integrated circuit includes a column redundancy fuse block having a fuse set array having a plurality of fuse sets including a plurality of column address fuses, and a fuse blowing information block configured to output a fuse blowing determination signal of a corresponding column based on a cutting state of the column address fuses, wherein the column redundancy fuse is disposed in the edge area, wherein the fuse blowing determination signal is inputted to a column control block through upper portion of a memory cell array of a corresponding bank. | 11-03-2011 |
Sang-Soo Park, Ichon-Shi KR
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20090061639 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE - A method for fabricating a semiconductor device includes stacking a spin on carbon (SOC) layer and an multifunction hard mask (MFHM) layer on a substrate, forming a photoresist pattern over the MFHM layer, first etching the MFHM layer using a first amount of a fluorine-based gas, second etching the MFHM layer using a second amount of a fluorine-based gas, wherein the second amount is less than the first amount, etching the SOC layer using the MFHM layer as an etch barrier, and etching the substrate using the SOC layer and the MFHM layer as an etch barrier. | 03-05-2009 |
Tae-Su Park, Ichon-Shi KR
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20090146306 | Semiconductor device with epitaxial C49-titanium silicide (TiSi2) layer and method for fabricating the same - The present invention relates to a semiconductor device with an epitaxially grown titanium silicide layer having a phase of C49 and a method for fabricating the same. This titanium silicide layer has a predetermined interfacial energy that does not transform the phase of the titanium layer, and thus, occurrences of agglomeration of the titanium layer and a grooving phenomenon can be prevented. The semiconductor device includes: a silicon layer; an insulation layer formed on the silicon layer, wherein a partial portion of the insulation layer is opened to form a contact hole exposing a partial portion of the silicon layer; an epitaxially grown titanium silicide layer having a phase of C49 and formed on the exposed silicon substrate disposed within the contact hole; and a metal layer formed on an upper surface of the titanium silicide layer. | 06-11-2009 |
Young-June Park, Ichon-Shi KR
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20110198701 | Transistor of Volatile Memory Device with Gate Dielectric Structure Capable of Trapping Charges and Method for Fabricating the Same - The present invention relates to a transistor of a volatile memory device with gate dielectric structure capable of trapping charges and a method for fabricating the same. The transistor in a cell region of a volatile memory device includes a substrate of a first conductive type; a gate dielectric structure capable of trapping charges and formed on the substrate; a gate formed on the gate dielectric structure; a gate insulation layer formed on the gate; a source/drain of a second conductive type formed in a predetermined region of the substrate disposed beneath each lateral side of the gate; and a channel ion implantation region of the first conductive type formed in a predetermined region of the substrate disposed beneath the gate. | 08-18-2011 |