Patent application number | Description | Published |
20100307321 | System and Method for Producing a Harmonious Musical Accompaniment - An apparatus for enhancing audio comprising a first interface and a harmonizing module is disclosed. The first interface receive a first audio segment from a first source. The harmonizing module is coupled to the first interface. The harmonizing module is configured to identify at least one musical property of the first audio segment; calculate a subset of notes that are harmonious with the first audio segment based on the at least one musical property; and select from the subset of notes to generate an audio track to be played substantially synchronously with the first audio segment. A second interface may also be provided to receive a second audio segment from a second source. In this case, the harmonizing module may be configured to generate the audio track by transforming one or more notes of the second audio segment. A method is also provided. | 12-09-2010 |
20100319517 | System and Method for Generating a Musical Compilation Track from Multiple Takes - An apparatus for creating a musical composition comprising an audio interface, and audio converter module, and a multi-track compositor module is disclosed. The audio interface operably receives audio from an audio input device and outputting audio to an audio output device. The audio converter module is operably connected to the audio interface to convert audio received via the audio interface into an audio track having one or more partitions. The multi-track compositor module is configured to receive a first audio track and a second audio track and automatically score each partition of the first and second audio tracks based on one or more criteria. The multi-track compositor module is then configured to construct a third audio track from the partitions of the first and second audio tracks based on the scores for each partition. A method is also provided. | 12-23-2010 |
20100322042 | System and Method for Generating Musical Tracks Within a Continuously Looping Recording Session - An apparatus for creating a musical composition comprising an audio interface, an audio converter and a live looping recording session is disclosed. The audio interface operably receives audio from an input device and outputs audio to an audio output device. The audio converter module is operably connected to the audio interface to convert audio received via the audio interface into an audio track. The recording session module is configured to repeatedly playback a live loop that includes at least a portion of a first audio track, and to add at least a portion of a second audio track to the live loop during repeated playback. The first audio track may be a pre-existing track stored in a data storage medium. The recording session module may be configured to add at least a portion of a third audio track to the live loop during playback, which may be automatically generated based on one or more musical criteria of the first or second tracks. The apparatus may include a user interface coupled to the recording session module to provide a visual representation illustrating the portion of the live loop that is being played. The audio converter module may include a track partitioner to divide at least one of the first and second audio tracks into one or more partitions, a quantizer that aligns audio with a predetermined beat, and a frequency detector to identify the pitch of one or more sounds leading to their storage as a morphology. A method is also provided. | 12-23-2010 |
20130220102 | Method for Generating a Musical Compilation Track from Multiple Takes - An apparatus for creating a musical composition comprising an audio interface, and audio converter module, and a multi-track compositor module is disclosed. The audio interface operably receives audio from an audio input device and outputting audio to an audio output device. The audio converter module is operably connected to the audio interface to convert audio received via the audio interface into an audio track having one or more partitions. The multi-track compositor module is configured to receive a first audio track and a second audio track and automatically score each partition of the first and second audio tracks based on one or more criteria. The multi-track compositor module is then configured to construct a third audio track from the partitions of the first and second audio tracks based on the scores for each partition. A method is also provided. | 08-29-2013 |
Patent application number | Description | Published |
20090144686 | METHOD AND APPARATUS FOR MONITORING MARGINAL LAYOUT DESIGN RULES - A method includes generating a layout for an integrated circuit device in accordance with a plurality of layout design rules. A plurality of metrology sites on the layout associated with at least one subset of the layout design rules is identified. A metrology tag associated with each of the metrology sites is generated. At least one metrology recipe for determining a characteristic of the integrated circuit device is generated based on the metrology tags. Metrology data is collected using the at least one metrology recipe. A selected layout design rule in the at least one subset is modified based on the metrology data. | 06-04-2009 |
20090144692 | METHOD AND APPARATUS FOR MONITORING OPTICAL PROXIMITY CORRECTION PERFORMANCE - A method includes specifying a plurality of optical proximity correction metrology sites on a wafer. Metrology data is collected from at least a subset of the metrology sites. Data values are predicted for the subset of the metrology sites using an optical proximity correction design model. The collected metrology data is compared to the predicted data values to generate an optical proximity correction metric. A problem condition associated with the optical proximity correction design model is identified based on the optical proximity correction metric. | 06-04-2009 |
20100099032 | SYSTEM FOR GENERATING AND OPTIMIZING MASK ASSIST FEATURES BASED ON HYBRID (MODEL AND RULES) METHODOLOGY - An optimal assist feature rules set for an integrated circuit design layout is created using inverse lithography. The full chip layout is lithographically simulated, and printability failure areas are determined. The features are analyzed for feature layout patterns, and inverse lithography is performed on the unique feature layouts to form assist features. The resulting layout of assist features is analyzed to create an assist feature rules set. The rules can then be applied to a photomask patterned with the integrated circuit design layout to print optimal assist features. The resulting photomask may be used to form an integrated circuit on a semiconductor substrate. | 04-22-2010 |
20130198696 | METHODS FOR QUANTITATIVELY EVALUATING THE QUALITY OF DOUBLE PATTERNING TECHNOLOGY-COMPLIANT LAYOUTS - A method for fabricating an integrated circuit is disclosed that includes, in accordance with an embodiment, providing a double patterning technology-compliant logical design for the integrated circuit, the logical design including a plurality of elements; scoring the design of one or more of the plurality of elements to produce a design score; modifying the design based at least in part on the design score; generating a mask set implementing the modified logical design; and employing the mask set to implement the logical design in and on a semiconductor substrate. | 08-01-2013 |
20130212548 | METHODS FOR ANALYZING DESIGN RULES - Methods and apparatus are provided for analyzing impact of design rules on a layout. One exemplary method involves generating variants of the layout for different values for the rule, determining values of a device metric for each of the layout variants, and identifying the relationship between rule and the device metric based on the values for the device metric corresponding to the different values for the rule. In one embodiment, the layout variants are generated by using the different values for the rule to perform layout compaction on an initial layout generated in accordance with an initial value for the rule. | 08-15-2013 |
20130219347 | METHODS FOR DECOMPOSING CIRCUIT DESIGN LAYOUTS AND FOR FABRICATING SEMICONDUCTOR DEVICES USING DECOMPOSED PATTERNS - Methods for fabricating semiconductor devices are provided. In an embodiment, a method of fabricating a semiconductor device includes scanning a circuit design layout and proposing patterns for decomposed layouts. The proposed patterns are then compared with a library of prior patterns including a category of forbidden patterns and a category of preferred patterns. If a selected proposed pattern matches a forbidden pattern, the selected proposed pattern is eliminated. If the selected proposed pattern matches a preferred pattern, then the selected proposed pattern is identified for use in the decomposed layouts. Decomposed layouts are generated from the identified patterns. A plurality of masks is fabricated based on the decomposed layouts. Then a multiple patterning lithographic technique is performed with the plurality of masks on a semiconductor substrate. | 08-22-2013 |
20140215415 | AUTOMATED DESIGN LAYOUT PATTERN CORRECTION BASED ON CONTEXT-AWARE PATTERNS - A process and apparatus are provided for automated pattern-based semiconductor design layout correction. Embodiments include scanning a drawn semiconductor design layout to determine a difficult-to-manufacture pattern within the drawn semiconductor design layout based on a match with a pre-characterized difficult-to-manufacture pattern, determining a corrected pattern based on a pre-determined correlation between the corrected pattern and the pre-characterized difficult-to-manufacture pattern, and replacing the difficult-to-manufacture pattern with the corrected pattern within the drawn semiconductor design layout. | 07-31-2014 |
20140245238 | METHODS INVOLVING PATTERN MATCHING TO IDENTIFY AND RESOLVE POTENTIAL NON-DOUBLE-PATTERNING-COMPLIANT PATTERNS IN DOUBLE PATTERNING APPLICATIONS - One illustrative method disclosed herein involves producing an initial circuit layout, prior to decomposing the initial circuit layout, identifying at least one potential non-double-patterning-compliant (NDPC) pattern in the initial circuit layout, fixing the at least one potential non-double-patterning-compliant (NDPC) pattern so as to produce a double-patterning-compliant (DPT) pattern, producing a modified circuit layout by removing the potential non-double-patterning-compliant (NDPC) pattern and adding the double-patterning-compliant (DPT) pattern to the initial circuit layout, and performing design rule checking and double patterning compliance checking on the modified circuit layout. | 08-28-2014 |
20140282301 | STITCH INSERTION FOR REDUCING COLOR DENSITY DIFFERENCES IN DOUBLE PATTERNING TECHNOLOGY (DPT) - Methodology enabling a reduction in a density difference between two complementary exposure masks and/or windows of a layout and an apparatus for performing the method are disclosed. Embodiments include: determining a layer of an IC design having features to be resolved by first and second masks; determining a difference of density by comparing a first density of a first set of the features with a second density of a second set of the features; determining a region on the layer of a first feature to be resolved by the first mask; and inserting, within the region, a polygon to be resolved by the second mask based on the difference of density. | 09-18-2014 |