Tadahito Fujisawa
Tadahito Fujisawa, Mie JP
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20110043776 | EXPOSURE CONTROL APPARATUS, MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE, AND EXPOSURE APPARATUS - According to one embodiment, an exposure control apparatus includes exposure setting unit that performs an exposure setting of setting an exposure shot as a shot that is exposed or a shot that is not exposed based on height information on a height of a substrate in the exposure shot arranged in a substrate peripheral portion, and an exposure instructing unit that outputs an exposure instruction to the shot that is exposed and an instruction to skip an exposure to the shot that is not exposed. | 02-24-2011 |
20110047518 | PATTERN DETERMINING METHOD - According to the embodiments, a first representative point is set on outline pattern data on a pattern formed in a process before a processed pattern. Then, a minimum distance from the first representative point to a peripheral pattern is calculated. Then, area of a region with no pattern, which is sandwiched by the first representative point and the peripheral pattern, in a region within a predetermined range from the first representative point is calculated. Then, it is determined whether the first representative point becomes a processing failure by using the minimum distance and the area. | 02-24-2011 |
Tadahito Fujisawa, Yokkaichi-Shi JP
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20080235650 | PATTERN CREATION METHOD, MASK MANUFACTURING METHOD AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD - A pattern creation method, including laying out data of a most extreme end pattern of integrated circuit patterns on a first layer and laying out data of the integrated circuit patterns excluding the most extreme end pattern on a second layer, extracting data of a first most proximate pattern being most proximate to the most extreme end pattern from the second layer and converting the extracted data to a third layer, generating data of a contacting pattern which contacts both the first most proximate pattern and the most extreme end pattern in a fourth layer, generating data of a non-overlapping pattern of the contacting pattern excluding overlapping portions with the most extreme end pattern and the first most proximate pattern in a fifth layer, extracting data of a second most proximate pattern being most proximate to the non-overlapping pattern and converting the extracted data to the first layer. | 09-25-2008 |
20100112812 | Photomask quality estimation system and method for use in manufacturing of semiconductor device, and method for manufacturing the semiconductor device - A photomask quality estimation system comprises a measuring unit, a latitude computation unit and an estimation unit. The measuring unit measures the mask characteristic of each of a plurality of chip patterns formed on a mask substrate. The latitude computation unit computes the exposure latitude of each chip pattern based on the mask characteristic. The estimation unit estimates the quality of each chip pattern based on the exposure latitude. | 05-06-2010 |
20100193960 | Semiconductor device, method for making pattern layout, method for making mask pattern, method for making layout, method for manufacturing photo mask, photo mask, and method for manufacturing semiconductor device - A semiconductor device includes a semiconductor substrate, and a circuit pattern group comprising at least N (≧2) circuit pattern on the semiconductor substrate, at least one vicinity of end portion among the at least of N circuit patterns including a connection area to electrically connect to a circuit pattern in another circuit pattern group different from the circuit pattern group, the at least N wirings pattern including a circuit pattern N1 and at least one circuit pattern Ni (i≧2) arranged in one direction different from longitudinal direction of the circuit pattern N1, the at least one circuit patterns Ni having larger i being arranged at further position away from the circuit pattern N1, and in terms of a pattern including the connection area among the at least of Ni circuit patterns, the larger the i, the connection area being arranged at a further position in longitudinal direction. | 08-05-2010 |
Tadahito Fujisawa, Tokyo JP
Patent application number | Description | Published |
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20080220377 | PHOTO MASK, EXPOSURE METHOD USING THE SAME, AND METHOD OF GENERATING DATA - A photo mask formed with patterns to be transferred to a substrate using an exposure apparatus, the photo mask comprising a pattern row having three or more hole patterns surrounded by a shielding portion or a semitransparent film and arranged along one direction, and an assist pattern surrounded by the shielding portion or semitransparent film and having a longitudinal direction and a latitudinal direction, the assist pattern being located at a specified distance from the pattern row in a direction orthogonal to the one direction, the longitudinal direction of the assist pattern being substantially parallel with the one direction, the longitudinal length of the assist pattern being equivalent to or larger than the longitudinal length of the pattern row, the assist pattern being not transferred to the substrate. | 09-11-2008 |
20100112485 | Reticle set, method for designing a reticle set, exposure monitoring method, inspection method for reticle set and manufacturing method for a semiconductor device - A reticle set, includes a first photomask having a circuit pattern provided with first and second openings provided adjacent to each other sandwiching a first opaque portion, and a monitor mark provided adjacent to the circuit pattern; and a second photomask having a trim pattern provided with a second opaque portion covering the first opaque portion in an area occupied by the circuit pattern and an extending portion connected to one end of the first opaque portion and extending outside the area when the second photomask is aligned with a pattern delineated on a substrate by the first photomask. | 05-06-2010 |
Tadahito Fujisawa, Yokkaichi JP
Patent application number | Description | Published |
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20080303115 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF FABRICATING THE SAME - A semiconductor memory device includes a semiconductor substrate having a dummy cell region adjacent to a memory cell region, a plurality of memory cell transistors, a selective gate transistor, a peripheral circuit transistor, a selective gate line, a contact plug, a dummy contact plug formed in an element forming region of the memory cell region adjacent to the selective gate line, and a spacer insulating film formed on a sidewall of the peripheral circuit transistor. The sidewall of the selective gate electrode is formed with no spacer insulating film, and the selective gate line has a sidewall facing an region of the dummy cell region in which the dummy contact plug is formed, except for the sidewall of the selective gate electrode. The sidewall of the selective gate line is formed with a spacer insulating film. | 12-11-2008 |