Patent application number | Description | Published |
20100158345 | Defect And Critical Dimension Analysis Systems And Methods For A Semiconductor Lithographic Process - Apparatus and method evaluate a wafer fabrication process for forming patterns on a wafer based upon design data. Within a recipe database, two or more inspection regions are defined on the wafer for analysis. Patterns within each of the inspection regions are automatically selected based upon tendency for measurement variation resulting from variation in the fabrication process. For each inspection region, at least one image of patterns within the inspection region is captured, a reference pattern, represented by one or both of (a) one or more line segments and (b) one or more curves, is automatically generated from the design data. An inspection unit detects edges within each of the images and registers the image with the reference pattern. One or more measurements are determined from the edges for each of the selected patterns and are processed within a statistical analyzer to form statistical information associated with the fabrication process. | 06-24-2010 |
20100215247 | System And Method For A Semiconductor Lithographic Process Control Using Statistical Information In Defect Identification - A system and method is described for evaluating a wafer fabrication process for forming patterns on a wafer based upon data. Multiple inspection regions are defined on the wafer for analysis. For each inspection region, images of patterns within the inspection region are captured, edges are detected, and lines are registered to lines of a reference pattern automatically generated from the design data. Line widths are determined from the edges. Measured line widths are analyzed to provide statistics and feedback information regarding the fabrication process. In particular embodiments defects are identified as where measured line widths lie outside boundaries determined from the statistics. In particular embodiments, lines of different drawn width and/or orientation are grouped and analyzed separately. Measured line widths may also be grouped for analysis according to geometry such as shape or proximity to other shapes in the inspection region to provide feedback for optical proximity correction rules. | 08-26-2010 |
20110235895 | PATTERN INSPECTION APPARATUS AND METHOD - A pattern inspection apparatus is used for inspecting a fine pattern, such as a semiconductor integrated circuit (LSI), a liquid crystal panel, and a photomask (reticle) for the semiconductor or the liquid crystal panel, which are fabricated based on data for fabricating the fine pattern such as design data. The pattern inspection apparatus includes a reference pattern generation device configured to generate a reference pattern represented by one or more lines, comprising one of a line segment and a curve, from the data, an image generation device configured to generate the image of the pattern to-be-inspected, a detecting device configured to detect an edge of the image of the pattern to-be-inspected, and an inspection device configured to inspect the pattern to-be-inspected by comparing the edge of the image of the pattern to-be-inspected with the one or more lines of the reference pattern. | 09-29-2011 |
20120117520 | Systems And Methods For Inspecting And Controlling Integrated Circuit Fabrication Using A Calibrated Lithography Simulator - A system and method for precise control of fine-line photolithography is disclosed. The system includes a wafer inspector that detects and measures edges and contours of patterns as produced on a wafer and a lithography simulator. The method calibrates the lithography simulator using multiple measurements and/or edges of patterns on the wafer. The calibrated lithography simulator is used to simulate processing to permit optimization of processing conditions by iterative adjustment and re-simulation. In embodiments, the process conditions optimized include one or more of dose, placement of edges on masks, and placement, shape, and locations of SRAF/OPC structures on the masks. In embodiments, the method includes using the calibrated lithography simulator to match results of production process equipment to those achieved with standard equipment. In embodiments, process data from multiple process simulations is stored in a single image file. The method concludes with fabrication of wafers using the optimized conditions and masks. | 05-10-2012 |
20120328181 | PATTERN INSPECTION APPARATUS AND METHOD - A pattern inspection apparatus is used for inspecting a fine pattern, such as a semiconductor integrated circuit (LSI), a liquid crystal panel, and a photomask (reticle) for the semiconductor or the liquid crystal panel, which are fabricated based on data for fabricating the fine pattern such as design data. The pattern inspection apparatus includes a reference pattern generation device configured to generate a reference pattern represented by one or more lines, comprising one of a line segment and a curve, from the data, an image generation device configured to generate the image of the pattern to-be-inspected, a detecting device configured to detect an edge of the image of the pattern to-be-inspected, and an inspection device configured to inspect the pattern to-be-inspected by comparing the edge of the image of the pattern to-be-inspected with the one or more lines of the reference pattern. | 12-27-2012 |
Patent application number | Description | Published |
20090024869 | Autonomous Takeover Destination Changing Method in a Failover - For realizing an optimum failover in NAS, this invention provides a computer system including: a first computer; a second computer; a third computer; and a storage device coupled to the plurality of computers via a network, in which: the first computer executes, upon reception of an access request to the storage device from a client computer coupled to the plurality of computers, the requested access; and transmits to the client computer a response to the access request; the second computer judges whether a failure has occurred in the first computer; obtains load information of the second computer; obtains load information of the third computer from the third computer; and transmits a change request to the third computer when the obtained load information satisfies a predetermined condition; and the third computer judges whether a failure has occurred in the first computer when the change request is received from the second computer. | 01-22-2009 |
20090031154 | POWER SAVING METHOD IN NAS AND COMPUTER SYSTEM USING THE METHOD - Provided is a computer system which includes plurality of computers including a first, second, and third computers, and a storage device coupled to the plurality of computers via a network, in which: the first computer is configured to: access data in a storage area of the storage device; cut, based on settings information and loads on the plurality of computers, at least a part of electric power supplied to the first computer; and send, before cutting the at least a part of electric power supplied to the first computer, a takeover request to the second computer; and the second computer accesses the data within the storage area after receiving the takeover request. With the configuration as described above, power consumption in NAS is reduced. | 01-29-2009 |
20110106939 | COMPUTER SYSTEM AND ITS MANAGEMENT METHOD - Specifically, provided is a computer system, and its management method, including multiple nodes for providing to a host system a storage area to be used for reading and writing data, and respectively acquiring a snapshot at a pre-set time, and which configures a node group from a part or all of the nodes among the multiple nodes and makes data redundant in node units in the node group. With the foregoing computer system and its management method, an access log is acquired from the respective nodes configuring the node group, and the usage of the snapshot in the node group is determined based on the acquired access log of the respective nodes, and the acquisition time of the snapshot is changed in a part or all of the nodes among the nodes configuring the node group based on the determination result. | 05-05-2011 |
Patent application number | Description | Published |
20090075100 | METHOD OF FORMING METALLIC TONE GLITTER PAINT FILMS AND THE PAINTED OBJECTS - A metallic tone glitter paint film is formed by applying sequentially a first base metallic paint, a second base glitter paint in which there is compounded a very small scale-like pigment, or a very small scale-like pigment and an aluminum pigment (C), and a clear paint, and baking and hardening. The first base metallic paint comprises aluminum pigment (A) or which the average particle diameter D | 03-19-2009 |
20090162696 | METHOD OF FORMING METALLIC TONE GLITTER PAINT FILMS AND PAINTED OBJECTS - A metallic tone glitter paint film is formed by applying sequentially a first base metallic paint, a second base glitter paint in which very small scale like pigment or very small scale-like pigment and aluminum pigment is compounded and a clear | 06-25-2009 |
20110003080 | PRIMERS AND A METHOD OF COATING IN WHICH THEY ARE USED - Disclosed is a primer having from 50 to 90 mass % of (A) a chlorinated polyolefin resin having a chlorine content of from 5 to 50 mass % and a weight average molecular weight of from 1,000 to 100,000, from 45 to 5 mass % of (B) a blocked polyisocyanate compound, from 45 to 5 mass % of (C) a polyol resin having a hydroxyl group value of from 30 to 120 mgKOH/g and a weight average molecular weight from 5,000 to 50,000, from 0.5 to 12 mass % of (D) a diol having a weight average molecular weight of from 120 to 1,000 and from 0.01 to 1.5 mass % of (E) a hardening catalyst, wherein the proportions are with respect to the total mass of the resin solid fraction of the (A), (B), and (C) components. | 01-06-2011 |