Bo, US
Cheng Bo, Santa Clara, CA US
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20160097861 | METHOD AND APPARATUS FOR LOCATION DETERMINATION - A method and apparatus, such as implemented by software code on a mobile device, to estimate a location and a traveling distance by leveraging lower-power inertial sensors embedded in the mobile device as a supplement to the device's GPS. To minimize the negative impact of sensor noises, the invention exploits intermittent strong GPS signals and uses linear regression to build a prediction model which is based on a trace estimated from inertial sensors and the one computed from the GPS. Additionally or alternatively, the invention can utilize landmarks (e.g., bridges, traffic lights, etc.) detected automatically and/or special driving patterns (e.g., turning, uphill, and downhill) from inertial sensory data to improve the localization accuracy when the GPS signal is weak. | 04-07-2016 |
Jessica Bo, Canton, MI US
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20160044896 | Claw Trimming Assembly - A claw trimming assembly includes a pair of pliers structured to have a pair of cutting members urged toward each other when the pair of pliers are squeezed. The pair of pliers may trim a claw of an animal. A light emitter is movably coupled to the pair of pliers. The light emitter emits light onto the claw of the animal so the claw may be trimmed without injuring the animal. A sharpener removably coupled to the pair of pliers. The sharpener is structured to engage each of the pair of cutting members of the pliers. The sharpener may sharpen the pair of cutting members. | 02-18-2016 |
Jiang Bo, Amherst, MA US
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20150326466 | INFORMATION PROPAGATION IN A NETWORK - Method for managing information propagation in a network, said information being propagated from a source to a receiving node device through a path of the network comprising at least one edge of the network directly linking a first and a second relaying node devices, wherein the method comprises a step of allocating to the second relaying node device a score each time that the receiving node device receives a useful content from the source through said path, wherein the first relaying node device is able to receive information from the second relaying node device at a given rate, and the method further comprises a stop of periodically updating said rate as a function of a sum of the scores allocated to the second relaying node device | 11-12-2015 |
Li Bo, College Park, MD US
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20110101789 | RF POWER HARVESTING CIRCUIT - Provided is an RF power harvesting circuit with improved sensitivity to RF energy. The RF power harvesting device includes an inductor, a first capacitor connected to the inductor, a first MOSFET connected to a first node, and a second MOSFET connected to the first node. The inductor or the first capacitor are connected to the first node. | 05-05-2011 |
Sun Bo, San Diego, CA US
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20120139592 | Method and Apparatus for Frequency Synthesizing - Systems and methods for frequency synthesis are disclosed. Exemplary embodiments of the digital frequency synthesizer can produce a fixed frequency and/or a modulated signal. An exemplary digital frequency synthesizer includes series-coupled delay cells, a linear feedback shift register, and an accumulator. The series-coupled delay cells generate, from an input clock signal, multiple clock edges corresponding to fractional clock periods. A linear feedback shift register selects clock edges to pass to a combinational logic circuit, based on a sign/enable control signal received from an accumulator and a clock signal received from the combinational logic circuit's output. The accumulator receives a control signal and controls the phase of the synthesizer output based upon the received control signal. | 06-07-2012 |
Xiangzheng Bo, Austin, TX US
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20080261362 | METHOD OF MAKING A SEMICONDUCTOR DEVICE USING A STRESSOR - A method for forming a semiconductor device includes providing a substrate and forming a p-channel device and an n-channel device, each of the p-channel device and the n-channel device comprising a source, a drain, and a gate, the p-channel device having a first sidewall spacer and the n-channel device having a second sidewall spacer. The method further includes forming a liner and forming a tensile stressor layer over the liner and removing a portion of the tensile stressor layer from a region overlying the p-channel device. The method further includes transferring a stress characteristic of an overlying portion of a remaining portion of the tensile stressor layer to a channel of the n-channel device. The method further includes using the remaining portion of the tensile stressor layer as a hard mask, forming a first recess and a second recess adjacent the gate of the p-channel device. | 10-23-2008 |
20080272411 | SEMICONDUCTOR DEVICE WITH MULTIPLE TENSILE STRESSOR LAYERS AND METHOD - A semiconductor device has at least two tensile stressor layers that are cured with UV radiation. A second tensile stressor layer is formed after a first stressor layer. In some examples, the tensile stressor layers include silicon nitride and hydrogen. In some examples, the second tensile stressor layer has a greater shrinkage percentage due to the curing than the first tensile stressor layer. In one form, the second tensile stressor layer after the curing exerts a greater tensile stress than the first tensile stressor layer. The tensile stressors layers are utilized to improve carrier mobility in an N-channel transistor and thus enhance transistor performance. In one form a single group of overlying tensile stressor layers is provided with each layer being increasingly thicker and having increasingly more hydrogen prior to being cured. In other embodiments multiple overlying groups are formed, each group having a similar repeating depth and hydrogen profile. | 11-06-2008 |
20090042351 | METHOD FOR MAKING A TRANSISTOR WITH A STRESSOR - A method for forming a semiconductor device on a semiconductor material layer includes forming a gate structure over the semiconductor material layer. The method further includes forming a first nitride spacer adjacent to the gate structure and forming source/drain extensions in the semiconductor material layer. The method further includes forming an oxide liner overlying the gate structure and the source/drain extensions. The method further includes forming a second nitride spacer adjacent to the oxide liner. The method further includes forming source/drain regions in the semiconductor material layer. The method further includes using an etching process that is selective to the oxide liner, removing the second nitride spacer. The method further includes using an etching process that is selective to the first nitride spacer, at least partially removing the oxide liner. The method further includes forming silicide regions overlying the source/drain regions and the gate structure. | 02-12-2009 |
Xiangzheng Bo, Plano, TX US
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20150076577 | Three Dimensional Three Semiconductor High-Voltage Capacitors - An integrated circuit capacitor. The capacitor includes a substrate, a first conductor, and a first insulating region between the first conductor and the substrate. The capacitor also includes a second conductor, a second insulating region between the first conductor and the second conductor, a third conductor, and a third insulating region between the first conductor and the third conductor. The capacitor also includes a fourth conductor and a fourth insulating region between the first conductor and the fourth conductor. | 03-19-2015 |
Xiang-Zheng Bo, Plano, TX US
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20140187008 | HIGH TILT ANGLE PLUS TWIST DRAIN EXTENSION IMPLANT FOR CHC LIFETIME IMPROVEMENT - An integrated circuit containing an analog MOS transistor may be formed by implanting drain extensions with exactly four sub-implants wherein at least one sub-implant implants dopants in a substrate of the integrated circuit at a source/drain gate edge of the analog MOS transistor at a twist angle having a magnitude of 5 degrees to 40 degrees with respect to the source/drain gate edge of the analog MOS transistor, for each source/drain gate edge of the analog MOS transistor, wherein a zero twist angle sub-implant is perpendicular to the source/drain gate edge. No more than two sub-implants put the dopants in the substrate at any source/drain gate edge of the analog MOS transistor. All four sub-implants are performed at a same tilt angle. No halo implants are performed on the analog MOS transistor. | 07-03-2014 |
20150187760 | DEEP COLLECTOR VERTICAL BIPOLAR TRANSISTOR WITH ENHANCED GAIN - An integrated circuit and method having a deep collector vertical bipolar transistor with a first base tuning diffusion. A MOS transistor has a second base tuning diffusion. The first base tuning diffusion and the second base tuning diffusion are formed using the same implant. | 07-02-2015 |
20160027647 | HIGH TILT ANGLE PLUS TWIST DRAIN EXTENSION IMPLANT FOR CHC LIFETIME IMPROVEMENT - An integrated circuit containing an analog MOS transistor may be formed by implanting drain extensions with exactly four sub-implants wherein at least one sub-implant implants dopants in a substrate of the integrated circuit at a source/drain gate edge of the analog MOS transistor at a twist angle having a magnitude of 5 degrees to 40 degrees with respect to the source/drain gate edge of the analog MOS transistor, for each source/drain gate edge of the analog MOS transistor, wherein a zero twist angle sub-implant is perpendicular to the source/drain gate edge. No more than two sub-implants put the dopants in the substrate at any source/drain gate edge of the analog MOS transistor. All four sub-implants are performed at a same tilt angle. No halo implants are performed on the analog MOS transistor. | 01-28-2016 |
20160079364 | DEEP COLLECTOR VERTICAL BIPOLAR TRANSISTOR WITH ENHANCED GAIN - An integrated circuit and method having a deep collector vertical bipolar transistor with a first base tuning diffusion. A MOS transistor has a second base tuning diffusion. The first base tuning diffusion and the second base tuning diffusion are formed using the same implant. | 03-17-2016 |
Xiang-Zheng Bo, Austin, TX US
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20090146134 | Semiconductive percolating networks - The present invention relates to a semi-conductive composition comprising carbon nanotubes in a matrix. These semiconductive compositions are useful in printing semiconducting portions of thin film transistors. | 06-11-2009 |
20110210401 | MULTILAYER SILICON NITRIDE DEPOSITION FOR A SEMICONDUCTOR DEVICE - A method for making a semiconductor device is provided which comprises (a) providing a semiconductor structure equipped with a gate ( | 09-01-2011 |
Yingjian Bo, Elkins Park, PA US
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20130096335 | PROCESS FOR SYNTHESIS OF SILANE DIPEPTIDE ANALOGS - The invention provides a method of preparing silane dipeptide analogs, comprising the steps of treating a solution of a substituted 1,2-oxasilolane with lithium metal to form a solution of the dilithium salt of a substituted 3-hydroxypropylsilanol, and reacting the solution of the dilithium salt of the substituted 3-hydroxypropylsilanol with a substituted enamine. | 04-18-2013 |
Yu Bo, Chestnut Hill, MA US
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20120217165 | Metal deposition using seed layers - Methods of forming a conductive metal layers on substrates are disclosed which employ a seed layer to enhance bonding, especially to smooth, low-roughness or hydrophobic substrates. In one aspect of the invention, the seed layer can be formed by applying nanoparticles onto a surface of the substrate; and the metallization is achieved by electroplating an electrically conducting metal onto the seed layer, whereby the nanoparticles serve as nucleation sites for metal deposition. In another approach, the seed layer can be formed by a self-assembling linker material, such as a sulfur-containing silane material. | 08-30-2012 |
Yunxin Bo, Thousand Oaks, CA US
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20090143575 | VANILLOID RECEPTOR LIGANDS AND THEIR USE IN TREATMENTS - Therapeutic benzimidazoles and compositions containing them, for the treatment of acute, inflammatory and neuropathic pain, dental pain, general headache, migraine, cluster headache, mixed-vascular and non-vascular syndromes, tension headache, general inflammation, arthritis, rheumatic diseases, osteoarthritis, inflammatory bowel disorders, inflammatory eye disorders, inflammatory or unstable bladder disorders, psoriasis, skin complaints with inflammatory components, chronic inflammatory conditions, inflammatory pain and associated hyperalgesia and allodynia, neuropathic pain and associated hyperalgesia and allodynia, diabetic neuropathy pain, causalgia, sympathetically maintained pain, deafferentation syndromes, asthma, epithelial tissue damage or dysfunction, herpes simplex, disturbances of visceral motility at respiratory, genitourinary, gastrointestinal or vascular regions, wounds, burns, allergic skin reactions, pruritus, vitiligo, general gastrointestinal disorders, gastric ulceration, duodenal ulcers, diarrhea, gastric lesions induced by necrotizing agents, hair growth, vasomotor or allergic rhinitis, bronchial disorders or bladder disorders. | 06-04-2009 |
20120225854 | COMPOUNDS THAT INTERACT WITH GLUCOKINASE REGULATORY PROTEIN FOR THE TREATMENT OF DIABETES - The present invention relates to compounds of Formula I, or pharmaceutically acceptable salts thereof, | 09-06-2012 |
Yunxin Y. Bo, Thousand Oaks, CA US
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20090082358 | Vanilloid receptor ligands and their use in treatments - Bicyclic 3,4-fused piperidine compounds, and compositions containing them, for the treatment of acute, inflammatory and neuropathic pain, dental pain, general headache, migraine, cluster headache, mixed-vascular and non-vascular syndromes, tension headache, general inflammation, arthritis, rheumatic diseases, osteoarthritis, inflammatory bowel disorders, inflammatory eye disorders, inflammatory or unstable bladder disorders, psoriasis, skin complaints with inflammatory components, chronic inflammatory conditions, inflammatory pain and associated hyperalgesia and allodynia, neuropathic pain and associated hyperalgesia and allodynia, diabetic neuropathy pain, causalgia, sympathetically maintained pain, deafferentation syndromes, asthma, epithelial tissue damage or dysfunction, herpes simplex, disturbances of visceral motility at respiratory, genitourinary, gastrointestinal or vascular regions, wounds, burns, allergic skin reactions, pruritus, vitiligo, general gastrointestinal disorders, gastric ulceration, duodenal ulcers, diarrhea, gastric lesions induced by necrotizing agents, hair growth, vasomotor or allergic rhinitis, bronchial disorders or bladder disorders. | 03-26-2009 |
20090264424 | VANILLOID RECEPTOR LIGANDS AND THEIR USE IN TREATMENTS - Compounds having the general structure | 10-22-2009 |
20100261728 | TRP-M8 RECEPTOR LIGANDS AND THEIR USE IN TREATMENTS - Tetrahydroisoquinoline compounds of formula (I), and compositions containing them, for the treatment of acute, inflammatory and neurophatic pain, dental pain, general headache, migraine, cluster headache, mixed-vascular and non-vascular syndromes, tension headache, general inflammation, arthritis, rheumatic diseases, osteoarthritis, inflammatory bowel disorders, inflammatory eye disorders, inflammatory or unstable bladder disorders, psoriasis, skin complaints with inflammatory components, chronic inflammatory conditions, inflammatory pain and associated hyperalgesia and allodynia, neurophatic pain and associated hyperalgesia and allodynia, diabetic neuropathy pain, causalgia, sympathetically maintained pain, deafferentation syndromes, asthma, epithelial tissue damage or dysfunction, herpes simplex, disturbances of visceral motility at respiratory, genitourinary, gastrointestinal or vascular regions, wounds, burns, allergic skin reactions, pruritus, vitiligo, general gastrointestinal disorders, gastric ulceration, duodenal ulcers, diarrhea, gastric lesions induced by necrotising agents, hair growth, vasomotor or allergic rhinitis, bronchial disorders or bladder disorders. | 10-14-2010 |
20100273764 | INHIBITORS OF PI3 KINASE AND/OR MTOR - The present invention relates to compounds of Formula I, or a pharmaceutically acceptable salt thereof; | 10-28-2010 |
20110092504 | INHIBITORS OF PI3 KINASE - The present invention relates to compounds of Formula (I), or a pharmaceutically acceptable salt thereof; methods of treating diseases or conditions, such as cancer, using the compounds; and pharmaceutical compositions containing the compounds, wherein Q, X | 04-21-2011 |
20120071474 | INHIBITORS OF PI3 KINASE - The present invention relates to compounds of Formula I, II or III or a pharmaceutically acceptable salt thereof; | 03-22-2012 |
20130079303 | Inhibitors of PI3 Kinase and/or mTOR - The present invention relates to compounds of Formula I, or a pharmaceutically acceptable salt thereof; | 03-28-2013 |
Zheng Bo US
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20150240351 | High Electric Field Fabrication of Oriented Nanostructures - A method of growing carbon nanostructures on a conductive substrate without the need for a vacuum or low-pressure environment provides high electrical field strengths to generate the necessary carbon ions from a feedstock gas and to promote alignment and separation of the resulting structures. In one embodiment, substantially uniform “vertical” nanostructures may be formed around the periphery of an extended wire for use in corona discharge applications or the like. Growth on a planar substrate may provide use with a variety of apparatus requiring a high specific surface conductor such as capacitors, batteries, and solar cells. | 08-27-2015 |