Patent application number | Description | Published |
20080198743 | DATA FLOW CONTROL FOR SIMULTANEOUS PACKET RECEPTION - Embodiments of the present invention provide methods, a module, and a system for calculating a credit limit for an interface capable of receiving multiple packets simultaneously. Generally, the multiple packets are simultaneously received at an interface on the second device, each packet being one of a plurality of packet types, and a flow control credit limit to be transmitted to the first device is adjusted based on the combination of packet types of the simultaneously received packets. | 08-21-2008 |
20080288780 | LOW-LATENCY DATA DECRYPTION INTERFACE - Methods and apparatus for reducing the impact of latency associated with decrypting encrypted data are provided. Rather than wait until an entire packet of encrypted data is validated (e.g., by checking for data transfer errors), the encrypted data may be pipelined to a decryption engine as it is received, thus allowing decryption to begin prior to validation. In some cases, the decryption engine may be notified of data transfer errors detected during the validation process, in order to prevent reporting false security violations. | 11-20-2008 |
20090144564 | DATA ENCRYPTION INTERFACE FOR REDUCING ENCRYPT LATENCY IMPACT ON STANDARD TRAFFIC - Methods and apparatus that may be utilized in systems to reduce the impact of latency associated with encrypting data on non-encrypted data are provided. Secure and non-secure data may be routed independently. Thus, non-secure data may be forwarded on (e.g., to targeted write buffers), without waiting for previously sent secure data to be encrypted. As a result, non-secure data may be made available for subsequent processing much earlier than in conventional systems utilizing a common data path for both secure and non-secure data. | 06-04-2009 |
20090234974 | PERFORMANCE COUNTERS FOR VIRTUALIZED NETWORK INTERFACES OF COMMUNICATIONS NETWORKS - Performance counters are provided for virtualized network interfaces of communications networks, while minimizing the use of hardware resources. A virtualized network interface includes physical resources, as well as logical resources. Dedicated performance counters are provided for the physical resources of the virtualized network interface, as well as for logical partitions coupled to that interface, while non-dedicated performance counters are provided for the logical resources. This enables the provision of performance counters for virtualized network interfaces, while minimizing hardware resources consumed by those interfaces. | 09-17-2009 |
20130166672 | Physically Remote Shared Computer Memory - A computing system with physically remote shared computer memory, the computing system including: a remote memory management module, a plurality of computing devices, a plurality of remote memory modules that are external to the plurality of computing devices, and a remote memory controller, the remote memory management module configured to partition the physically remote shared computer memory amongst a plurality of computing devices; each computing device including a computer processor and a local memory controller, the local memory controller including: a processor interface, a local memory interface, and a local interconnect interface; each remote memory controller including: a remote memory interface and a remote interconnect interface, wherein the remote memory controller is operatively coupled to the data communications interconnect via the remote interconnect interface such that the remote memory controller is coupled for data communications with the local memory controller over the data communications interconnect. | 06-27-2013 |
20130166849 | Physically Remote Shared Computer Memory - A computing system with physically remote shared computer memory, the computing system including: a remote memory management module, a plurality of computing devices, a plurality of remote memory modules that are external to the plurality of computing devices, and a remote memory controller, the remote memory management module configured to partition the physically remote shared computer memory amongst a plurality of computing devices; each computing device including a computer processor and a local memory controller, the local memory controller including: a processor interface, a local memory interface, and a local interconnect interface; each remote memory controller including: a remote memory interface and a remote interconnect interface, wherein the remote memory controller is operatively coupled to the data communications interconnect via the remote interconnect interface such that the remote memory controller is coupled for data communications with the local memory controller over the data communications interconnect. | 06-27-2013 |
20140047175 | IMPLEMENTING EFFICIENT CACHE TAG LOOKUP IN VERY LARGE CACHE SYSTEMS - A method and circuit for implementing a cache directory and efficient cache tag lookup in very large cache systems, and a design structure on which the subject circuit resides are provided. A tag cache includes a fast partial large (LX) cache directory maintained separately on chip apart from a main LX cache directory (LXDIR) stored off chip in dynamic random access memory (DRAM) with large cache data (LXDATA). The tag cache stores most frequently accessed LXDIR tags. The tag cache contains predefined information enabling access to LXDATA directly on tag cache hit with matching address and data present in the LX cache. Only on tag cache misses the LXDIR is accessed to reach LXDATA. | 02-13-2014 |
Patent application number | Description | Published |
20080295745 | TABLE CONSTRUCTION - A table has two end legs arranged in a parallel, laterally spaced apart relationship for support on a floor surface. Two side rails are arranged in a parallel, laterally spaced apart relationship, and are connected with upper portions of the end legs to retain them in an upright orientation, defining a self-supported table frame without intermediate bracing between the side rails, with a central, vertically extending widow. Top support members are connected with the side rails and protrude outwardly therefrom in a cantilevered fashion. A top member is supported on and connected with the table frame and the top support members, defining a plurality of workstations. A utility module configured to route utilities is positioned within the window of the frame, with opposite sides abuttingly supported on the side rails to removably mount the utility module on the frame and thereby accommodate different utility requirements at the workstations. | 12-04-2008 |
20120266784 | WORKSURFACE ASSEMBLY WITH PERSONAL CARRY ITEM STORAGE SHELF - A worksurface assembly includes a worksurface member having an upper surface, a bottom surface, a forward edge, a rearward edge, and an aperture that opens both upwardly and forwardly from the worksurface member, and a storage member including a pair of sidewalls, a rear wall and a bottom wall that cooperate to form an interior storage area having a height to width ratio of greater than or equal to about 1:1 at at least one position along a length of the storage member, wherein the storage member has a forwardly facing opening and an upwardly facing opening, and wherein the storage member is readily detachably secured to the worksurface member such that the interior storage of the storage member is accessible through the aperture of the worksurface member and such that access to the interior space is uninterrupted between the forwardly facing opening and the upwardly facing opening of the storage member. | 10-25-2012 |
Patent application number | Description | Published |
20080280577 | RECEIVER AND INTEGRATED AM-FM/IQ DEMODULATORS FOR GIGABIT-RATE DATA DETECTION - This disclosure addresses providing gigabit-rate data transmission over wireless radio links, using carrier frequencies in the millimeter-wave range (>30 GHz). More specifically, a circuit for detection of amplitude-shift keyed (ASK) or other amplitude modulations (AM) which can be easily incorporated into an integrated circuit receiver system is described, making the receiver capable of supporting both complex IQ modulation schemes and simpler, non-coherent on-off or multiple-level keying signals. Several novel radio architectures are also described which, with the addition of a frequency discriminator network, have the capability of handling frequency shift keyed (FSK) or other frequency modulations (FM), as well as AM and complex IQ modulation schemes. These radio architectures support this wide variety of modulations by efficiently sharing detector hardware components. The architecture for supporting both quadrature down-conversion and ASK/AM is described first, followed by the ASK/AM detector circuit details, then the AM-FM detector architecture, and finally the most general AM-FM/IQ demodulator system concept and the FSK/FM detector circuit details. | 11-13-2008 |
20130002347 | COUPLING SYSTEM FOR DATA RECEIVERS - A data receiver, a method of operating a data receiver, and an integrated coupling system in a data receiver are disclosed. In one embodiment, the data receiver comprises an input terminal for receiving an input data signal, an input amplifier for amplifying selected components of the input data signal, and an input signal path for transmitting specified high-frequency components and a baseline component of the input data signal from the input terminal to the input amplifier. The data receiver further comprises a feed-forward resistive network connected to the input terminal and to the input amplifier. This feed forward resistive network is used to forward a low-frequency drift compensation signal from the input terminal to the input amplifier, using a passive resistive network, to compensate for low frequency variations in the input data signal, and to develop a desired bias voltage at the input amplifier. | 01-03-2013 |
20130044837 | RECEIVER AND INTEGRATED AM-FM/IQ DEMODULATORS FOR GIGABIT-RATE DATA DETECTION - Provision of gigabit-rate data transmission over wireless radio links, using carrier frequencies in the millimeter-wave range (>30 GHz). More specifically, a circuit for detection of amplitude-shift keyed (ASK) or other amplitude modulations (AM) which can be easily incorporated into an integrated circuit receiver system is described, making the receiver capable of supporting both complex IQ modulation schemes and simpler, non-coherent on-off or multiple-level keying signals. Several novel radio architectures are also described which, with the addition of a frequency discriminator network, have the capability of handling frequency shift keyed (FSK) or other frequency modulations (FM), as well as AM and complex IQ modulation schemes. These radio architectures support this wide variety of modulations by efficiently sharing detector hardware components. Disclosed herein are architecture for supporting both quadrature down-conversion and ASK/AM, ASK/AM detector circuit details, AM-FM detector architecture, and an AM-FM/IQ demodulator system and FSK/FM detector circuit details. | 02-21-2013 |
20130045701 | RECEIVER AND INTEGRATED AM-FM/IQ DEMODULATORS FOR GIGABIT-RATE DATA DETECTION - Provision of gigabit-rate data transmission over wireless radio links, using carrier frequencies in the millimeter-wave range (>30 GHz). More specifically, a circuit for detection of amplitude-shift keyed (ASK) or other amplitude modulations (AM) which can be easily incorporated into an integrated circuit receiver system is described, making the receiver capable of supporting both complex IQ modulation schemes and simpler, non-coherent on-off or multiple-level keying signals. Several novel radio architectures are also described which, with the addition of a frequency discriminator network, have the capability of handling frequency shift keyed (FSK) or other frequency modulations (FM), as well as AM and complex IQ modulation schemes. These radio architectures support this wide variety of modulations by efficiently sharing detector hardware components. Disclosed herein are architecture for supporting both quadrature down-conversion and ASK/AM, ASK/AM detector circuit details, AM-FM detector architecture, and an AM-FM/IQ demodulator system and FSK/FM detector circuit details. | 02-21-2013 |
20130045702 | RECEIVER AND INTEGRATED AM-FM/IQ DEMODULATORS FOR GIGABIT-RATE DATA DETECTION - Provision of gigabit-rate data transmission over wireless radio links, using carrier frequencies in the millimeter-wave range (>30 GHz). More specifically, a circuit for detection of amplitude-shift keyed (ASK) or other amplitude modulations (AM) which can be easily incorporated into an integrated circuit receiver system is described, making the receiver capable of supporting both complex IQ modulation schemes and simpler, non-coherent on-off or multiple-level keying signals. Several novel radio architectures are also described which, with the addition of a frequency discriminator network, have the capability of handling frequency shift keyed (FSK) or other frequency modulations (FM), as well as AM and complex IQ modulation schemes. These radio architectures support this wide variety of modulations by efficiently sharing detector hardware components. Disclosed herein are architecture for supporting both quadrature down-conversion and ASK/AM, ASK/AM detector circuit details, AM-FM detector architecture, and an AM-FM/IQ demodulator system and FSK/FM detector circuit details. | 02-21-2013 |
20130215954 | ANALOG SIGNAL CURRENT INTEGRATORS WITH TUNABLE PEAKING FUNCTION - Analog signal current integrators are provided having tunable peaking functions. Analog signal current integrators with tunable peaking functions enable data rate dependent loss compensation for applications in high data rate receiver integrated circuits incorporating advanced equalization functions, such as decision-feedback equalizers. For instance, a current integrator circuit includes a current integrating amplifier circuit comprising an adjustable circuit element to tune a peaking response of the current integrator circuit, and a peaking control circuit to generate a control signal to adjust a value of the adjustable circuit element as a function of an operating condition of the current integrator circuit. The operating condition may be a specified data rate or a communication channel characteristic or both. The adjustable circuit element may be a degeneration capacitor or a bias current source. | 08-22-2013 |
20140133604 | COUPLING SYSTEM FOR DATA RECEIVERS - A data receiver, a method of operating a data receiver, and an integrated coupling system in a data receiver are disclosed. In one embodiment, the data receiver comprises an input terminal for receiving an input data signal, an input amplifier for amplifying selected components of the input data signal, and an input signal path for transmitting specified high-frequency components and a baseline component of the input data signal from the input terminal to the input amplifier. The data receiver further comprises a feed-forward resistive network connected to the input terminal and to the input amplifier. This feed forward resistive network is used to forward a low-frequency drift compensation signal from the input terminal to the input amplifier, using a passive resistive network, to compensate for low frequency variations in the input data signal, and to develop a desired bias voltage at the input amplifier. | 05-15-2014 |
Patent application number | Description | Published |
20080225990 | APPARATUS AND METHOD FOR SIGNAL PHASE CONTROL IN AN INTEGRATED RADIO CIRCUIT - An apparatus and method to control signal phase in a radio device includes a phase rotator configured to control a phase of a local oscillator. A phase error determination module is configured to determine phase error information based on received in-phase (I) and quadrature (Q) (IQ) signal values. A phase correction module is configured to derive from the received IQ signal values a correction signal and apply the correction signal to the phase rotator in a path of the local oscillator. | 09-18-2008 |
20090207900 | Apparatus for Stabilizing Convergence of an Adaptive Line Equalizer - Illustrative embodiments provide a computer implemented method and an apparatus for data decorrelation in a line equalizer adaptive system. The apparatus comprises an input and an output, forming a data path there between, wherein the input capable of receiving data to create received data and the output capable of sending data. The apparatus further comprises an adaptive equalizer capable of equalizing the received data, connected to the data path, and a synchronous decorrelator connected to the data path, in communication with the adaptive equalizer, wherein the synchronous decorrelator evaluates an adapt enable output for each received data input to the adaptive equalizer to determine whether the adaptive equalizer can update settings of the line equalizer adaptive system. | 08-20-2009 |
20100046683 | ADAPTIVE CLOCK AND EQUALIZATION CONTROL SYSTEMS AND METHODS FOR DATA RECEIVERS IN COMMUNICATIONS SYSTEMS - Systems and methods for adaptive clock and equalization control are provided for data receivers, which are based on a “closed loop” sampling clock framework that employs controllable and dynamically adapted time offsets on both local data and amplitude clocks. The controllable clock offsets are dynamically adapted using signal processing methods adapted to achieve optimum sampling of data and amplitude sampling clock signals to accurately detect data bits and optimize system equalization settings, including, decision-feedback equalizer and/or an optional linear equalizer preceding a decision-feedback equalizer. | 02-25-2010 |
20100102895 | QUADRATURE MODULATION CIRCUITS AND SYSTEMS SUPPORTING MULTIPLE MODULATION MODES AT GIGABIT DATA RATES - Quadrature modulation systems, circuits and methods are provided to support various modulation modes including ASK (amplitude shift key), FSK (frequency shift key) and PSK (phase shift key) modulation at high data rates (e.g., gigabit data rates). For example, a modulation circuit includes a mixer circuit including an integrated sign modulation control circuit and a plurality of mixer ports. The mixer ports include a first input port, a second input port, an output port and a sign modulation control port. The modulation circuit generates a modulated signal by operation of the mixer circuit multiplying a modulating signal applied to the first input port with a carrier signal applied to the second input port to generate a mixed signal output from the output port, and by operation of the integrated sign modulation control circuit controlling polarity switching of a signal at one of the mixer ports in response to a sign modulation control signal input to the sign modulation control port. The sign modulation control signal can be a digital data signal having binary data encoded into the modulated signal. | 04-29-2010 |