Patent application number | Description | Published |
20080220206 | Semiconductor die for increasing yield and usable wafer area - According to one embodiment, a semiconductor die for increasing usable area of a wafer and for increasing yield has a substantially hexagonal shape. The wafer can have, for example, a circular shape. The semiconductor die can be diced by, for example, using a water-jet-guided laser. In one embodiment, the semiconductor die results in an approximately 2.0% to 4.0% reduction in the unusable area of the wafer. Moreover, the substantially hexagonal shape of the semiconductor die reduces stress at corners of the semiconductor die, thus increasing the yield of the wafer. | 09-11-2008 |
20080220220 | Semiconductor die having increased usable area - According to one embodiment, a semiconductor die having increased usable area has at least six sides. The semiconductor die has a reduced stress at each corner of the die, resulting in smaller keep out zones near the corners of the semiconductor die, which allow the placement of bond pads near each corner of the die. The semiconductor die further allows the placement of active circuitry near each corner of the semiconductor die. One embodiment results in a 5.0% increase in usable area on the semiconductor die. | 09-11-2008 |
20090057858 | Low cost lead frame package and method for forming same - According to one exemplary embodiment, a lead frame package includes a number of leads and a number of contacts, where each of the contacts is situated over one of the leads. The lead frame package further includes a semiconductor die including a number of bond pads. Each of the contacts is directly attached and bonded to one of the bond pads on the semiconductor die. Each of the contacts is situated over a top portion of one of the leads, where the top portion has a shorter length than a middle portion of each of the leads. Each of the contacts is connected to one of the bond pads on the semiconductor die without a wire bond. The semiconductor die does not include a redistribution layer situated over an active surface of the semiconductor die. | 03-05-2009 |
20090263969 | HIDDEN PLATING TRACES - A strengthened semiconductor die substrate and package are disclosed. The substrate may include contact fingers formed with nonlinear edges. Providing a nonlinear contour to the contact finger edges reduces the mechanical stress exerted on the semiconductor die which would otherwise occur with straight edges to the contact fingers. The substrate may additionally or alternatively include plating traces extending at an angle from the contact fingers. Extending at an angle, at least the ends of the plating traces at the edge of the substrate are covered beneath a lid in which the semiconductor package is encased. Thus, when in use with a host device, contact between the ends of the plating traces beneath the lid and contact pins of the host device is avoided. | 10-22-2009 |
20100252315 | Printed Circuit Board With Coextensive Electrical Connectors And Contact Pad Areas - A printed circuit board is disclosed having coextensive electrical connectors and contact pad areas. Areas of the contact pads where the traces and/or vias are located may be etched away to ensure electrical isolation between the traces, vias and contact pads. | 10-07-2010 |
20120164828 | HIDDEN PLATING TRACES - A strengthened semiconductor die substrate and package are disclosed. The substrate may include contact fingers formed with nonlinear edges. Providing a nonlinear contour to the contact finger edges reduces the mechanical stress exerted on the semiconductor die which would otherwise occur with straight edges to the contact fingers. The substrate may additionally or alternatively include plating traces extending at an angle from the contact fingers. Extending at an angle, at least the ends of the plating traces at the edge of the substrate are covered beneath a lid in which the semiconductor package is encased. Thus, when in use with a host device, contact between the ends of the plating traces beneath the lid and contact pins of the host device is avoided. | 06-28-2012 |
20120273968 | Printed Circuit Board With Coextensive Electrical Connectors And Contact Pad Areas - A printed circuit board is disclosed having coextensive electrical connectors and contact pad areas. Areas of the contact pads where the traces and/or vias are located may be etched away to ensure electrical isolation between the traces, vias and contact pads. | 11-01-2012 |
20130299959 | RIGID WAVE PATTERN DESIGN ON CHIP CARRIER SUBSTRATE AND PRINTED CIRCUIT BOARD FOR SEMICONDUCTOR AND ELECTRONIC SUB-SYSTEM PACKAGING - A rigid wave pattern formed on a first side of a substrate in a semiconductor die package. The rigid wave pattern aligns with and overlies the contact fingers formed on the second side of the substrate. The rigid wave pattern includes a first pattern with an etched portion and an unetched portion around the etched portion. When the substrate and dice are encased during the molding process, the rigid wave pattern effectively reduces deformation of and stresses on the dice, therefore substantially alleviating die cracking. | 11-14-2013 |
20150054177 | RIGID WAVE PATTERN DESIGN ON CHIP CARRIER SUBSTRATE AND PRINTED CIRCUIT BOARD FOR SEMICONDUCTOR AND ELECTRONIC SUB-SYSTEM PACKAGING - A rigid wave pattern formed on a first side of a substrate in a semiconductor die package. The rigid wave pattern aligns with and overlies the contact fingers formed on the second side of the substrate. The rigid wave pattern includes a first pattern with an etched portion and an unetched portion around the etched portion. When the substrate and dice are encased during the molding process, the rigid wave pattern effectively reduces deformation of and stresses on the dice, therefore substantially alleviating die cracking. | 02-26-2015 |
Patent application number | Description | Published |
20090102030 | INTEGRATED CIRCUIT PACKAGE WITH ETCHED LEADFRAME FOR PACKAGE-ON-PACKAGE INTERCONNECTS - Methods, systems, and apparatuses for integrated circuit packages, and for package stacking, are provided. An electrically conductive frame is attached to a first surface of a substrate. The electrically conductive frame includes a perimeter ring portion, a plurality of leads, and a plurality of interconnect members positioned within a periphery formed by the perimeter ring portion. Each interconnect member is coupled to the perimeter ring portion by a respective lead. A first end of each interconnect member is coupled to the first surface of the substrate. An encapsulating material is applied to the first surface of the substrate, without covering a second end of each interconnect member with the encapsulating material. The perimeter ring portion is removed from the electrically conductive frame to isolate the plurality of interconnect members. A first integrated circuit package is formed in this manner. A second integrated circuit package may be mounted to the first package. Signals of the first package may be electrically coupled with the second package at the exposed second ends of the interconnect members. Side surfaces of the interconnect members may be exposed at sides of the first package. | 04-23-2009 |
20090108473 | DIE-ATTACH MATERIAL OVERFLOW CONTROL FOR DIE PROTECTION IN INTEGRATED CIRCUIT PACKAGES - Methods, systems, and apparatuses for integrated circuit packages are provided. An integrated circuit package includes a metal layer, an integrated circuit die, and an adhesive material. The metal layer has a first surface that has a die-attach region. The metal layer further has one or more recessed regions formed in the first surface of the metal layer adjacent to the die-attach region. The adhesive material attaches a first surface of the die to the die-attach region and at least partially fills the recessed region(s). Excess adhesive material flows into the recessed region(s) during application of the die to the die-attach region, so that the side surfaces of the die remain substantially uncovered by the adhesive material. By preventing the excess adhesive material from covering the side surfaces of the die, the adhesive material is prevented from penetrating the side surfaces of the die, which could damage the die. | 04-30-2009 |
20090194872 | DEPOPULATING INTEGRATED CIRCUIT PACKAGE BALL LOCATIONS TO ENABLE IMPROVED EDGE CLEARANCE IN SHIPPING TRAY - Methods, systems, and apparatuses for integrated circuit packages, transport containers, and for transporting integrated circuit packages are provided. A transport container for an integrated circuit package includes a body and a plurality of mounting features. The body has a surface that includes a package receiving region. The plurality of mounting features is positioned in the package receiving region. A first mounting feature is positioned on a first inner surface of the package receiving region and a second mounting feature is positioned on a second inner surface of the package receiving region. The package receiving region is configured to receive an integrated circuit package such that the received package is supported by the plurality of mounting features. The first and second mounting features coincide with respective spaces in first and second edges of an array of solder balls on a surface of the package. | 08-06-2009 |
20100019360 | INTEGRATED CIRCUIT PACKAGE WITH ETCHED LEADFRAME FOR PACKAGE-ON-PACKAGE INTERCONNECTS - Methods, systems, and apparatuses for integrated circuit packages, and for package stacking, are provided. An electrically conductive frame is attached to a first surface of a substrate. The electrically conductive frame includes a perimeter ring portion, a plurality of leads, and a plurality of interconnect members positioned within a periphery formed by the perimeter ring portion. Each interconnect member is coupled to the perimeter ring portion by a respective lead. A first end of each interconnect member is coupled to the first surface of the substrate. An encapsulating material is applied to the first surface of the substrate, without covering a second end of each interconnect member with the encapsulating material. The perimeter ring portion is removed from the electrically conductive frame to isolate the plurality of interconnect members. A first integrated circuit package is formed in this manner. A second integrated circuit package may be mounted to the first package. Signals of the first package may be electrically coupled with the second package at the exposed second ends of the interconnect members. Side surfaces of the interconnect members may be exposed at sides of the first package. | 01-28-2010 |