Chen, Sinshih Township
Chia-Liang Chen, Sinshih Township TW
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20090142529 | Volatile liquid loadable porous metal or ceramic container and manufacturing method - A volatile liquid loadable porous metal or ceramic container and manufacturing method thereof provided with a structural body formed by metal or ceramic sintering and provided with breathable pores, which extend from an outer surface of the structural body to the interior of the structural body, and the breathable pores form spaces to transport or/and store liquid. The manufacturing method includes: a. taking a low temperature volatile material as the core; b. completely covering the aforementioned core with metal or ceramic powder in the predetermined mold; c. controlling compactness of the metal or ceramic powder; d. sintering of the core at a temperature higher than the vaporization temperature to cause gaseous effusion of the core; e. taking off the predetermined mold after completing sintering. | 06-04-2009 |
Chia-Lung Chen, Sinshih Township TW
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20120212207 | Bandgap Circuit and Complementary Start-Up Circuit for Bandgap Circuit - A bandgap circuit includes a bias current generating circuit and a complementary start-up circuit. The bias current generating circuit includes a first node and a second node and is arranged to generate a bias current in response to a voltage provided at the first node or a voltage provided at the second node. The complementary start-up circuit is arranged to start-up the bias current generating circuit and includes a first start-up circuit coupled to the first node and a second start-up circuit coupled to the second node. The first and second start-up circuits operate complementarily, so that the second start-up circuit provides the voltage to the second node when the first start-up circuit is unable to provide the voltage to the first node, and the first start-up circuit provides the voltage to the first node when the second start-up circuit is unable to provide the voltage to the second node. | 08-23-2012 |
Chien-Chun Chen, Sinshih Township TW
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20090051844 | Defect repairing method of liquid crystal display and signal transmission method of source driver and timing controller thereof - A liquid crystal display (LCD) includes a controller, a source driver, first and second data lines and a data transmission path. The controller outputs first and second image data, and the source driver receives and outputs the first and second image data. The source driver includes first and second data channel circuits and a first repair channel circuit. The first and second data channel circuits respectively output first and second sub-pixel data. The first repair channel circuit is coupled to the controller to receive first repairing data. The first and second data lines are respectively coupled to the first and second data channel circuits to receive the first and second sub-pixel data. The data transmission path includes a redundant line, which is for coupling the first repair channel circuit to one of the first and second data lines, and interlaces with the first and second data lines. | 02-26-2009 |
Chien-Ru Chen, Sinshih Township TW
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20090066675 | DISPLAY DRIVER AND DIGITAL TO ANALOG CONVERTER THEREOF - The present invention provides a programmable digital to analog converter comprises a reference voltage generator for generating a plurality of reference voltages based on a plurality of reference signals respectively, the gamma reference voltage generator comprising: a resistor string comprising a plurality of resistors in serial for providing a plurality of voltages; and a plurality of reference decoders, each receiving said voltages from said resistor string and selectively outputting a reference voltage from said voltages based on the corresponding reference signal, and a data decoder receiving the reference voltages for selectively outputting an analog voltage based on a data signal. | 03-12-2009 |
20090146856 | DIGITAL-TO-ANALOG CONVERTER WITH R-2R LADDER NETWORK BY POLARITY CONTROL - The present invention provides the voltage generator comprises providing a binary weight digital-to-analog converter (DAC) including an R-2R ladder network, and control switches, and an operation amplifier (OP) with a feedback resistance, and providing a plurality of voltages, from an input of said ladder network, in a positive polarity and a negative polarity, wherein said positive polarity and negative polarity are determined by a reference voltage, and each of said switches is switched between a connection to said OP and said reference voltage. | 06-11-2009 |
20100283768 | Output Buffer Adapted to a Source Driver and Source Driver - An output buffer adapted to a source driver and a source driver are provided. The output buffer comprises an input and an output stage. The input stage comprises an input node, a first and a second output terminal. The output stage comprises a PMOS, a NMOS, a first and a second switches. The first and the second switch are connected between the gate of the PMOS, the first output terminal and the gate of the PMOS, the voltage supply respectively to both receive a latch signal. When the latch signal is in a first state, the first and the second switches disable the output stage. When the latch signal is in a second state, the first and the second switches enable the output stage to transfer an analog data from a DAC of the source driver to the output node connected to the drain of the PMOS and NMOS. | 11-11-2010 |
20100315388 | SOURCE DRIVER AND SERIAL-TO-PARALLEL DATA CONVERTING METHOD ADAPTED IN THE SOURCE DRIVER - A source driver receiving data from an external bus is provided. The source driver comprises: a plurality of internal buses; a serial-to-parallel unit, a shift register and a plurality of channels. The serial-to-parallel unit is for receiving the data from the external bus and converting the data into plural display data for transmitting respectively on the internal buses in parallel; the shift register is for outputting shift control signals; and the plurality of channels are for latching data from the internal buses according to the shift control signals; wherein each shift control signal controls at least two channels that correspond respectively to the internal buses. | 12-16-2010 |
Jeh-Chuen Chen, Sinshih Township TW
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20090244799 | LATCH-UP PROTECTION CIRCUIT FOR LCD DRIVER IC - A latch-up protection circuit for LCD driver is provided. The latch-up protection circuit for LCD driver comprises an NMOS, a switch and a capacitor. The NMOS comprises a drain electrically connected to a ground; a source electrically connected to a negative voltage source; and a gate. The switch is electrically connected to the gate to receive a control signal, wherein the switch switches between a positive voltage source and the negative voltage source according to the control signal; and the capacitor is electrically connected to the positive voltage source and the gate. | 10-01-2009 |
Jung-Zone Chen, Sinshih Township TW
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20100052964 | Digital to Analog Converter and Display Driving System Thereof - A digital to analog converter of the source driver includes a gamma voltage generator and a data decoder. The gamma voltage generator receives a gamma code to generate an analog gamma voltage. The gamma voltage includes a register, a reference decoder, and a calibrator. The register stores the gamma code. The reference decoder converts the gamma code from the register into the analog gamma voltage. The calibrator, receiving a reference gamma voltage in a calibration mode, includes a comparator and a counter, in which the counter tunes the gamma code according to the control signal generated by the comparator comparing the analog gamma voltage and the reference gamma voltage. The data decoder receives digital pixel data and selects one gamma voltage as a driving voltage based on the digital pixel data. | 03-04-2010 |
Kai-Ji Chen, Sinshih Township TW
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20090153126 | CURRENT MIRROR CIRCUIT - The present invention discloses a current mirror circuit generating an output current flowing through an output current path according to an input current flowing through an input current path. The current mirror circuit comprises a P type transistor in the output current path, an operational amplifier, and a basic circuit. The operational amplifier has a negative input coupled to a node receiving the input current, a positive input coupled to a drain of the P type transistor, and an output coupled to a gate of the P type transistor. The basic circuit comprises a first transistor in the input current path and a second transistor in the output current path. The first transistor has a gate and a drain coupled together. The second transistor has a gate coupled to the gate of the first transistor. | 06-18-2009 |
20090200959 | Light-Emitting Diode Driving Circuit - A light-emitting diode driving circuit includes a control circuit, a transistor switch and a compensating circuit. The control circuit receives an oscillating signal to generate a pulse drive signal. The transistor switch is activated by the pulse drive signal such that an inductor is charged by an input voltage, in which the inductor is arranged to deliver an inducting current to at least one light-emitting diode when the transistor switch is deactivated. The compensating circuit is coupled between the control circuit and a capacitor provided for reducing ripples of an output voltage corresponding to the inducting current. The compensating circuit performs a charging and discharging operation along with the capacitor when controlled by a dimming control signal provided to control brightness of the light-emitting diode. | 08-13-2009 |
Lung-Sheng Chen, Sinshih Township TW
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20120026000 | Hook-on Chair with Clamping Display Mechanism - In the specification and drawing, a hook-on chair is described and shown with a clamping mechanism and a display mechanism, wherein the display mechanism is positioned to reflect a clamping or loosing situation of the clamping mechanism. | 02-02-2012 |
Pen-Hsin Chen, Sinshih Township TW
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20110157103 | Display Device and Driving Circuit - A display device is provided, including a panel, source driver chips, a gate driver chip, a printed circuit board and transmission lines. The panel includes light emitting elements and display cells. The display cells are respectively connected to data lines and gate lines. The source driver chips output pixel signals to the data lines. At least one source driver chip includes a timing controller integrated therein for generating timing control signals and the pixel signals according to an image control signal provided by a host. The gate driver chip outputs corresponding scan signals to the gate lines. The transmission lines are routed on the printed circuit board and connect to the source driver chips. | 06-30-2011 |
20130002621 | DISPLAY DEVICE AND DRIVING CIRCUIT - A display device is provided, including a panel having a plurality of display cells, wherein the display cells are respectively connected to a plurality of data lines and gate lines. A plurality of source driver chips output a plurality of pixel signals to the data lines, wherein each source driver chip comprises a timing controller integrated therein for receiving an image control signal provided by a host and generating a plurality of timing control signals and the pixel signals according to-the image control signal. A gate driver chip outputs corresponding scan signals to the gate lines. A printed circuit board is also provided, and a plurality of transmission lines are routed on the printed circuit board and connected the source driver chips. | 01-03-2013 |
Ping-Po Chen, Sinshih Township TW
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20080238851 | DISPLAY AND SOURCE DRIVER THEREOF - A pixel circuit has a light emitting diode, a first driving transistor, a second driving transistor, a capacitor, and a switch unit. When a scan signal is asserted, the switch unit couples sources/drains of the second driving transistor respectively to a first and a second source/drain of the first driving transistor, and couples a gate and second source/drain of the first driving transistor together. When the scan signal is de-asserted, the switch unit decouples one of the sources/drains of the second driving transistor from the first/second source/drain of the first driving transistor, and decouples the gate from the second source/drain of the first driving transistor. | 10-02-2008 |
20100182295 | LCD DRIVING CIRCUIT AND DRIVING METHOD THEREOF - A LCD driving circuit is provided herein. The LCD driving circuit includes a data processor for processing a plurality of data signals to generate a plurality of processed data signals to respectively drive a line of subpixels arranged on a LCD panel, a driving control module having a data sequence unit for receiving and arranging the processed data signal, and a switching control unit to generate a control signal and a plurality of driving signals corresponding with the control signal to drive a plurality of transistors, a source line driving circuit having a plurality of latching units to respectively store the processed data signal. | 07-22-2010 |
Schief Chen, Sinshih Township TW
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20110110801 | FLUID PUMP FOR DELIVERING COOLED WORKING FLUID IN AN ENGINE COOLING SYSTEM - A fluid pump for delivering cooled working fluid in an engine cooling system includes a housing unit defining front and rear chambers, an inlet disposed upstream of a central region of the front chamber, an outlet disposed downstream of a surrounding region of the front chamber, a canister member dividing the rear chamber into stator- and rotor-side spaces for receiving a stator and a rotor, respectively, a hollow shaft which is rotated with the rotor to turn an impeller in the central region and which defines a passage, and an auxiliary conduit communicated with the inlet and the rear chamber so as to divert part of the working fluid to flow through the internal duct and the passage, thereby diffusing heat generated within the housing unit. | 05-12-2011 |
Shing-Chia Chen, Sinshih Township TW
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20090060360 | Method and apparatus for processing image and electronic device using the same - A method and apparatus for processing an image, and an electronic device are provided. The method comprises: picking a maximum gray level from the gray levels in the sub-pixels of each image pixel in the image to obtain a luminance map which is consisted of the maximum gray levels of the image pixels; determining an image-content lightness of the image according to the luminance map; and adjusting the gray levels in the sub-pixels of the image pixels in the image according to the image-content lightness of the image. | 03-05-2009 |
20090066715 | METHOD AND APPARATUS FOR PROCESSING DIGITAL IMAGE TO BE DISPLAYED ON DISPLAY DEVICE WITH BACKLIGHT MODULE - A method and apparatus for processing a digital image to be displayed on a display panel illuminated with a backlight module. The backlight module is set to a specific backlight duty according to a luminance statistic of the digital image. The digital image is remapped through a tone mapping function formed according to the specific backlight duty and the luminance statistic. | 03-12-2009 |
20090067713 | CONTENT-ADAPTIVE CONTRAST IMPROVING METHOD AND APPARATUS FOR DIGITAL IMAGE - The present invention is directed to a digital image content-adaptive contrast improving method. The method includes forming a piecewise linear tone remapping function for a digital image according to the histogram thereof. The piecewise linear tone remapping function is formed by repeatedly performing a first and a second step. The first step determines a starting linear tone mapping function for a specific range of luminance values. The second step generates a new tone mapping function for the specific range of luminance values based on the starting linear tone mapping function and the histogram. An apparatus for implementing the method is also provided. | 03-12-2009 |
20090097777 | DIGITAL IMAGE TONE REMAPPING METHOD AND APPARATUS - A digital image tone remapping method is disclosed. The method includes computing an average luminance value of a digital image; generating a preliminary tone mapping function according to the average luminance value; generating a luminance statistic of the digital image; determining new remapped values for a plurality of skeleton luminance values according to the preliminary tone mapping function and the luminance statistic; generating a final tone mapping function according to the new remapped values and the plurality of skeleton luminance values; and remapping the digital image through the final tone mapping function. The present invention also discloses an apparatus performing the method. | 04-16-2009 |
20090303390 | Method for separating luminance and chrominance of composite TV analog signal - A method for separating luminance and chrominance of a composite TV analog signal includes the steps of: measuring first differences between horizontal neighbor pixels, second differences between vertical neighbor pixels and third differences between temporal neighbor pixels encoded in the composite TV analog signal; comparing the first, second and third differences with one another to obtain a minimum difference used as a factor of a weighting function; and filtering the composite TV analog signal simultaneously by a two-dimensional (2D) comb filter and a three-dimensional (3D) comb filter according to the weighting function on the basis of the minimum difference to obtain a luminance signal and a chrominance signal, in which magnitudes of a part of the composite TV analog signal filtered by the 2D comb filter and magnitudes of the other part of the composite TV analog signal filtered by the 3D comb filter are determined by the weighting function. | 12-10-2009 |
Tung-Yang Chen, Sinshih Township TW
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20120159413 | IMPEDANCE DESIGN METHOD - The invention discloses a chipset having N input/output (I/O) ports coupled to a voltage source which have an observation I/O port. The method includes calculating a first set of impedances at a predetermined frequency or the observation I/O port, if the voltage source is internally coupled to the N I/O ports within the chipset, and calculating a second set of impedances at the predetermined frequency for the observation I/O port, if the voltage source is externally coupled to the N I/O ports through a carrier coupling the core chip to the voltage source. The first set of impedances are compared to the second set of impedances, and the impedance of the power network or the impedance of the carrier is adjusted according to the comparison result. | 06-21-2012 |
20120236445 | On-Chip Noise Filter Circuit - A noise filter circuit for an IC is provided. The noise filter circuit comprises a decoupling unit coupled to a power pad of the IC and a current amplifier circuit coupled to the decoupling unit and the power pad of the IC. The decoupling unit generates a first current in response to a transient voltage being on the power pad of the IC. The current amplifier circuit drains a second current from the power pad of the IC according to the first current. | 09-20-2012 |
Tyng-Yang Chen, Sinshih Township TW
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20100072973 | Voltage Converter - A voltage converter to convert a high voltage to a low voltage is provided. The voltage converter comprises: a current mirror, a current bias, a plurality of loads and a low voltage output. The current mirror comprises a first PMOS and a second PMOS, wherein the source of the first PMOS and the second PMOS receive a high voltage input which is a supply voltage of the current mirror, and the gate of the first PMOS is connected to the drain of the first PMOS. The current bias is connected between the drain of the first PMOS and a ground potential. The plurality of loads are parallel connected between the drain of the second PMOS and the ground potential. And the low voltage output connected to the drain of the second PMOS. | 03-25-2010 |
20100156320 | LED CIRCUIT WITH HIGH DIMMING FREQUENCY - A LED circuit comprises: an inductor, a group of LEDs, a capacitor, a power MOS and a switching circuit. The inductor is connected to a voltage supply and a first node; the group of LEDs is connected to the first node and a ground potential; the capacitor is connected to the first node and a ground potential; the power MOS is connected to the first node and a ground potential, wherein the gate of the power MOS receives a switching signal such that the capacitor is charged when the power MOS is turn on to further turn on the LEDs and the capacitor is discharged when the power MOS is turn off to turn off the LEDs. The switching circuit is to generate the switching signal. | 06-24-2010 |