Patent application number | Description | Published |
20090040821 | LOW POWER MULTIPLE BIT SENSE AMPLIFIER - A sense amplifier for multiple level flash memory cells is comprised of a voltage ramp generator that generates a ramp voltage signal. Reference sense amplifiers compare an input reference current to a ramp current generated from the ramp voltage signal. When the ramp voltage signal is greater than the reference current, an output latch signal is toggled. A sense amplifier compares an input bit line current to a threshold and outputs a logical low when the bit line current goes over the threshold. The sense amplifier output is latched into one of three digital latches at a time determined by the latch signals. An encoder encodes the data from the three digital latches into two bits of output data. | 02-12-2009 |
20100157685 | PROGRAMMING IN A MEMORY DEVICE - Methods for programming a memory device, memory devices, and a memory systems are provided. According to at least one such method, a selected memory cell is programmed by a series of programming pulses. The series of programming pulses are configured in sets of programming pulses where each set has the same quantity of pulses and each programming pulse in the set has substantially the same amplitude (i.e., programming voltage). The amplitude of the programming pulses of subsequent sets is increased by a step voltage from the previous amplitude. | 06-24-2010 |
20110255343 | PROGRAMMING IN A MEMORY DEVICE - Methods for programming a memory device and memory devices are provided. According to at least one such method, a selected memory cell is programmed by a series of programming pulses. The series of programming pulses are configured in sets of programming pulses where each set has the same quantity of pulses and each programming pulse in the set has substantially the same amplitude (i.e., programming voltage). The amplitude of the programming pulses of subsequent sets is increased by a step voltage from the previous amplitude. | 10-20-2011 |
20120269011 | VOLTAGE SWITCHING IN A MEMORY DEVICE - Voltage switches, memory devices, memory systems, and methods for switching are disclosed. One such voltage switch uses a pair of switch circuits coupled in series, each switch circuit being driven by a level shift circuit. Each switch circuit uses a group of series coupled transistors with a parallel control transistor where the number of transistors in each group may be determined by an expected switch input voltage and a maximum allowable voltage drop for each transistor. A voltage of a particular state of an enable signal is shifted up to the switch input voltage by the level shift circuits. The particular state of the enable signal turns on the voltage switch such that the switch output voltage is substantially equal to the switch input voltage. | 10-25-2012 |
20130215688 | VOLTAGE SWITCHING IN A MEMORY DEVICE - Voltage switches, memory devices, memory systems, and methods for switching are disclosed. One such voltage switch uses a pair of switch circuits coupled in series, each switch circuit being driven by a level shift circuit. Each switch circuit uses a group of series coupled transistors with a parallel control transistor where the number of transistors in each group may be determined by an expected switch input voltage and a maximum allowable voltage drop for each transistor. A voltage of a particular state of an enable signal is shifted up to the switch input voltage by the level shift circuits. The particular state of the enable signal turns on the voltage switch such that the switch output voltage is substantially equal to the switch input voltage. | 08-22-2013 |
Patent application number | Description | Published |
20090141558 | Sensing memory cells - The present disclosure includes methods, devices, modules, and systems for operating memory cells. One method embodiment includes applying a ramping voltage to a control gate of a memory cell and to an analog-to-digital converter (ADC). The aforementioned embodiment of a method also includes detecting an output of the ADC at least partially in response to when the ramping voltage causes the memory cell to trip sense circuitry. | 06-04-2009 |
20100008165 | MEMORY CELL SENSING USING NEGATIVE VOLTAGE - Embodiments of the present disclosure provide methods, devices, modules, and systems for memory cell sensing using negative voltage. One method includes applying a negative read voltage to a selected access line of an array of memory cells, applying a pass voltage to a number of unselected access lines of the array, and sensing whether a cell coupled to the selected access line is in a conductive state in response to the applied negative read voltage. | 01-14-2010 |
20110141822 | Source Bias Shift for Multilevel Memories - The threshold voltage range of a multilevel memory cell may be increased without using a negative voltage pump. In one embodiment, an added positive voltage may be applied to the source of the selected cell. A boost voltage may be applied to the output of a sense amplifier. Non-ideal characteristics of a buffer that supplies the voltage to the selected cell may be compensated for in some embodiments. | 06-16-2011 |
20110249507 | SENSING MEMORY CELLS - The present disclosure includes methods, devices, modules, and systems for operating memory cells. One method embodiment includes applying a ramping voltage to a control gate of a memory cell and to an analog-to-digital converter (ADC). The aforementioned embodiment of a method also includes detecting an output of the ADC at least partially in response to when the ramping voltage causes the memory cell to trip sense circuitry. | 10-13-2011 |
20120176837 | MEMORY CELL SENSING USING NEGATIVE VOLTAGE - Embodiments of the present disclosure provide methods, devices, modules, and systems for memory cell sensing using negative voltage. One method includes applying a negative read voltage to a selected access line of an array of memory cells, applying a pass voltage to a number of unselected access lines of the array, and sensing whether a cell coupled to the selected access line is in a conductive state in response to the applied negative read voltage. | 07-12-2012 |
20130272053 | APPARATUSES AND METHODS FOR PROVIDING SET AND RESET VOLTAGES AT THE SAME TIME - Apparatuses and methods are described, such as those involving driver circuits that are configured to provide reset and set voltages to different variable state material memory cells in an array at the same time. Additional apparatuses, and methods are described. | 10-17-2013 |
20130308376 | APPARATUSES INCLUDING CURRENT COMPLIANCE CIRCUITS AND METHODS - Apparatus, devices, systems, and methods are described that include variable state material data storage. Example devices include current compliance circuits that are configured to dynamically adjust a current passing through a variable resistance material during a memory operation. Some configurations utilize components within an array of memory cells to form a current compliance circuit. Additional apparatus, systems, and methods are described. | 11-21-2013 |
20140098607 | SENSING MEMORY CELLS - The present disclosure includes methods, devices, modules, and systems for operating memory cells. One method embodiment includes applying a ramping voltage to a control gate of a memory cell and to an analog-to-digital converter (ADC). The aforementioned embodiment of a method also includes detecting an output of the ADC at least partially in response to when the ramping voltage causes the memory cell to trip sense circuitry. | 04-10-2014 |
20140104922 | APPARATUSES, CIRCUITS, AND METHODS FOR BIASING SIGNAL LINES - Apparatuses, circuits, and methods are disclosed for biasing signal lines in a memory array. In one such example the memory array includes a signal line coupled to a plurality of memory cells and is configured to provide access to the plurality of memory cells responsive to a biasing condition of the signal line. The memory array also includes a signal line driver coupled to the signal line, the signal line driver configured to provide a biasing signal to the signal line and to provide a preemphasis in the biasing signal responsive to a control signal. The control signal is responsive to an operating condition. | 04-17-2014 |
20150023095 | APPARATUSES INCLUDING CURRENT COMPLIANCE CIRCUITS AND METHODS - Apparatus, devices, systems, and methods are described that include variable state material data storage. Example devices include current compliance circuits that are configured to dynamically adjust a current passing through a variable resistance material during a memory operation. Some configurations utilize components within an array of memory cells to form a current compliance circuit. Additional apparatus, systems, and methods are described. | 01-22-2015 |
20150269999 | APPARATUSES AND METHODS FOR PROVIDING SET AND RESET VOLTAGES AT THE SAME TIME - Apparatuses and methods are described, such as those involving driver circuits that are configured to provide reset and set voltages to different variable state material memory cells in an array at the same time. Additional apparatuses, and methods are described. | 09-24-2015 |
Patent application number | Description | Published |
20100198250 | ENDOVASCULAR PROSTHESIS DELIVERY SYSTEM - An expandable dilation catheter advantageously useful to deliver and orient an endovascular prosthesis with respect to a target body passageway. The catheter comprises a first tubular member disposed in a proximal portion of the portion of the catheter and a second tubular member disposed in a distal portion of the catheter. The first tubular member and the second tubular member are in a spaced relationship with respect to one another. An expandable member (e.g., a balloon) is disposed distally of the second tubular member. A first lumen and a second lumen disposed in each of the first tubular member and in the second tubular member. The first lumen is in communication with an interior of the expandable member to function as an inflation lumen and the second lumen serves to receive a first guidewire. The first tubular member and second tubular member are interconnected by a coupling member. | 08-05-2010 |
20140128962 | ENDOVASCULAR PROSTHESIS AND DELIVERY DEVICE - In one of its aspects, the present invention relates to an endovascular prosthesis. The endovascular prosthesis comprises a first expandable portion expandable from a first, unexpanded state to a second, expanded state to urge the first expandable portion against a vascular lumen and a retractable leaf portion attached to the first expandable portion. The retractable leaf portion comprises at least one spine portion and a plurality of rib portions attached to the spine portion. Longitudinally adjacent pairs of rib portions are free of interconnecting struts. The endovascular prosthesis that can be unsheathed and re-sheathed for repositioning of the endovascular prosthesis prior to final deployment thereof. There is also described a delivery device that that is particularly well suited to delivering the present endovascular prosthesis through tortuous vasculature in the body. | 05-08-2014 |
20150342762 | ENDOVASCULAR PROSTHESIS AND DELIVERY DEVICE - In one of its aspects, the present invention relates to an endovascular prosthesis. The endovascular prosthesis comprises a first expandable portion expandable from a first, unexpanded state to a second, expanded state to urge the first expandable portion against a vascular lumen and a retractable leaf portion attached to the first expandable portion. The retractable leaf portion comprises at least one spine portion and a plurality of rib portions attached to the spine portion. Longitudinally adjacent pairs of rib portions are free of interconnecting struts. The endovascular prosthesis that can be unsheathed and re-sheathed for repositioning of the endovascular prosthesis prior to final deployment thereof. There is also described a delivery device that that is particularly well suited to delivering the present endovascular prosthesis through tortuous vasculature in the body. | 12-03-2015 |