Yu, Hsinchu City
Anchi Yu, Hsinchu City TW
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20110115900 | Film Scanner - A film scanner includes a specular surface for changing a path and a direction of lights for focusing an image, which is filmed on a film, on a sensing module. With such a disposition, a height of the film scanner is shortened, and a volume of the film scanner is shortened as a result. The film scanner is also burnt with a driver program on a circuit board, which implements or carries an image processing module, so that the film scanner is capable of scanning the image filmed on the film without being connected to a computer, and conveniences in usage and carry of the film scanner is introduced as a result. | 05-19-2011 |
Chang-Lung Yu, Hsinchu City TW
Patent application number | Description | Published |
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20090087236 | PAPER ROUTE SWITCHING APPARATUS - A disk having one or more indentations is configured at one end of a driving shaft and has interaction with an extension arm configured at a corresponding end of a switch shaft for switching the medium conveying route in an image system. When the driving shaft drives the disk to rotate along different directions, the indentation on the disk provides the extension arm room for the disk to guide the extension arm to switch its position between a first position and a second position. A plurality of switch gates on the switch shaft also switch to different positions corresponding to the extension arm such that the conveying route of a medium can be switched between a first route and a second route. | 04-02-2009 |
20090102117 | DE-SKEW MECHANISM - A de-skew mechanism, in an image forming device, with a correcting member disposed in a rotatable manner to the rotary shaft and turning with driving roller by a spring between them. A torque spring suppresses the turning of the correcting member to correct the skew of the medium. When conveyed, the medium will butt against the correcting member to be stopped and corrected. The medium conveying force and the force that the spring brings to the driving roller are sufficient for turning the correcting member and passing therethrough. At one time, the force that the correcting member brings to the medium will reduce to zero. As such, the medium will not be damaged by the correcting member while being conveyed. | 04-23-2009 |
20090189338 | DE-SKEW MECHANISM - A de-skew mechanism includes a driving shaft installed on a frame of an image forming device and driven by a motor, an active roller installed on the driving shaft and driven by the driving shaft, and an idle roller driven by the active roller for driving a medium with the active roller. A nip is formed between the active roller and the idle roller. The de-skew mechanism further includes a correcting member installed on the driving shaft in a rotatable manner and located upstream of the nip for correcting skew of the medium in a correcting position, and a restoring member connected to the correcting member for loading torque to the correcting member so as to drive the connecting member from the correcting position to a releasing position where the medium pass therethrough. | 07-30-2009 |
Chen-Hai Yu, Hsinchu City TW
Patent application number | Description | Published |
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20120104609 | DISCRETE CIRCUIT COMPONENT HAVING COPPER BLOCK ELECTRODES AND METHOD OF FABRICATION - A discrete circuit component has copper block electrodes and that utilizes a simple copper substrate as the basis for the component. The component is made by providing an electrode separation hole preformed in the main substrate. The electrode separation hole results in a simple fabrication for the construction of the discrete component product. With the presence of the electrode separation hole, two solid blocks of copper automatically come into shape for each fabricated device at the final phase of production when each device is cut loose from the main production matrix. | 05-03-2012 |
Chen-Hua Yu, Hsinchu City TW
Patent application number | Description | Published |
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20090117731 | SEMICONDUCTOR INTERCONNECTION STRUCTURE AND METHOD FOR MAKING THE SAME - A semiconductor interconnection structure is manufactured as follows. First, a substrate with a first dielectric layer and a second dielectric layer is formed. Subsequently, an opening is formed in the second dielectric layer. A thin metal layer and a seed layer are formed in sequence on the surface of the second dielectric layer in the opening, wherein the metal layer comprises at least one metal species having phase segregation property of a second conductor. The wafer of the substrate is subjected to a thermal treatment, by which most of the metal species in the metal layer at a bottom of the opening is diffused to a top surface of the second conductor to form a metal-based oxide layer. Afterwards, the wafer is subjected to planarization, so as to remove the second conductor outside the opening. | 05-07-2009 |
20100072632 | BOND PAD STRUCTURE HAVING DUMMY PLUGS AND/OR PATTERNS FORMED THEREAROUND - A semiconductor structure is provided. In one embodiment, a bond pad is formed above one or more underlying layers of a substrate. A plurality of dummy plugs are spaced around the bond pad, the plurality of dummy plugs substantially vertically traversing the one or more underlying layers, wherein the plurality of dummy plugs anchor at least two of the underlying layers together to achieve improved mechanical strength. | 03-25-2010 |
20120206160 | TESTING OF SEMICONDUCTOR CHIPS WITH MICROBUMPS - Test structures for performing electrical tests of devices under one or more microbumps are provided. Each test structure includes at least one microbump pad and a test pad. The microbump pad is a part of a metal pad connected to an interconnect for a device. A width of the microbump pad is equal to or less than about 50 μm. The test pad is connected to the at least one microbump pad. The test pad has a size large enough to allow circuit probing of the device. The test pad is another part of the metal pad. A width of the test pad is greater than the at least one microbump pad. | 08-16-2012 |
20120261827 | THROUGH-SILICON VIAS FOR SEMICONDCUTOR SUBSTRATE AND METHOD OF MANUFACTURE - A semiconductor component includes a semiconductor substrate having a top surface. An opening extends from the top surface into the semiconductor substrate. The opening includes an interior surface. A first dielectric liner having a first compressive stress is disposed on the interior surface of the opening. A second dielectric liner having a tensile stress is disposed on the first dielectric liner. A third dielectric liner having a second compressive stress disposed on the second dielectric liner. A metal barrier layer is disposed on the third dielectric liner. A conductive material is disposed on the metal barrier layer and fills the opening. | 10-18-2012 |
20120326298 | BUMP STRUCTURE WITH BARRIER LAYER ON POST-PASSIVATION INTERCONNECT - A semiconductor device includes a barrier layer between a solder bump and a post-passivation interconnect (PPI) layer. The barrier layer is formed of at least one of an electroless nickel (Ni) layer, an electroless palladium (Pd) layer or an immersion gold (Au) layer. | 12-27-2012 |
20130026614 | STRUCTURE AND METHOD FOR BUMP TO LANDING TRACE RATIO - The present disclosure provides an integrated circuit. The integrated circuit includes an interconnect structure formed on a substrate; a landing metal trace formed on the interconnect structure and coupled to the interconnect structure, wherein the landing metal trace includes a first width T defined in a first direction; and a metal bump post formed on and aligned with the landing metal trace, wherein the metal bump post includes a second width U defined in the first direction, and the second width U is greater than the first width T. | 01-31-2013 |
20130026620 | SELF-ALIGNING CONDUCTIVE BUMP STRUCTURE AND METHOD OF MAKING THE SAME - The disclosure relates to a conductive bump structure of a semiconductor device. An exemplary structure for a semiconductor device comprises a substrate comprising a major surface and conductive bumps distributed over the major surface of the substrate. Each of a first subset of the conductive bumps comprise a regular body, and each of a second subset of the conductive bumps comprise a ring-shaped body. | 01-31-2013 |
20130034956 | CLEANING RESIDUAL MOLDING COMPOUND ON SOLDER BUMPS - A method of forming wafer-level chip scale packaging solder bumps on a wafer substrate involves cleaning the surface of the solder bumps using a laser to remove any residual molding compound from the surface of the solder bumps after the solder bumps are reflowed and a liquid molding compound is applied and cured. | 02-07-2013 |
20130087908 | BUMP WITH PROTECTION STRUCTURE - A semiconductor device includes a bump structure formed on a post-passivation interconnect (PPI) line and surrounded by a protection structure. The protection structure includes a polymer layer and at least one dielectric layer. The dielectric layer may be formed on the top surface of the polymer layer, underlying the polymer layer, inserted between the bump structure and the polymer layer, inserted between the PPI line and the polymer layer, covering the exterior sidewalls of the polymer layer, or combinations thereof. | 04-11-2013 |
20130093076 | SEMICONDUCTOR PACKAGE AND METHOD OF FORMING THE SAME - A method of a semiconductor package includes providing a substrate having a conductive trace coated with an organic solderability preservative (OSP) layer, removing the OSP layer from the conductive trace, and then coupling a chip to the substrate to form a semiconductor package. | 04-18-2013 |
20130134582 | NOVEL BUMP STRUCTURES FOR MULTI-CHIP PACKAGING - The mechanisms for forming a multi-chip package described enable chips with different bump sizes being packaged to a common substrate. A chip with larger bumps can be bonded with two or more smaller bumps on a substrate. Conversely, two or more small bumps on a chip may be bonded with a large bump on a substrate. By allowing bumps with different sizes to be bonded together, chips with different bump sizes can be packaged together to form a multi-chip package. | 05-30-2013 |
20130140713 | Interposer Wafer Bonding Method and Apparatus - The present disclosure relates to a method for fast and precise alignment and mounting of a top die onto an interposer wafer. The method is performed by applying a hydrophobic self assembled monolayer to a carrier wafer in a pattern defining a top die placement region correlating to an arrangement of a top die on an interposer wafer. A liquid is provided into the top die placement region and a top die is placed into contact with the liquid. The surface tension of the liquid automatically aligns the top die by generating a force causing the top die to overlap with the top die placement region. The liquid is then eliminated and the top die is affixed to the carrier wafer. The carrier wafer is bonded to the interposer wafer, bringing the top die into contact with an interposer. | 06-06-2013 |
20130147032 | PASSIVATION LAYER FOR PACKAGED CHIP - The embodiments described above provide mechanisms for forming metal bumps on metal pads with testing pads on a packaged integrated circuit (IC) chip. A passivation layer is formed to cover the testing pads and possibly portions of metal pads. The passivation layer does not cover surfaces away from the testing pad region and the metal pad region. The limited covering of the testing pads and the portions of the metal pads by the passivation layer reduces interface resistance for a UBM layer formed between the metal pads and the metal bumps. Such reduction of interface resistance leads to the reduction of resistance of the metal bumps. | 06-13-2013 |
20130147033 | POST-PASSIVATION INTERCONNECT STRUCTURE - A semiconductor device includes a passivation layer overlying a semiconductor substrate, and an interconnect structure overlying the passivation layer. The interconnect structure includes a landing pad region and a dummy region electrically separated from each other. A protective layer overlies the interconnect structure and includes a first opening exposing a portion of the landing pad region and a second opening exposing a portion of the dummy region. A metal layer is formed on the exposed portion of landing pad region and the exposed portion of the dummy region. A bump is formed on the metal layer overlying the landing pad region. | 06-13-2013 |
20130193578 | THROUGH-SILICON VIAS FOR SEMICONDCUTOR SUBSTRATE AND METHOD OF MANUFACTURE - A semiconductor component includes a semiconductor substrate having a top surface. An opening extends from the top surface into the semiconductor substrate. The opening includes an interior surface. A first dielectric liner having a first compressive stress is disposed on the interior surface of the opening. A second dielectric liner having a tensile stress is disposed on the first dielectric liner. A third dielectric liner having a second compressive stress disposed on the second dielectric liner. A metal barrier layer is disposed on the third dielectric liner. A conductive material is disposed on the metal barrier layer and fills the opening. | 08-01-2013 |
20130221074 | SOLDER BUMP STRETCHING METHOD - A method includes heating a solder bump above a melting temperature of the solder bump. The solder bump is stretched to increase a height of the solder bump. The solder bump is cooled down. | 08-29-2013 |
20130221521 | SOLDER BUMP STRETCHING METHOD FOR FORMING A SOLDER BUMP JOINT IN A DEVICE - A method includes heating a solder bump above a melting temperature of the solder bump. The solder bump is stretched to increase a height of the solder bump. The solder bump is cooled down to form a solder bump joint in an electrical device. | 08-29-2013 |
20130228927 | INTERCONNECT STRUCTURES - A semiconductor structure includes a first dielectric layer over a substrate. At least one first conductive structure is within the first dielectric layer. The first conductive structure includes a cap portion extending above a top surface of the first dielectric layer. At least one first dielectric spacer is on at least one sidewall of the cap portion of the first conductive structure. | 09-05-2013 |
20130270702 | COPPER INTERCONNECT STRUCTURE AND METHOD FOR FORMING THE SAME - A copper interconnect structure in a semiconductor device including an opening formed in a dielectric layer of the semiconductor device, the opening having sidewalls and a bottom. A first barrier layer is conformally deposited on the sidewalls and the bottom of the opening. A first seed layer is conformally deposited on the first barrier layer. A second barrier layer is conformally deposited on the first seed layer. A second seed layer is conformally deposited on the second barrier layer and a conductive plug is deposited in the opening of the dielectric layer. | 10-17-2013 |
20130277844 | THROUGH VIA PROCESS - A semiconductor component having a semiconductor substrate including an integrated circuit (IC) component, an interlayer dielectric (ILD) layer formed on the semiconductor substrate, a contact plug formed in the ILD layer and electrically connected to the IC component, a via plug formed in the ILD layer and extending through a portion of the semiconductor substrate, wherein the top surfaces of the ILD layer, the via plug and the contact plug are leveled off, and an interconnection structure comprising a plurality of metal layers formed in a plurality of inter-metal dielectric (IMD) layers, wherein a lowermost metal layer of the interconnection structure is electrically connected to the exposed portions of the contact plug and the via plug. | 10-24-2013 |
20130307144 | THREE-DIMENSIONAL CHIP STACK AND METHOD OF FORMING THE SAME - A three dimensional (3D) chip stack includes a first chip bonded to a second chip. The first chip includes a first bump structure overlying the first substrate, and the second chip includes a second bump structure overlying the second substrate. The first bump structure is attached to the second bump structure, and a joining region is formed between the first bump structure and the second bump structure. The joining region is a solderless region which includes a noble metal. | 11-21-2013 |
20130320225 | DEVICES AND METHODS FOR IMPROVED REFLECTIVE ELECTRON BEAM LITHOGRAPHY - A device for reflective electron-beam lithography and methods of producing the same are described. The device includes a substrate, a plurality of conductive layers formed on the substrate, which are parallel to each other and separated by insulating pillar structures, and a plurality of apertures in each conductive layer. Apertures in each conductive layer are vertically aligned with the apertures in other conductive layers and a periphery of each aperture includes conductive layers that are suspended. | 12-05-2013 |
20140014959 | PASSIVATION LAYER FOR PACKAGED CHIP - A packaged IC chip includes a testing pad, wherein the testing pad is electrically connected to devices in the packaged integrated circuit chip. The packaged IC chip further includes a first passivation layer over a portion of the testing pad, and a second passivation layer covering a surface of the testing pad and a portion of the first passivation layer surrounding the testing region of the testing pad. A distance between edges of the second passivation layer covering the surface of the testing pad to edges of the testing pad is in a range from about 2 mm to about 15 mm. | 01-16-2014 |
20140015146 | SEMICONDUCTOR COMPONENT HAVING THROUGH-SILICON VIAS AND METHOD OF MANUFACTURE - A semiconductor component includes a semiconductor substrate having an opening A first dielectric liner having a first compressive stress is disposed in the opening. A second dielectric liner having a tensile stress is disposed on the first dielectric liner. A third dielectric liner having a second compressive stress disposed on the second dielectric liner. | 01-16-2014 |
20140054637 | Omnidirectional Reflector - A system and method for manufacturing an LED is provided. A preferred embodiment includes a substrate with a distributed Bragg reflector formed over the substrate. A photonic crystal layer is formed over the distributed Bragg reflector to collimate the light that impinges upon the distributed Bragg reflector, thereby increasing the efficiency of the distributed Bragg reflector. A first contact layer, an active layer, and a second contact layer are preferably either formed over the photonic crystal layer or alternatively attached to the photonic crystal layer. | 02-27-2014 |
20140054760 | PACKAGE-ON-PACKAGE SEMICONDUCTOR DEVICE - A semiconductor device and method of forming the semiconductor device, the semiconductor device includes a package having at least one first die and at least one second die. The semiconductor device further includes a set of conductive elements electrically connecting the at least one first and the at least one second die to a substrate. The semiconductor device further includes a thermal contact pad between the at least one first die and the at least one second die, to thermally isolate the at least one first die from the at least one second die. | 02-27-2014 |
20140127857 | Carrier Wafers, Methods of Manufacture Thereof, and Packaging Methods - Carrier wafers, methods of manufacture thereof, and packaging methods are disclosed. In one embodiment, a carrier wafer includes a first glass layer. The carrier wafer includes a second glass layer coupled to the first glass layer. The first glass layer has a first coefficient of thermal expansion (CTE), and the second glass layer has a second CTE. | 05-08-2014 |
20140130962 | THIN WAFER HANDLING METHOD - A method includes receiving a carrier with a release layer formed thereon. A first adhesive layer is formed on a wafer. A second adhesive layer is formed over the first adhesive layer or over the release layer. The carrier and the wafer are bonded with the release layer, the first adhesive layer, and the second adhesive layer in between the carrier and the wafer. | 05-15-2014 |
20140131865 | Structure and Method for Bump to Landing Trace Ratio - The present disclosure provides an integrated circuit. The integrated circuit includes an interconnect structure formed on a substrate; a landing metal trace formed on the interconnect structure and coupled to the interconnect structure, wherein the landing metal trace includes a first width T defined in a first direction; and a metal bump post formed on and aligned with the landing metal trace, wherein the metal bump post includes a second width U defined in the first direction, and the second width U is greater than the first width T. | 05-15-2014 |
20140131896 | Exposing Connectors in Packages Through Selective Treatment - A method includes performing an etching step on a package. The package includes a package component, a connector on a top surface of the package component, a die bonded to the top surface of the package component, and a molding material molded over the top surface of the package component. The molding material covers the connector, wherein a portion of the molding material covering the connector is removed by the etching step, and the connector is exposed. | 05-15-2014 |
20140175548 | High Temperature Gate Replacement Process - A method for fabricating an integrated circuit device is disclosed. An exemplary method comprises performing a gate replacement process to form a gate structure, wherein the gate replacement process includes an annealing process; after the annealing process, removing portions of a dielectric material layer to form a contact opening, wherein a portion of the substrate is exposed; forming a silicide feature on the exposed portion of the substrate through the contact opening; and filling the contact opening to form a contact to the exposed portion of the substrate. | 06-26-2014 |
20140220741 | STACKED STRUCTURES AND METHODS OF FORMING STACKED STRUCTURES - A stacked structure includes a first die bonded over a second die. The first die has a first die area defined over a first surface. At least one first protective structure is formed over the first surface, around the first die area. At least one side of the first protective structure has at least one first extrusion part extending across a first scribe line around the protective structure. The second die has a second die area defined over a second surface. At least one second protective structure is formed over the second surface, around the second die area. At least one side of the second protective structure has at least one second extrusion part extending across a second scribe line around the protective structure, wherein the first extrusion part is connected with the second extrusion part. | 08-07-2014 |
20140235001 | Reflective Layer for Light-Emitting Diodes - A system and method for manufacturing a light-generating device is described. A preferred embodiment comprises a plurality of LEDs formed on a substrate. Each LED preferably has spacers along the sidewalls of the LED, and a reflective surface is formed on the substrate between the LEDs. The reflective surface is preferably located lower than the active layer of the individual LEDs. | 08-21-2014 |
20140253262 | RF CHOKE DEVICE FOR INTEGRATED CIRCUITS - Among other things, one or more techniques and systems for selectively filtering RF signals within one or more RF frequency band are provided. In particular, an RF choke, such as a 3D RF choke or a semi-lumped RF choke, configured to selectively filter such RF signals is provided. The RF choke comprises a metal connection line configured as an inductive element for the RF choke. In an example, one or more metal lines, such as a metal open stub, are formed as capacitive elements for the RF choke. In another example, one or more through vias are formed as capacitive elements for the RF choke. In this way, the RF choke allows DC power signals to pass through the metal connection line, while impeding RF signals within the one or more RF frequency bands from passing through the metal connection line. | 09-11-2014 |
20140264930 | Fan-Out Interconnect Structure and Method for Forming Same - A method embodiment includes forming a sacrificial film layer over a top surface of a die, the die having a contact pad at the top surface. The die is attached to a carrier, and a molding compound is formed over the die and the sacrificial film layer. The molding compound extends along sidewalls of the die. The sacrificial film layer is exposed. The contact pad is exposed by removing at least a portion of the sacrificial film layer. A first polymer layer is formed over the die, and a redistribution layer (RDL) is formed over the die and electrically connects to the contact pad. | 09-18-2014 |
20140299985 | BUMP STRUCTURES FOR MULTI-CHIP PACKAGING - A multi-chip package includes a substrate having a plurality of first bump structures. A pitch between first bump structures of the plurality of first bump structures is uniform across a surface of the substrate. The multi-chip package includes a first chip bonded to the substrate and a second chip bonded to the substrate. The first chip includes a plurality of second bump structures, and the plurality of second bump structures are bonded to a first set of first bump structures of the plurality of first bump structures. The second chip includes a plurality of third bump structures, and the plurality of third bump structures are bonded to a second set of first bump structures of the plurality of first bump structures. A pitch between second bump structures of the plurality of second bump structures is different from a pitch between third bump structures of the plurality of third bump structures. | 10-09-2014 |
20140327141 | COPPER INTERCONNECT STRUCTURE AND METHOD FOR FORMING THE SAME - A copper interconnect structure in a semiconductor device comprises a dielectric layer having sidewalls and a surface defining an opening in the dielectric layer. The copper interconnect structure also comprises a barrier layer deposited on the sidewalls and the surface of the dielectric layer defining the opening. The copper interconnect structure further comprises a barrier/seed mixed layer deposited on the barrier layer. The copper interconnect structure additionally comprises an adhesive layer deposited on the barrier/seed mixed layer. The copper interconnect structure also comprises a seed layer deposited on the adhesive layer. | 11-06-2014 |
20140327464 | TESTING OF SEMICONDUCTOR CHIPS WITH MICROBUMPS - A test structure including an array of microbumps electrically connecting a chip and a substrate, wherein a width of each microbump of the array of microbumps is equal to or less than about 50 microns (μm). The test structure further includes an interconnect structure connected to the array of microbumps. The test structure further includes an array of test pads around a periphery of the array of microbumps, wherein a test pad of the array of test pads is connected to a corresponding microbump of the array of microbumps through the interconnect structure. A width of the test pad is greater than a width of the corresponding microbump, and the test pad is adapted to be covered after circuit probing by a passivation material to prevent particle and corrosion issues. | 11-06-2014 |
20140363910 | NOVEL SEMICONDUCTOR PACKAGE WITH THROUGH SILICON VIAS - A method of fabricating an LED is provided. A doped layer is formed over a silicon substrate. A plurality of dielectric plugs is formed over the silicon substrate. A light-emitting diode (LED) structure is formed over the doped layer. The LED structure is formed between the dielectric plugs. The dielectric plugs are removed, thereby forming a plurality of openings that partially expose the doped layer. The doped layer is converted into a porous layer at least in part by performing an electro-chemical anodization process through the openings. A conductive substrate is formed over the LED structure. Thereafter, the silicon substrate is removed. The removing of the silicon substrate comprises cleaving the porous layer or chemically etching the porous layer. | 12-11-2014 |
20150021758 | MECHANISMS FOR FORMING BUMP STRUCTURES OVER WIDE METAL PAD - Embodiments of mechanisms for forming a semiconductor die are provided. The semiconductor die includes a semiconductor substrate and a protection layer formed over the semiconductor substrate. The semiconductor die also includes a conductive layer conformally formed over the protection layer, and a recess is formed in the conductive layer. The recess surrounds a region of the conductive layer. The semiconductor die further includes a solder bump formed over the region of the conductive layer surrounded by the recess. | 01-22-2015 |
20150042438 | TUNABLE THREE DIMENSIONAL INDUCTOR - A tunable three-dimensional (3D) inductor comprises a plurality of vias arranged with spacing among them, a plurality of interconnects in a metal layer, wherein the plurality of interconnects connect the plurality of vias on one end, and a plurality of tunable wires that connects to the plurality of vias on the other end to form the 3D inductor. The physical configuration and inductance value of the 3D inductor are adjustable by tuning the plurality of tunable wires during manufacturing process. | 02-12-2015 |
20150053918 | LIGHT-EMITTING DIODE WITH CURRENT-SPREADING REGION - A light-emitting diode (LED) device is provided. The LED device has a lower LED layer and an upper LED layer with a light-emitting layer interposed therebetween. A current blocking layer is formed in the upper LED layer such that current passing between an electrode contacting the upper LED layer flows around the current blocking layer. When the current blocking layer is positioned between the electrode and the light-emitting layer, the light emitted by the light-emitting layer is not blocked by the electrode and the light efficiency is increased. The current blocking layer may be formed by converting a portion of the upper LED layer into a resistive region. In an embodiment, ions such as magnesium, carbon, or silicon are implanted into the upper LED layer to form the current blocking layer. | 02-26-2015 |
20150061162 | SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF - A method of manufacturing a semiconductor structure includes several operations. The several operations include placing a plurality of dies on a carrier; defining a first zone and a second zone in a top surface of the carrier; calculating a first coverage ratio in the first zone; calculating a second coverage ratio in the second zone; disposing a dummy block on a specified location of the top surface of the carrier if the difference between the first coverage ratio and the second coverage ratio is greater than a predetermined value; forming a molding compound on the carrier. | 03-05-2015 |
20150079763 | SOLDER BUMP STRETCHING METHOD AND DEVICE FOR PERFORMING THE SAME - A wafer-level pulling method includes securing a top holder to a plurality of chips; and securing a bottom holder to a wafer, wherein the plurality of chips are bonded to the wafer by a plurality of solder bumps. The wafer-level pulling method further includes softening the plurality of solder bumps; and stretching the plurality of softened solder bumps. | 03-19-2015 |
Chia-Hao Yu, Hsinchu City TW
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20140186751 | Apparatus Of Repairing A Mask And A Method For The Same - An apparatus includes a probe tip configured to contact the mask, a cantilever configured to mount the probe tip wherein the cantilever includes a mirror, an optical unit having a light source projecting a light beam on the mirror and a light detector receiving a reflected light beam from the mirror, and an electrical power supply configured to connect the probe tip. The apparatus further includes a computer system configured to connect the optical unit, the electrical power supply, and the stage. The electrical power supply provides an electrical current to the probe tip and heats the probe tip to a predetermined temperature. The heated probe tip repairs a defect by smoothing and reducing a dimension of the defect, and inducing structural deformations of multilayer that cancel out the distortion (of multilayer) caused by buried defects using the heated probe tip as a thermal source canning the defect. | 07-03-2014 |
20140268074 | Lithography System with an Embedded Cleaning Module - The present disclosure provides a lithography system. The lithography system includes an exposing module configured to perform a lithography exposing process using a mask secured on a mask stage; and a cleaning module integrated in the exposing module and designed to clean at least one of the mask and the mask stage using an attraction mechanism. | 09-18-2014 |
20150072270 | Method Of Manufacturing An Extreme Ultraviolet (EUV) Mask And The Mask Manufactured Therefrom - Any defects in the reflective multilayer coating or absorber layer of an EUV mask are problematic in transferring a pattern of the EUV mask to a wafer since they produce errors in integrated circuit patterns on the wafer. In this regard, a method of manufacturing an EUV mask is provided according to various embodiments of the present disclosure. To repair the defect, a columnar reflector, which acts as a Bragg reflector, is deposited according to various embodiments so as to locally compensate and repair the defect. According to the embodiments of the present disclosure, the reflective loss due to the defect can be compensated and recover the phase different due to the defect from, so as to form a desirable wafer printed image. | 03-12-2015 |
Chia-Hung Yu, Hsinchu City TW
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20140084188 | APPARATUS FOR MEASURING THE OPTOELECTRONIC CHARACTERISTICS OF LIGHT-EMITTING DIODE - An apparatus for measuring the optoelectronic characteristics of a light-emitting diode includes: a container including a light input port and a light output port; a measurement module connected to the light output port of the container; a sample holder under the container for holding a light-emitting diode under test, wherein a surface of the measurement module reflects more than 50% of the luminous flux generated by the light-emitting diode under test; and a light gathering unit between the container and the sample holder, wherein an interior wall of the light gathering unit reflects more than 50% of the luminous flux generated by the light-emitting diode under test. | 03-27-2014 |
Chia-Wei Yu, Hsinchu City TW
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20110310095 | THREE DIMENSIONAL PROCESSING CIRCUIT AND PROCESSING METHOD - A three dimensional processing circuit and processing method is disclosed. In the present invention, a key depth is obtained to change an OSD location by analyzing the key image information in the 3D image. Therefore, the disadvantages of the conventional 3D processing circuit and processing method are fixed so as to decrease fatigue of user's eyes. | 12-22-2011 |
Chien-Hsien Yu, Hsinchu City TW
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20090101899 | STACKED STRUCTURE AND METHOD OF PATTERNING THE SAME AND ORGANIC THIN FILM TRANSISTOR AND ARRAY HAVING THE SAME - A stacked structure including a soluble organic semiconductor material and a water soluble photosensitive material is provided. The water soluble photosensitive material is disposed on the surface of the soluble organic semiconductor material. | 04-23-2009 |
20120138909 | STACKED STRUCTURE AND ORGANIC THIN FILM TRANSISTOR AND ARRAY HAVING THE SAME - A stacked structure including a soluble organic semiconductor material and a water soluble photosensitive material is provided. The water soluble photosensitive material is directly disposed on the surface of the soluble organic semiconductor material. | 06-07-2012 |
20120139869 | REATTACHABLE TOUCH INPUT DEVICE - A reattachable touch input device is for use with an electronic device. The reattachable touch input device includes a touch sensing layer and a reattachable attachment member. The touch sensing layer is operable to generate a touch position signal in response to at least one touch action detected thereby. The reattachable attachment member is disposed under the touch sensing layer and is configured for releasable attachment of the reattachable touch input device to a surface. | 06-07-2012 |
Chih-Chieh Yu, Hsinchu City TW
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20120044715 | BACKLIGHT MODULE AND DISPLAY DEVICE HAVING THE SAME - A backlight module includes a light guide plate, at least one first light source, and at least one second light source. A first light incident surface and a second light incident surface are alternately arranged on a light incident side of the light guide plate and form an angle with each other. The first light source is disposed adjacent to the first light incident surface, and a light beam emitted by the first light source is guided towards a left half of the light guide plate. The second light source is disposed adjacent to the second light incident surface, and a light beam emitted by the second light source is guided towards a right half of the light guide plate. The first light source and the second light source are alternately turned on and off in succession. | 02-23-2012 |
Chih-Jen Yu, Hsinchu City TW
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20120264063 | METHOD AND SYSTEM FOR FEED-FORWARD ADVANCED PROCESS CONTROL - A method including providing a present wafer to be processed by a photolithography tool, selecting a processed wafer having a past chip design from a plurality of processed wafers, the processed wafer being previously processed by the photolithography tool, selecting a plurality of critical dimension (CD) data points extracted from a plurality of fields on the processed wafer, modeling the plurality of CD data points with a function relating CD to position on the processed wafer, creating a field layout on the present wafer for a new chip design, creating an initial exposure dose map for the new chip design using the function and the field layout, and controlling the exposure of the photolithography tool according to the initial exposure dose map to form the new chip design on the present wafer. | 10-18-2012 |
20130239073 | METHOD AND SYSTEM FOR FEED-FORWARD ADVANCED PROCESS CONTROL - Embodiments of the present disclosure disclose a method of forming a new integrated circuit design on a semiconductor wafer using a photolithography tool. The method includes selecting a previously processed wafer having a past integrated circuit design different than the new integrated circuit design, selecting a plurality of critical dimension (CD) data points extracted from the previously processed wafer after the previously processed wafer was etched, and creating a field layout and associated baseline exposure dose map for the new integrated circuit design. The method also includes refining each field in the baseline exposure dose map based on a difference between an average CD for the previously processed wafer and an average CD for each field in the field layout and controlling the exposure of the photolithography tool according to the refined baseline exposure dose map to form the new integrated circuit design on the semiconductor wafer. | 09-12-2013 |
Chih-Ming Yu, Hsinchu City TW
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20100320892 | HEAT DISSIPATION ENHANCED LED LAMP FOR SPOTLIGHT - In a LED lamp, a thermally conductive electric insulator is filled in a cavity of a lamp base, a LED filament includes an AC LED device, a resistor is connected with the AC LED device in series between two electrodes of the lamp base to form an electric loop, and a reflective cup has a hole at a bottom thereof to expose the AC LED device and a reflective surface to reflect light of the AC LED device for providing a spotlight. The thermally conductive electric insulator mechanically contacts the LED filament and the first one of the two electrodes, and thereby establishes a heat dissipation channel from the AC LED device to the first electrode therethrough. | 12-23-2010 |
20100320902 | Heat dissipation enhanced LED lamp - A LED lamp which could directly replace an ordinary tungsten, halogen, or electricity-saving light bulb includes a filament, a lamp base and a thermally conductive electric insulator. The filament includes at least one AC LED device, and the thermally conductive electric insulator is filled in a cavity of the lamp base to mechanically contact with the filament and an electrode of the lamp base. When the AC LED device is powered on, the thermally conductive electric insulator provides a thermal channel to transfer heat from the filament to the electrode for heat dissipation enhancement. The LED lamp can be directly inserted into an ordinary bulb socket that is generally used in lighting fixtures, without having to modify the system of the lighting fixtures or use an additional adapter. | 12-23-2010 |
20100320903 | HEAT DISSIPATION ENHANCED LED LAMP - A LED lamp which could directly replace an ordinary tungsten, halogen, or electricity-saving light bulb, includes a LED filament, a lamp base, a thermally conductive electric insulator, and a mask. The thermally conductive electric insulator is filled in a cavity of the lamp base, and includes a first portion mechanically contacting the LED filament and an electrode of the lamp base to provide a first thermal channel from the LED filament to the lamp base, and a second portion adhering the mask to the lamp base to provide a second thermal channel from the lamp base to the mask. By using the mask to enlarge the heat dissipation area, a better heat dissipation effect is achieved. | 12-23-2010 |
20110014840 | ASSEMBLY METHOD OF A LED LAMP - Simple, rapid and low-cost assembly methods of a LED lamp are provided. A standard lamp base having two electrodes and a cavity is soldered with a resistor to the first one of the electrodes, and then filled with a thermally conductive electric insulator in the cavity. A circuit board is attached onto the thermally conductive electric insulator and then soldered to the second electrode and the resistor. An LED device is soldered onto the circuit board such that the LED device and the resistor are serially connected between the electrodes. Preferably, the circuit board has a through hole through which a thermally conductive member is inserted into the thermally conductive electric insulator with its lower end, and the LED device is placed onto the upper end of the thermally conductive member. | 01-20-2011 |
20110157896 | COLOR LED LAMP - A light diffusion bulb and a color filter bulb are used in a color LED lamp including a white or warm white LED having a power of at least 0.5 W. The light diffusion bulb and color filter bulb both are bounded to a base to enclose the LED. The light diffusion bulb scatters the light of the LED by a great number of particles such that the light diffusion bulb becomes a surface light source conforming to the geometric shape thereof for uniform illumination, and the color filter bulb filters the light of the LED to thereby determine the light color of the LED lamp. Alternatively, the light diffusion function and color filtering function are combined in a single bulb. | 06-30-2011 |
Chih-Sheng Yu, Hsinchu City TW
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20110158861 | VOLATILITY-TYPE ISOLATION AND PURIFICATION DEVICE - The present invention discloses a volatility-type isolation and purification device comprising a substrate and at least one separation region. The surface of the at least one separation region comprises at least one immobilization layer. When a mixture solution comprising at least one substance to be separated is dropped on the at least one separation region, the substances to be separated each is immobilized on the immobilization layer respectively by the volatility or hysteresis of the mixture solution itself. | 06-30-2011 |
20110159547 | POLYMERASE CHAIN REACTON METHOD, POLYMERASE CHAIN REACTON DROPLET DEVICE, AND POLYMERASE CHAIN REACTON DROPLET DEVICE ARRAY - The present invention discloses a polymerase chain reaction (PCR) method, a PCR droplet device and a PCR droplet device array. The steps of the method comprise that a liquid comprising an analyzer is dropped on the heating coil disposed on the droplet device to form a droplet, then dropping a hydrophobic solution to prevent the droplet from evaporating. When an electric current or a voltage is supplied through at least one conducting wire to heat the heating coil, the inside of the droplet can generate buoyancy to drive the analyzer to move to the top of the inside of the droplet. Subsequently, the analyzer is moved to a periphery of the inside of the droplet so as to form a thermal cycle. Therefore the template is amplified by recycling the thermal cycle. | 06-30-2011 |
20120088696 | MICRO ELECTROCHEMICAL MULTIPLEX REAL-TIME PCR PLATFORM - A micro electrochemical multiplex Real-Time PCR platform which can be widely used to rapidly amplify, examine, and quantify target nucleotides in real-time, and can be used in sepsis diagnosis, rapid detection of animal/plant viral or bacterial infections, plant disease control, real-time environmental monitoring, food industry contamination prevention, and improvement of agricultural varieties. | 04-12-2012 |
Chih-Shih Yu, Hsinchu City TW
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20100201844 | Apparatus and Method for Image Capturing - An image capturing method including following steps is provided. A preview image is captured and compressed into a compressed preview image according to a preview quantization table. An image complexity is judged by determining the amount of high frequency components the preview image has according to a set of factors consisting of the preview quantization table, a resolution of the preview image and a size of the compressed preview image. The more the amount of high frequency components the preview image has, the higher the image complexity. A to-be-captured image is captured. An initial quantization table is determined according to a set of factors consisting of the image complexity, a resolution of the to-be-captured image and an image compression target. The to-be-captured image is compressed into an output image according to the initial quantization table. | 08-12-2010 |
Chi-Hua Yu, Hsinchu City TW
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20110253358 | LAMP ASSEMBLY - A lamp assembly is provided, including a light source, a thermal module, a connecting member, and an adapter electrically connected to the light source. The thermal module includes a first thermal member and a second thermal member. The first and second thermal members respectively have a plurality of first and second fins which are arranged in a staggered manner. The second thermal member forms a plurality of through holes for heat dissipation. The light source is disposed on the second thermal member, and the connecting member connects the thermal module with the adapter. | 10-20-2011 |
20110254425 | Lamp Assembly - A lamp assembly is provided, including a light source, a thermal module, a connecting member, and an adapter electrically connected to the light source. The thermal module includes a first thermal member and a second thermal member which are formed by a die casting process, wherein the light source is disposed on the second thermal member. The first and second thermal members respectively have a plurality of first and second fins which are arranged in a staggered manner. The connecting member is formed by a metal extrusion process and extends through the first thermal member to connect the second thermal member with the adapter. | 10-20-2011 |
20130135854 | ILLUMINATION DEVICE - An illumination device includes a base, a flexible circuit board disposed on the base, and a plurality of illumination units. The flexible circuit board has a plurality of first branches and at least one second branch which are connected together. Each of the first branches has a radius of curvature, and the radii of curvature of the first branches are different from or identical to one another, so that the first branches are assembled to form a curved surface. The second branch extends from one of the first branches. After the first branches are assembled, the second branch is overlapped with another first branch. The illumination units are packaged onto the first branches of the flexible circuit board. Here, the illumination units located on one of the first branches is electrically connected to the illumination units located on another of the first branches through the second branch. | 05-30-2013 |
20130152468 | PLANTING CONTAINER AND PLANTING TOWER - A planting container is suitable for forming planting columns by using ones with the same structure three-dimensionally stacked. The planting columns are arranged around a center line parallel to the gravity direction to set up a planting tower. The planting container includes a bottom wall and a side wall. The side wall extends from the peripheral of the bottom wall and both walls define a containing space. The side wall has a planting opening communicating with the containing space. The side wall has a top end and a bottom end. When two containers with the same structure are three-dimensionally stacked by each other, the bottom end of the upper container engages with the top end of the lower container. The side wall laterally tilts towards the center line relatively to the bottom wall, so that the planting column tilts towards the adjacent column and tilts towards the center line. | 06-20-2013 |
Chih-Yeh Yu, Hsinchu City TW
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20140264924 | APPARATUS AND METHOD FOR MITIGATING DYNAMIC IR VOLTAGE DROP AND ELECTROMIGRATION AFFECTS - An integrated circuit structure includes a plurality of power or ground rails for an integrated circuit, the plurality of power or ground rails vertically separated on a plane, a plurality of functional cells between the plurality of power rails or between the plurality of ground rails or both, and a jumper connection between the vertically separated power rails or ground rails, the jumper connection within a vertically aligned gap among the plurality of functional cells. A method of mitigating IR drop and electromigration affects in an integrated circuit includes forming a plurality of power rails or ground rails, each of the power rails or ground rails on separate vertical levels of a plane of an integrated circuit layout and connecting with a jumper connection at least two power rails or two ground rails, the jumper connection within a vertically aligned gap among cells of the integrated circuit. | 09-18-2014 |
Chi-Min Yu, Hsinchu City TW
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20080293342 | CMP HEAD AND METHOD OF MAKING THE SAME - A CMP head includes a membrane support and a membrane. The membrane support is disk-shaped, having an origin and a radius R. The membrane support has at least a ventilator disposed in a central region within the range between origin and (2/3) R, and at least a diversion opening disposed in a peripheral region within the range between (2/3) R and R. The membrane includes a disk-shaped part disposed on the first surface of the membrane support, and an annular part surrounding the annular sidewall of the membrane support. | 11-27-2008 |
Chin-Chih Yu, Hsinchu City TW
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20090305473 | METHOD FOR FABRICATING THIN FILM TRANSISTOR - A method for fabricating a thin film transistor is provided. A gate is formed on a substrate. A gate insulating layer is formed on the substrate to cover the gate. A metal oxide material layer is formed on the gate insulating layer. A photoresist layer is formed on the metal oxide material layer, in which a thickness of the photoresist layer above the gate is larger than that of the photoresist layer above two sides adjacent to the gate. A portion of the metal oxide material layer is removed to form a metal oxide active layer by using the photoresist layer as a mask. The photoresist layer above the two sides adjacent to the gate is removed and the remaining photoresist layer covers a portion of the metal oxide active layer. A source and a drain are formed on the metal oxide active layer covered by the photoresist layer. | 12-10-2009 |
20100044696 | THIN FILM TRANSISTOR AND LIQUID CRYSTAL DISPLAY - A thin film transistor is provided. The thin film transistor includes a substrate, a gate, a source/drain, an insulating layer, and a semiconductor active layer. The gate and the source/drain are respectively deposited on the substrate and are separated by the insulating layer on the substrate. The semiconductor active layer connects the source and the drain. The material of the semiconductor active layer is a semiconductor precursor which produces semiconductor property after being irradiated by a light source. A liquid crystal display which includes the above thin film transistor is also provided. | 02-25-2010 |
Ching-Fang Yu, Hsinchu City TW
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20130157177 | EUV MASK AND METHOD FOR FORMING THE SAME - An extreme ultraviolet (EUV) mask can be used in lithography, such as is used in the fabrication of a semiconductor wafer. The EUV mask includes a low thermal expansion material (LTEM) substrate and a reflective multilayer (ML) disposed thereon. A capping layer is disposed on the reflective ML and a patterned absorption layer disposed on the capping layer. The pattern includes an antireflection (ARC) type pattern. | 06-20-2013 |
20130287287 | METHOD AND APPARATUS FOR DEFECT IDENTIFICATION - A method of identifying defects including producing, with an imaging system, an original image of a fabricated article having a feature thereon, the feature having an intended height and extracting a contour image from the original image, the contour image having an outline of those portions of the feature having a height approximate to the intended height. The method also includes producing a simulated image of the article based upon the contour and creating a defect image based on the differences between the simulated image and the original image, the defect image including any portions of the feature having a height less than the intended height. | 10-31-2013 |
20130322736 | METHOD AND APPARATUS FOR EFFICIENT DEFECT INSPECTION - A method of inspecting fabricated articles includes receiving a fabricated article to be inspected for defects, the fabricated article having a pattern thereon, and the pattern being based on a pattern design and creating a rule set for defining critical regions of the pattern as represented in the pattern design, the critical regions being regions in which defects are more likely to be found during inspection. The method also includes applying the rule set to the pattern design to identify a critical region of the pattern on the fabricated article and a non-critical region of the pattern on the fabricated article. Further, the method includes inspecting the non-critical region of the pattern on the fabricated article for defects at first resolution and inspecting the critical region of the pattern on the fabricated article for defects at a second resolution higher than the first resolution. | 12-05-2013 |
20140205938 | EUV Mask and Method for Forming the Same - An extreme ultraviolet (EUV) mask can be used in lithography, such as is used in the fabrication of a semiconductor wafer. The EUV mask includes a low thermal expansion material (LTEM) substrate and a reflective multilayer (ML) disposed thereon. A capping layer is disposed on the reflective ML and a patterned absorption layer disposed on the capping layer. The pattern includes an antireflection (ARC) type pattern. | 07-24-2014 |
Ching-Tan Yu, Hsinchu City TW
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20120170281 | OPTICAL LENS, OPTICAL LENS MODULE, AND METHOD FOR FORMING CURVED SURFACE OF OPTICAL LENS - An optical lens includes a first curved surface and a second curved surface. The first curved surface is for receiving a light ray, and includes a first curve, a second curve, a first symmetrical curve and a second symmetrical curve disposed on a first plane, and a third curve and a fourth curve disposed on a third plane. The second curved surface is opposite to the first curved surface, and includes a fifth curve, a sixth curve, a fifth symmetrical curve and a sixth symmetrical curve disposed on the first plane, and a seventh curve and an eighth curve disposed on the third plane. The first plane is perpendicular to the third plane, and the curvatures of all the curves are controlled by a weight factor, so that the light ray is emitted onto a preset area through the optical lens. | 07-05-2012 |
Chi-Yeh Yu, Hsinchu City TW
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20120326319 | METHOD AND STRUCTURE FOR THROUGH-SILICON VIA (TSV) WITH DIFFUSED ISOLATION WELL - A semiconductor device and method for forming the same provide a through silicon via (TSV) surrounded by a dielectric liner. The TSV and dielectric liner are surrounded by a well region formed by thermal diffusion. The well region includes a dopant impurity type opposite the dopant impurity type of the substrate. The well region may be a double-diffused well with an inner portion formed of a first material and with a first concentration and an outer portion formed of a second material with a second concentration. The surrounding well region serves as an isolation well, reducing parasitic capacitance. | 12-27-2012 |
20130106459 | 3D-IC INTERPOSER TESTING STRUCTURE AND METHOD OF TESTING THE STRUCTURE | 05-02-2013 |
20130212544 | SYSTEM AND METHOD OF ELECTROMIGRATION MITIGATION IN STACKED IC DESIGNS - A computer implemented method comprises accessing a 3D-IC model stored in a tangible, non-transitory machine readable medium, processing the model in a computer processor to generate a temperature map containing temperatures at a plurality of points of the 3D-IC under the operating condition; identifying an electromigration (EM) rating factor, and calculating and outputting from the processor data representing a temperature-dependent EM current constraint at each point. | 08-15-2013 |
20130304449 | SYSTEM AND METHOD OF ELECTROMIGRATION AVOIDANCE FOR AUTOMATIC PLACE-AND- ROUTE - A method includes identifying at least one local power segment of a circuit, estimating at least one performance parameter of the at least one power segment based on a computer-based simulation of the circuit, and changing a design of the circuit based on at least one electromigration avoidance strategy if the at least one parameter is greater than or equal to a threshold value. A data file representing the circuit is stored if the at least one parameter is less than the threshold value. | 11-14-2013 |
20140096102 | SYSTEM AND METHOD FOR ACROSS-CHIP THERMAL AND POWER MANAGEMENT IN STACKED IC DESIGNS - A computer implemented method comprises accessing a 3D-IC model stored in a tangible, non-transitory machine readable medium, inputting a power profile in a computer processor, generating a transient temperature profile based on the 3D-IC model, identifying a potential thermal violation at a corresponding operating time interval and a corresponding location of a plurality of points of the 3D-IC design, and outputting data representing the potential thermal violation. The 3D-IC model represents a 3D-IC design comprising a plurality of elements in a stack configuration. The power profile is applied to the plurality of elements of the 3D-IC design as a function of an operating time. The transient temperature profile includes temperatures at a plurality of points of the 3D-IC design as a function of an operating time. | 04-03-2014 |
20140101626 | SYSTEM AND METHOD OF ELECTROMIGRATION MITIGATION IN STACKED IC DESIGNS - A computer implemented method comprises accessing a 3D-IC model stored in a tangible, non-transitory machine readable medium, processing the model in a computer processor to generate a temperature map containing temperatures at a plurality of points of the 3D-IC under the operating condition; identifying an electromigration (EM) rating factor, and calculating and outputting from the processor data representing a temperature-dependent EM current constraint at each point. | 04-10-2014 |
20140295655 | METHOD FOR FORMING THROUGH-SILICON VIA (TSV) WITH DIFFUSED ISOLATION WELL - A semiconductor device and method for forming the same provide a through silicon via (TSV) surrounded by a dielectric liner. The TSV and dielectric liner are surrounded by a well region formed by thermal diffusion. The well region includes a dopant impurity type opposite the dopant impurity type of the substrate. The well region may be a double-diffused well with an inner portion formed of a first material and with a first concentration and an outer portion formed of a second material with a second concentration. The surrounding well region serves as an isolation well, reducing parasitic capacitance. | 10-02-2014 |
Chu-Chun Yu, Hsinchu City TW
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20090061204 | Multilayer fire-resistant material - A multilayer fire-resistant material is provided, which comprises two or more layers formed of homogeneous or heterogeneous materials, with at least one layer being an organic/inorganic composite. The organic/inorganic composite comprises an organic component of a polymer, oligomer, or copolymer having a first reactive functional group, and inorganic particles having a second reactive functional group. The inorganic particles are chemically bonded to the organic component via a reaction between the first and the second reactive functional groups. | 03-05-2009 |
Chung-Shan Yu, Hsinchu City TW
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20140066614 | PROBE OF IODINE-123 MARKER THYMIDINE (FLT)ANALOGUE [123I]-IARAU - A tumor radiation probe of iodine-123 marker thymidine (FLT) analogue [ | 03-06-2014 |
Feng-Chi Yu, Hsinchu City TW
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20140351800 | Establishing Platform for If-This-Than-That Rule Based Application Program Used in Mobile Communication Device - The present invention relates to an application program establishing platform and a system of performing the same. The application program establishing platform, which is configured to be implementable on a computer to provide a user with a user interface for establishing an application program based on a user-defined logical determining criterion and implementable on a mobile device, includes: a managing module configured to provide the user to set the user-defined logical determining criterion, wherein the user-defined logical determining criterion is based on an if-this-than-that rule, and to compile the application program into a format implementable on the mobile device. | 11-27-2014 |
Hong-Tu Yu, Hsinchu City TW
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20140118503 | STEREO CAMERA APPARATUS, SELF-CALIBRATION APPARATUS AND CALIBRATION METHOD - A stereo camera apparatus including an image capturing device, an optical axis controlling module and a calculating module is provided. The image capturing device is suitable for obtaining a stereo image, and the image capturing device includes a plurality of image capturing units. The optical axis controlling module is coupled to the image capturing device. The calculating module is coupled to the image capturing device and the optical axis controlling module, wherein the calculating module calculates a calibration condition according to the stereo image. The optical axis controlling module adjusts directions of imaging optical axes of the image capturing units. After being adjusted by the optical axis controlling modules, the imaging optical axes of the image capturing units are aligned. Besides, a self-calibration apparatus and a method of calibration are also provided. | 05-01-2014 |
Hsiang-Cheng Yu, Hsinchu City TW
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20140118297 | Method for improving linearity of touch system coordinates - A method for improving linearity of touch system coordinates first reads two-dimensional raw data of a capacitive touch panel. Next, it reads a pixel and adjacent pixels of the pixel from the two-dimension raw data. Then, it determines whether the value of the pixel is great than a pre-determined threshold. If the value of the pixel is not greater than the pre-determined threshold, it then determines whether there is a value of the adjacent pixels is greater than the pre-determined threshold. If there is no value of the adjacent pixels greater than the pre-determined threshold, it sets the value of the pixel to a pre-determined value. Otherwise, it reserves the value of the pixel in order to increase the linearity of two-dimensional raw data so as to avoid the interference of noise to the two-dimensional raw data. | 05-01-2014 |
Hsueh Ling Yu, Hsinchu City TW
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20100142754 | INSPECTION METHOD AND SYSTEM FOR DISPLAY - A ghost image inspection system comprises a carrier, a reflectance measurement apparatus, and a processing apparatus. The carrier is configured to support the electronic paper display, and the electronic paper display is configured to show a test pattern and at least one sub-frame. The test pattern has a plurality of optical states. The reflectance measurement apparatus is coupled to the carrier and is configured to measure reflectances of the test pattern and at least one sub-frame, and the processing apparatus is coupled to the reflectance measurement apparatus and is configured to determine whether the reflectance is worse than a threshold value of a ghost image index. | 06-10-2010 |
Hui-Hung Yu, Hsinchu City TW
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20090141171 | DISPLAY SYSTEM AND DISPLAY METHOD CAPABLE OF RECEIVING MULTIPLE SOURCES AND WITH SYNCHRONOUS MULTIPLE OUTPUTS - The synchronous briefing or visual playback in different areas and capability of receiving multiple image sources are achieved by connecting various briefing subsystems in different areas via the Internet. One or more image sources are configured in each briefing subsystem and each connected to a server of the subsystem via physical or wireless network. The server of each briefing subsystem transmits briefing or image data to a playback device for outputting purpose via physical or wireless network. The internet-connected servers in all the briefing subsystems are capable of transmitting briefing or image data to one another via the Internet such that briefing or image outputting in one subsystem can be synchronously performed in other subsystems. | 06-04-2009 |
20090167867 | CAMERA CONTROL SYSTEM CAPABLE OF POSITIONING AND TRACKING OBJECT IN SPACE AND METHOD THEREOF - A space position device capable of generating position signals according to its position in space is used in the camera control system for tracking an object. The space position device generates and transmits its position signals to a control unit every predetermined time interval. The control unit then generates control command for controlling a camera to rotate upward/downward, leftward/rightward, zoom in or zoom out according to the generated position signals such that the camera adjusts its focus on the space position device for tracking an object automatically. | 07-02-2009 |
Hui-Yuan Yu, Hsinchu City TW
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20130109614 | ANTAGONISTS FOR DISEASES INDUCED BY CELLS WITH HIGH-AFFINITY ELR-CXC CHEMOKINE RECEPTOR PROTEINS | 05-02-2013 |
20130109834 | HIGH SALT-RESISTANCE ANTIBACTERIAL PEPTIDE AND METHOD FOR PRODUCING THE SAME | 05-02-2013 |
Jian-Shen Yu, Hsinchu City TW
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20090230403 | Dual Gate Layout for Thin Film Transistor - A dual gate layout of a thin film transistor of liquid crystal display to alleviate dark current leakage is disclosed. The layout comprises (1) a polysilicon on a substrate having a L-shaped or a snake shaped from top-view, which has a heavily doped source region, a first lightly doped region, a first gate channel, a second lightly doped region, a second gate channel, a third lightly doped region and a heavily doped drain region formed in order therein; (2) a gate oxide layer formed on the polysilicon layer and the substrate, (3) a gate metal layer then formed on the gate oxide layer having a scanning line and an extension portion with a L-shaped or an I-shaped. The gate metal intersects with the polysilicon layer thereto define the forgoing gate channels. Among of gate channels, at least one is along the signal line, which is connected to the source region through a source contact. | 09-17-2009 |
20090236606 | Dual Gate Layout for Thin Film Transistor - A dual gate layout of a thin film transistor of liquid crystal display to alleviate dark current leakage is disclosed. The layout comprises ( | 09-24-2009 |
20110133200 | Dual Gate Layout for Thin Film Transistor - A dual gate layout of a thin film transistor of liquid crystal display to alleviate dark current leakage is disclosed. The layout includes (1) a polysilicon on a substrate having a L-shaped or a snake shaped from top-view, which has a heavily doped source region, a first lightly doped region, a first gate channel, a second lightly doped region, a second gate channel, a third lightly doped region and a heavily doped drain region formed in order therein; (2) a gate oxide layer formed on the polysilicon layer and the substrate, (3) a gate metal layer then formed on the gate oxide layer having a scanning line and an extension portion with a L-shaped or an I-shaped. The gate metal intersects with the polysilicon layer thereto define the forgoing gate channels. Among of gate channels, at least one is along the signal line, which is connected to the source region through a source contact. | 06-09-2011 |
20110204954 | Voltage Level Shifter - A voltage level shifter formed by single-typed transistors comprises two input terminals, two power supply terminals, a plurality of thin-film transistors, and an output terminal. Another voltage level shifter formed by single-typed transistors comprises two input terminals, an output terminal, two power supply terminals, two input units, a first thin-film transistor, a disable unit, a feedback unit, and a second thin-film transistor. The voltage level shifters are formed by single-typed TFTs. When integrating the voltage level shifters into a substrate of a TFT display, the manufacturing processes are simplified. Besides, power is saved. | 08-25-2011 |
20120175627 | Dual Gate Layout for Thin Film Transistor - A dual gate layout of a thin film transistor of liquid crystal display to alleviate dark current leakage is disclosed. The layout includes (1) a polysilicon on a substrate having a shaped of L- or of snake from top-view, having a heavily doped source region, a first lightly doped region, a first gate channel, a second lightly doped region, a second gate channel, a third lightly doped region and a heavily doped drain region formed in order therein; (2) a gate oxide layer formed on the poly-Si layer and the substrate, (3) a gate metal layer then formed on the gate oxide layer having a scanning line and an extension portion with a L-shaped or an I-shaped. The gate metal intersects with the poly-Si layer thereto define the forgoing gate channels. Among of gate channels, at least one is along the signal line through a source contact. | 07-12-2012 |
Jing-Chi Yu, Hsinchu City TW
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20080291192 | CHARGE RECYCLING SYSTEM OF LIQUID CRYSTAL DISPLAY AND CHARGE RECYCLING METHOD THEREOF - A charge recycling system of a liquid crystal display includes a controller and at least one switch module. The controller outputs at least one control signal when driving signals of a gate line and a source line of the liquid crystal display are both disabled, and the switch module couples the source line to a voltage supply of a driving circuit of the liquid crystal display according to the control signal. In this way, charges stored in a liquid crystal unit coupled to the source line are recycled to the voltage supply of the driving circuit, therefore raising the utilization efficiency of charges of the liquid crystal display and lowering the power consumed by the liquid crystal display. | 11-27-2008 |
20080309681 | DEVICE AND METHOD FOR DRIVING LIQUID CRYSTAL DISPLAY PANEL - A device for driving an LCD panel comprises: a gray level voltage generation circuit, for generating gray level voltages, and determining whether the gray level voltages are generated by utilizing a first set of reference voltages or a second set of reference voltages according to a polarity inversion control signal, where the gray level voltage generation circuit determines whether a gray level voltage is generated by utilizing a maximum of the first set of reference voltages or a maximum of the second set of reference voltages, and determines whether another gray level voltage is generated by utilizing a minimum of the first set of reference voltages or a minimum of the second set of reference voltages; and a source driving circuit, for selecting a gray level voltage according to display data or inverted data of the display data to drive a source of a display cell of the LCD panel. | 12-18-2008 |
20110006396 | SEMICONDUCTOR DEVICE - A semiconductor device of the present invention comprises: a P type semiconductor substrate, an N-well, a first P+ diffusion region, a second P+ diffusion region, a Schottky diode, a first N+ diffusion region, a second N+ diffusion region, a third P+ diffusion region, a fourth P+ diffusion region, a first insulation layer, a second insulation layer, a first parasitic bipolar junction transistor (BJT), and a second parasitic BJT. The Schottky diode is coupled to an input signal. The first N+ diffusion region and the second N+ diffusion region are coupled to a voltage source, respectively. When a voltage level of the input signal is higher than a voltage level of the voltage source, the Schottky diode conducts charges to make the first parasitic BJT and the second parasitic BJT not conducted. | 01-13-2011 |
Jiunn-Der Yu, Hsinchu City TW
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20120069689 | BUILT-IN SELF REPAIR FOR MEMORY - A method for repairing a memory includes running a built-in self-test of the memory to find faulty bits. A first repair result using a redundant row block is calculated. A second repair result using a redundant column block is calculated. The first repair result and the second repair result are compared. A repair method using either the redundant row block or the redundant column block is selected. The memory is repaired by replacing a row block having at least one faulty bit with the redundant row block or replacing a column block having at least one faulty bit with the redundant column block. | 03-22-2012 |
Li-Wen Yu, Hsinchu City TW
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20090042894 | NOVEL SPECIES OF ACROCARPOSPORA, A METHOD OF PREPARING IODININ, AND THE USES OF IODININ - The present invention provides a novel species of | 02-12-2009 |
Ming-Hua Yu, Hsinchu City TW
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20130082309 | SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF - A method for fabricating a semiconductor device is disclosed. A strained material is formed in a cavity of a substrate and adjacent to an isolation structure in the substrate. The strained material has a corner above the surface of the substrate. The disclosed method provides an improved method for forming the strained material adjacent to the isolation structure with an increased portion in the cavity of the substrate to enhance carrier mobility and upgrade the device performance. The improved formation method is achieved by providing a treatment to redistribute at least a portion of the corner in the cavity. | 04-04-2013 |
20130084682 | SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF - A method for fabricating a semiconductor device is disclosed. A strained material is formed in a cavity of a substrate and adjacent to an isolation structure in the substrate. The strained material has a corner above the surface of the substrate. The disclosed method provides an improved method for forming the strained material adjacent to the isolation structure with an increased portion in the cavity of a substrate to enhance carrier mobility and upgrade the device performance. In an embodiment, the improved formation method is achieved using an etching process to redistribute the strained material by removing at least a portion of the corner to be located in the cavity. | 04-04-2013 |
20140367768 | SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF - A method for fabricating a semiconductor device includes forming an isolation feature in a substrate, forming a gate stack over the substrate, forming a source/drain (S/D) recess cavity in the substrate, where the S/D recess cavity is positioned between the gate stack and the isolation feature. The method further includes forming an epitaxial (epi) material in the S/D recess cavity, where the epi material has an upper surface which including a first crystal plane. Additionally, the method includes performing a redistribution process to the epi material in the S/D recess cavity using a chlorine-containing gas, where the first crystal plane is transformed to a second crystal plane after the redistribution. | 12-18-2014 |
Pao-Hsun Yu, Hsinchu City TW
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20110006697 | LOW PIN COUNT LED DRIVER INTEGRATED CIRCUIT - A LED driver integrated circuit has a voltage input pin, a voltage output pin, a capacitor pin, and a switching circuit connected to the capacitor pin and the voltage output pin. The capacitor pin and the voltage output pin are for a flying capacitor to be connected therebetween, and thus the switching circuit and the flying capacitor establish a charge pump to convert an input voltage received by the voltage input pin into an output voltage at the voltage output pin. | 01-13-2011 |
Peichen Yu, Hsinchu City TW
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20120073641 | Solar cell apparatus having the transparent conducting layer with the structure as a plurality of nano-level well-arranged arrays - The invention discloses an apparatus for enhancing light absorption of solar cells and photodetectors by diffraction. The invention comprises the structure as the plurality of nano-level well-arranged arrays with a plurality of certain defect areas including the shapes of rod, tapered-cone, and cone, which diffracts incident light to oblique angles for light trapping. Surface reflection can also be reduced for either broadband or narrow band spectral absorption. The increased contact area between the transparent conducting layer and photoactive layer is beneficial for current extraction, which increases the internal quantum efficiency (IQE). | 03-29-2012 |
Pei-Chen Yu, Hsinchu City TW
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20100040859 | Nanostructured thin-film formed by utilizing oblique-angle deposition and method of the same - The present invention discloses a transparent conductive nanostructured thin-film by oblique-angle deposition and method of the same. An electron beam system is utilized to evaporate the target source. Evaporation substrate is disposed on a plurality of adjustable sample stage. Multiple gas control valve and heat source is provided to control the gas flow and temperature within the process chamber. An annealing process is performed after the evaporation to improve the thin-film structure and optoelectronic properties. | 02-18-2010 |
20100261001 | NANOSTRUCTURED THIN-FILM FORMED BY UTILIZING OBLIQUE-ANGLE DEPOSITION AND METHOD OF THE SAME - The present invention discloses a transparent conductive nanostructured thin-film by oblique-angle deposition and method of the same. An electron beam system is utilized to evaporate the target source. Evaporation substrate is disposed on a plurality of adjustable sample stage. Multiple gas control valve and heat source is provided to control the gas flow and temperature within the process chamber. An annealing process is performed after the evaporation to improve the thin-film structure and optoelectronic properties. | 10-14-2010 |
20100307592 | Three-dimensional indium-tin-oxide electrode, method of fabricating the same, device of fabricating the same, and method of fabricating solar cell comprising the same - A three-dimensional ITO electrode and the method of fabricating the same are disclosed. The three-dimensional ITO electrode of the present invention has a conductive layer and a plurality of ITO nanorods formed on the conductive layer, wherein the length range of the ITO nanorods can vary from 10 nm to 1500 nm. The best length is about 50 nm-200 nm for organic solar cells. When applied into organic optoelectronic devices such as organic solar cells and organic light-emitting diodes (OLEDs), the three-dimensional structure of the ITO electrode may increase the contact area to the active layer, thus improving the electric current collecting efficiency and uniformity of current spreading (flowing). Also, an evaporator, a solar cell comprising the above three-dimensional ITO electrode, and the method of fabricating the solar cell are disclosed. | 12-09-2010 |
20110277839 | ED STRUCTURE AND SOLAR CELL INCLUDING THE SAME - An anti-reflection coating (ARC) stacked structure including a first ARC layer and a second ARC layer is provided. The first ARC layer is a continuous layer and the second ARC layer, located over the first ARC layer, is formed in fractals. In addition, a solar cell including the ARC stacked structure is further provided. | 11-17-2011 |
Ping-Hung Yu, Hsinchu City TW
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20130337434 | Method of Preparing Magnetic Bead Type Nasopharyngeal Enzyme Immunoassay Reagents by Polymerase Chain Reaction - A method of preparing magnetic bead type nasopharyngeal enzyme immunoassay reagents by polymerase chain reaction according to this invention offers in-vitro diagnostic reagents by means of utilizing nanotechnology. This method uses magnetic beads to coat EBV nuclear antigen (Epstein-Barr virus nuclear antigen, EBNA1) or early antigen (Early Antigen, EA). The use of polymerase chain reaction (polymerase Chain Reaction PCR) is for amplified detection. It is found that positive controls of different concentrations, after amplified by PCR, change in their brightness and concentration. That reveals the EBV antigens on the magnetic beads can specifically detect IgA antigens in the serum. | 12-19-2013 |
Po-Shing Yu, Hsinchu City TW
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20130141145 | CLOCK AND DATA RECOVERY CIRCUIT - The invention provides a clock and data recovery (CDR) circuit, including: a phase locked loop (PLL) circuit, providing a reference voltage; a first delay device, delaying an input data according to a control signal so as to generate a first delay signal; an edge detector, generating an edge signal according to the first delay signal and the input data; a second delay device, delaying the edge signal so as to generate a second delay signal; a first gated voltage-controlled oscillator, generating an output recovery clock according to the second delay signal and the reference voltage; a phase detector, detecting a phase difference between the first delay signal and the output recovery clock so as to generate a phase signal and a output recovery data; and an amplifier, amplifying the phase signal by a factor so as to generate the control signal. | 06-06-2013 |
20130169326 | GATED VOLTAGE-CONTROLLED OSCILLATOR AND CLOCK AND DATA RECOVERY CIRCUIT - A gated voltage-controlled oscillator receives a gating signal and outputs an oscillating signal having a frequency corresponding to the gating signal. The gated voltage-controlled oscillator includes a delay unit, having a first terminal and a second terminal, and a multiplexer, having a first input terminal, a second input terminal, a select terminal and an output terminal. The first input terminal and the select terminal are coupled to the gating signal. The second input terminal is coupled to the first terminal of the delay unit. The output terminal outputs the oscillating signal and is coupled to the second terminal of the delay unit. The delay unit delays the oscillating signal and outputs the delayed oscillating signal into the second input terminal. The multiplexer outputs a signal of the first input terminal or the second input terminal according to the gating signal. | 07-04-2013 |
Shang-Jen Yu, Hsinchu City TW
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20120024347 | SOLAR PACKAGE STRUCTURE AND METHOD FOR FABRICATING THE SAME - The invention provides a solar package structure and a method for fabricating the same. A solar package structure includes a carrier wafer. A conductive pattern layer is disposed on the carrier wafer. A solar cell chip array is disposed on the conductive pattern layer, wherein the solar cell chip array electrically connects to the conductive pattern layer. A first spacer dam is disposed on the carrier wafer, surrounding the solar cell chip array. A first optical element array is disposed over the carrier wafer to concentrate sunbeams onto the solar cell chip array, wherein the first optical element array is spaced apart from the carrier wafer by the first spacer dam. | 02-02-2012 |
Shang-Yuan Yu, Hsinchu City TW
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20140158155 | WAFER CLEANING - One or more techniques or systems for cleaning wafers during semiconductor fabrication or an associated brush are provided herein. In some embodiments, the brush includes a brush body and one or more inner hole supports within the brush body. For example, a first inner hole support and a second inner hole support define a first inner hole associated with a first size. For another example, a third inner hole support and a fourth inner hole support define a second inner hole associated with a second size different than the first size. In some embodiments, a cleaning solution is applied to a wafer based on a first flow rate at a first brush position and based on a second flow rate at a second brush position. In this manner, a flow field associated with wafer cleaning is provided, thus enhancing cleaning efficiency, for example. | 06-12-2014 |
20140216500 | Single Wafer Cleaning Tool with H2SO4 Recycling - Some embodiments relate to methods and apparatus for mitigating high metal concentrations in photoresist residue and recycling sulfuric acid (H | 08-07-2014 |
20150064928 | PHOTORESIST REMOVAL - Among other things, one or more systems and techniques for removing a photoresist from a semiconductor wafer are provided. The photoresist is formed over the semiconductor wafer for patterning or material deposition. Once completed, the photoresist is removed in a manner that mitigates damage to the semiconductor wafer or structures formed thereon. In an embodiment, trioxygen liquid is supplied to the photoresist. The trioxygen liquid is activated using an activator, such as an ultraviolet activator or a hydrogen peroxide activator, to create activated trioxygen liquid used to remove the photoresist. In an embodiment, the activation of the trioxygen liquid results in free radicals that aid in removing the photoresist. In an embodiment, an initial photoresist strip, such as using a sulfuric acid hydrogen peroxide mixture, is performed to remove a first portion of the photoresist, and the activated trioxygen liquid is used to remove a second portion of the photoresist. | 03-05-2015 |
Shao-Chi Yu, Hsinchu City TW
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20130105923 | DEEP WELL PROCESS FOR MEMS PRESSURE SENSOR | 05-02-2013 |
20150061007 | HIGH-VOLTAGE SUPER JUNCTION BY TRENCH AND EPITAXIAL DOPING - A high-voltage super junction device is disclosed. The device includes a semiconductor substrate region having a first conductivity type and having neighboring trenches disposed therein. The neighboring trenches each have trench sidewalls and a trench bottom surface. A region having a second conductivity type is disposed in or adjacent to a trench and meets the semiconductor substrate region at a p-n junction. A gate electrode is formed on the semiconductor substrate region and electrically is electrically isolated from the semiconductor substrate region by a gate dielectric. A body region having the second conductivity type is disposed on opposite sides of the gate electrode near a surface of the semiconductor substrate. A source region having the first conductivity type is disposed within in the body region on opposite sides of the gate electrode near the surface of the semiconductor substrate. | 03-05-2015 |
Shih-An Yu, Hsinchu City TW
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20130275064 | MEASUREMENT DEVICES AND MEASUREMENT METHODS FOR POWER CONSUMPTION - A measurement device is provided. The measurement device comprises a power controller, a detector, a temperature sensor, and a processor. The power controller receives alternating-current (AC) power and transforms the AC power to direct-current (DC) power. The detector detects the DC power to generate a voltage value and a current value. The temperature sensor senses an environment temperature of the measurement device. The processor reads the voltage value, the current value, and the environment temperature and obtains an efficiency coefficient of the power controller according to the voltage value, the current value, and the environment temperature. The processor further obtains a real power consumption value corresponding to the AC power according to the efficiency coefficient. | 10-17-2013 |
Shih-Yuan Yu, Hsinchu City TW
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20120182762 | ILLUMINATION MODULE - An illuminating module includes at least one light-emitting chip, a phosphor, and a color temperature conversion media. The light-emitting chip is capable of emitting wavelength light, and the phosphor is disposed in a propagation path of the wavelength light to transform the wavelength light into a first white light with a first color temperature. The color temperature conversion media is disposed in a propagation path of the first white light to transform the first white light into a second white light with a second color temperature. The second color temperature is smaller than the first color temperature. | 07-19-2012 |
Shinn-Sheng Yu, Hsinchu City TW
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20080248403 | METHOD AND SYSTEM FOR IMPROVING CRITICAL DIMENSION UNIFORMITY - A method for improving critical dimension uniformity of a wafer includes exposing a plurality of mask patterns on a first plurality of substrates at predetermined locations with common splits conditions of focus and exposure dose for each of the first plurality of substrates to form a plurality of perturbed wafers; measuring a critical dimension of the plurality of mask patterns at each of the predetermined locations for each of the plurality of perturbed wafers; averaging the critical dimension measured at each of the predetermined locations over the plurality of perturbed wafers to form a perturbed critical dimension map; measuring a sidewall angle of the plurality of mask patterns; averaging the sidewall angle measured to form a perturbed sidewall angle map; and providing the perturbed critical dimension map and the perturbed sidewall angle map to an exposure tool. | 10-09-2008 |
Shu-Han Yu, Hsinchu City TW
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20140104540 | LIQUID CRYSTAL PANEL AND THE APPARATUS USING THE SAME - This disclosure provides a LC panel and a LCD apparatus using the LC panel. The LC panel includes: a first substrate and a second substrate opposing the first substrate, arranging the first substrate to face the second substrate; a LC layer containing a plurality of LC molecules between the first substrate and second substrate; and a plurality of vertical alignment molecules, each comprising a long-chain alignment terminal, a cross-linking terminal, and at least one bonding terminal; wherein the at least one bonding terminal couples the vertical alignment molecule to the first or second substrate to form a surface bonding, the long-chain alignment terminals are parallel to each other and perpendicular to the first or second substrate, the cross-linking terminals link the neighboring vertical alignment molecules together, and the LC molecules are vertically aligned between the first substrate and second substrate by means of the long-chain alignment terminals. | 04-17-2014 |
Shu-Jenn Yu, Hsinchu City TW
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20140264618 | ISOLATION STRUCTURE - A structure comprises a p-type substrate, a deep n-type well and a deep p-type well. The deep n-type well is adjacent to the p-type substrate and has a first conductive path to a first terminal. The deep p-type well is in the deep n-type well, is separated from the p-type substrate by the deep n-type well, and has a second conductive path to a second terminal. A first n-type well is over the deep p-type well. A first p-type well is over the deep p-type well. | 09-18-2014 |
Tsung-Hsin Yu, Hsinchu City TW
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20140007031 | SEMICONDUCTOR DEVICE DESIGN METHOD, SYSTEM AND COMPUTER PROGRAM PRODUCT | 01-02-2014 |
20140091837 | START-UP CIRCUIT FOR AN OUTPUT DRIVER - One or more techniques and systems for starting an output driver and an associated start-up circuit are provided herein. In some embodiments, a voltage provider is configured to charge a charge store to a pre-turn-on voltage. In some embodiments, an output driver is configured to control a connection between the charge store and the output driver. For example, the connection enables the charge store to discharge a voltage to the output driver, thus starting the output driver. Accordingly, a response time associated with starting the output driver is mitigated at least because the charge store is charged to the pre-turn-on voltage and connected to the output driver such that a gate of the driver is biased in a sudden fashion. In this manner, the driver is turned on more quickly. Additionally, effects associated with process, voltage, and temperature variations are mitigated, for example. | 04-03-2014 |
20150074627 | SEMICONDUCTOR DEVICE DESIGN METHOD, SYSTEM AND COMPUTER PROGRAM PRODUCT - A semiconductor device design method includes extracting voltage data associated with at least one electrical component in a layout of a semiconductor device and based on a result of a simulation of an operation of the semiconductor device. Based on location data of the at least one electrical component, the extracted voltage data is incorporated in the layout to generate a modified layout of the semiconductor device. One or more operations of the method are performed by at least one processor. | 03-12-2015 |
Tu-Hao Yu, Hsinchu City TW
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20080197335 | Semiconductor device and fabrications thereof - A memory device is disclosed. A pillar structure comprises a first electrode layer, a dielectric layer overlying the first electrode layer, and a second electrode layer overlying the dielectric layer. A phase change layer covers a surrounding of the pillar structure. A bottom electrode electrically connects the first electrode layer of the pillar structure. A top electrode electrically connects the second electrode layer of the pillar structure. | 08-21-2008 |
20090148980 | METHOD FOR FORMING PHASE-CHANGE MEMORY ELEMENT - A method for forming a phase-change memory element. The method includes providing a substrate with an electrode formed thereon; sequentially forming a conductive layer and a first dielectric layer on the substrate; forming a patterned photoresist layer on the first dielectric layer; subjecting the patterned photoresist layer to a trimming process, remaining a photoresist pillar; etching the first dielectric layer with the photoresist pillar as etching mask, remaining a dielectric pillar; comformally forming a first phase-change material layer on the conductive layer and the dielectric pillar to cover the top surface and side walls of the dielectric pillar; forming a second dielectric layer to cover the first phase-change material layer; subjecting to the second dielectric layer and the first phase-change material layer to a planarization until exposing the top surface of the dielectric pillar; and forming a second phase-change material layer on the second dielectric layer. | 06-11-2009 |
Tz-Chiang Yu, Hsinchu City TW
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20130200423 | OPTOELECTRONIC SEMICONDUCTOR DEVICE AND THE MANUFACTURING METHOD THEREOF - The present application provides an optoelectronic semiconductor device, comprising: a substrate; an optoelectronic system on the substrate; a barrier layer on the optoelectronic system, wherein the barrier layer thickness is not smaller than 10 angstroms; and an electrode on the barrier layer. | 08-08-2013 |
Wei-Kuan Yu, Hsinchu City TW
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20130239071 | METHOD AND APPARATUS FOR ENHANCED OPTICAL PROXIMITY CORRECTION - Provided is an integrated circuit (IC) design method. The method includes receiving an IC design layout having a feature with an outer boundary, performing a dissection on the feature to divide the outer boundary into a plurality of segments, and performing, using the segments, an optical proximity correction (OPC) on the feature to generate a modified outer boundary. The method also includes simulating a photolithography exposure of the feature with the modified outer boundary to create a contour and performing an OPC evaluation to determine if the contour is within a threshold. Additionally, the method includes repeating the performing a dissection, the performing an optical proximity correction, and the simulating if the contour does not meet the threshold, wherein each repeated dissection and each repeated optical proximity correction is performed on the modified outer boundary generated by the previously performed optical proximity correction. | 09-12-2013 |
20150017571 | PHOTOLITHOGRPAHY SCATTERING BAR STRUCTURE AND METHOD - Provided is an integrated circuit (IC) photo mask. The IC photo mask includes a main feature of the IC, the main feature having a plurality of sides, and a plurality of assist features, the assist features being spaced from each other and spaced from the main feature, wherein each one of the assist features is adjacent to one of the sides, each one of the assist features has an elongated shape along a direction, whereby extending the shape in the direction would intersect at least another one of the assist features and the assist features are sub-resolution correction features for correcting for optical proximity effect in a photolithography process. | 01-15-2015 |
Wei-Lun Yu, Hsinchu City TW
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20140177692 | HYBRID POWER LINE/WIRELESS APPLIANCE AUTOMATION SYSTEM, DEVICE, AND POWER MONITORING METHOD UTILZING THE SAME - The present invention discloses a hybrid power line/wireless appliance automation system for interfacing between at least one electric power distribution circuit and at least one electronic device, a power line communication device, and a power monitoring method using the same. Each power line communication device can be communicatively interconnected via power line communication and/or wireless communication. A threshold value of each power line communication device is dynamically adjusted by a host device via wired or wireless connection, so as to determine whether to continuously supply or turn off power to an electronic device coupled to the power line communication device. The present invention may be implemented/integrated to existing household electric power network without the need for additional physical data network infrastructure/lines, therefore is suitable to be applied in an intelligent home management system. | 06-26-2014 |
Ya-Yun Yu, Hsinchu City TW
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20110311919 | METHOD FOR FABRICATING AN IMAGE SENSOR DEVICE - A method for fabricating an image sensor device is disclosed. The method for fabricating an image sensor device comprises forming a photosensitive layer on a substrate. The photosensitive layer is exposed through a first photomask to form an exposed portion and an unexposed portion. The unexposed portion is partially exposed through a second photomask to form a trimmed part, wherein the second photomask comprise a first segment and a second segment that has a transmittance greater than that of the first segment. The trimmed part is removed to form photosensitive structures. The photosensitive structures are reflowed to form a first microlens and a second microlens having different heights. | 12-22-2011 |
Yuan-Chu Yu, Hsinchu City TW
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20110283069 | METHOD FOR ESTIMATING CAPACITY USAGE STATUS OF STORAGE UNIT, ASSOCIATED MEMORY DEVICE AND CONTROLLER THEREOF - The present invention provides a method for estimating a capacity usage status of a storage unit, where the storage unit includes a plurality of sectors. The method includes: estimating capacity usage statuses of a portion of sectors; and utilizing a controller to estimate the capacity usage status of the storage unit according to the estimated capacity usage statuses of the portion of sectors in a situation of not estimating capacity usage statuses of all of the sectors of the storage unit. | 11-17-2011 |
Yuan Chuan Yu, Hsinchu City TW
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20140317391 | METHOD FOR CHANGING A SYSTEM PROGRAM AND PROCESSING DEVICE UTILIZING THE SAME - A processing device includes a program memory and a processor. The program memory includes at least a first memory partition for storing a system program and a second memory partition for storing an application program. The processor is coupled to the program memory for executing the programs stored in the program memory. The processor executes the application program to enable the processing device to provide at least a predetermined function, and executes the system program to enable the processing device to update the application program. When the system program has to be changed, the processor further receives a first program from a host, stores the first program in the second memory partition, triggers a reboot procedure to reboot from the second memory partition and thereafter execute the first program to change the system program based on the first program. | 10-23-2014 |