Patent application number | Description | Published |
20090140394 | Semiconductor Device and Method of Forming Through Hole Vias in Die Extension Region Around Periphery of Die - A semiconductor wafer contains a plurality of semiconductor die. The semiconductor wafer is diced to separate the semiconductor die. The semiconductor die are transferred onto a carrier. A die extension region is formed around a periphery of the semiconductor die on the carrier. The carrier is removed. A plurality of through hole vias (THV) is formed in first and second offset rows in the die extension region. A conductive material is deposited in the THVs. A first RDL is formed between contact pads on the semiconductor die and the THVs. A second RDL is formed on a backside of the semiconductor die in electrical contact with the THVs. An under bump metallization is formed in electrical contact with the second RDL. Solder bumps are formed on the under bump metallization. The die extension region is singulated to separate the semiconductor die. | 06-04-2009 |
20090166785 | Semiconductor Device with Optical Sensor and Method of Forming Interconnect Structure on Front and Backside of the Device - A semiconductor package has a semiconductor die with an optically active region which converts light to an electrical signal. An expansion region is formed around the semiconductor die. A through hole via (THV) is formed in the expansion region. Conductive material is deposited in the THV. A passivation layer is formed over the semiconductor die. The passivation layer allows for passage of light to the optically active region of the semiconductor die. A glass layer is applied to the passivation layer. A first RDL is electrically connected between the THV and a contact pad of the semiconductor die. Additional RDLs are formed on a front and back side of the semiconductor die. An under bump metallization (UBM) layer is formed over and electrically connected to the intermediate conduction layer. Solder material is deposited on the UBM and reflowed to form a solder bump. | 07-02-2009 |
20090302452 | MOUNTABLE INTEGRATED CIRCUIT PACKAGE-IN-PACKAGE SYSTEM - A mountable integrated circuit package-in-package system includes: providing an interface integrated circuit package system with a terminal having a plated bumped portion of an inner encapsulation; mounting the interface integrated circuit package system over a package carrier with the terminal facing away from the package carrier; connecting the package carrier and a pad extension of the terminal; and forming a package encapsulation over the interface integrated circuit package system with the terminal exposed. | 12-10-2009 |
20100006993 | INTEGRATED CIRCUIT PACKAGE SYSTEM WITH CHIP ON LEAD - An integrated circuit package system includes: providing a lead having a lead connection surface for connectivity to a next level system; attaching an integrated circuit over the lead having the lead connection surface substantially within a region below a perimeter of the integrated circuit without a die paddle, a substrate conductor, or a redistribution layer; and attaching a die connector to the integrated circuit and the lead. | 01-14-2010 |
20100029046 | INTEGRATED CIRCUIT PACKAGE SYSTEM WITH CONCAVE TERMINAL - An integrated circuit package system includes: connecting a concave terminal and an integrated circuit; and forming an encapsulation, having a bottom side, over the integrated circuit and the concave terminal with the concave terminal within the encapsulation. | 02-04-2010 |
20100140763 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH STACKED PADDLE AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: forming a package paddle and a terminal adjacent to the package paddle; mounting a stack paddle over the package paddle with the stack paddle at a non-center offset with the package paddle; mounting a stack integrated circuit over the stack paddle; and encapsulating the stack integrated circuit and the stack paddle. | 06-10-2010 |
20100140789 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH EXPOSED TERMINAL INTERCONNECTS AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: providing a lead; mounting an inner package so that the lead is peripheral to the inner package, and the inner package having a connection pad; forming an exposed terminal interconnect on the connection pad; and encapsulating the inner package, and partially encapsulating the exposed terminal interconnect with an encapsulation. | 06-10-2010 |
20100289128 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH LEADS AND TRANSPOSER AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: conductively bonding a first surface of a transposer to an inner end of a lead separate from the transposer; conductively bonding a die to the first surface of the transposer; and encapsulating the inner end with a mold compound having a bottom mold surface that is exposed and is coplanar with a surface of the transposer opposite the first surface. | 11-18-2010 |
20100308459 | Semiconductor Device and Method of Forming Through Hole Vias in Die Extension Region Around Periphery of Die - A semiconductor wafer contains a plurality of semiconductor die. The semiconductor wafer is diced to separate the semiconductor die. The semiconductor die are transferred onto a carrier. A die extension region is formed around a periphery of the semiconductor die on the carrier. The carrier is removed. A plurality of through hole vias (THV) is formed in first and second offset rows in the die extension region. A conductive material is deposited in the THVs. A first RDL is formed between contact pads on the semiconductor die and the THVs. A second RDL is formed on a backside of the semiconductor die in electrical contact with the THVs. An under bump metallization is formed in electrical contact with the second RDL. Solder bumps are formed on the under bump metallization. The die extension region is singulated to separate the semiconductor die. | 12-09-2010 |
20100308467 | Semiconductor Device and Method of Forming Through Hole Vias in Die Extension Region Around Periphery of Die - A semiconductor wafer contains a plurality of semiconductor die. The semiconductor wafer is diced to separate the semiconductor die. The semiconductor die are transferred onto a carrier. A die extension region is formed around a periphery of the semiconductor die on the carrier. The carrier is removed. A plurality of through hole vias (THV) is formed in first and second offset rows in the die extension region. A conductive material is deposited in the THVs. A first RDL is formed between contact pads on the semiconductor die and the THVs. A second RDL is formed on a backside of the semiconductor die in electrical contact with the THVs. An under bump metallization is formed in electrical contact with the second RDL. Solder bumps are formed on the under bump metallization. The die extension region is singulated to separate the semiconductor die. | 12-09-2010 |
20100311206 | Semiconductor Device and Method of Forming Through Hole Vias in Die Extension Region Around Periphery of Die - A semiconductor wafer contains a plurality of semiconductor die. The semiconductor wafer is diced to separate the semiconductor die. The semiconductor die are transferred onto a carrier. A die extension region is formed around a periphery of the semiconductor die on the carrier. The carrier is removed. A plurality of through hole vias (THV) is formed in first and second offset rows in the die extension region. A conductive material is deposited in the THVs. A first RDL is formed between contact pads on the semiconductor die and the THVs. A second RDL is formed on a backside of the semiconductor die in electrical contact with the THVs. An under bump metallization is formed in electrical contact with the second RDL. Solder bumps are formed on the under bump metallization. The die extension region is singulated to separate the semiconductor die. | 12-09-2010 |
20110049662 | Semiconductor Device with Optical Sensor and Method of Forming Interconnect Structure on Front and Backside of the Device - A semiconductor device includes a carrier and semiconductor die having an optically active region. The semiconductor die is mounted to the carrier to form a separation between the carrier and the semiconductor die. The semiconductor device further includes a passivation layer disposed over a surface of the semiconductor die and a glass layer disposed over a surface of the passivation layer. The passivation layer has a clear portion for passage of light to the optically active region of the semiconductor die. The semiconductor device further includes an encapsulant disposed over the carrier within the separation to form an expansion region around a periphery of the semiconductor die, a first via penetrating the expansion region, glass layer, and passivation layer, a second via penetrating the glass layer and passivation layer to expose a contact pad on the semiconductor die, and a conductive material filling the first and second vias. | 03-03-2011 |
20110068447 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH CIRCUITRY STACKING AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: forming a lead to include a first tip at one end, a second tip on the end opposite from the first tip with a connect area between each end located above the first tip, and a first tier section or a second tier section located between the connect area and the second tip; connecting a bottom component assembly to the first tier section or the second tier section; connecting a top component assembly over the connect area; and applying an encapsulant over and under the connect area with the first tip exposed. | 03-24-2011 |
20110068458 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH A LEADED PACKAGE AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: providing a first device having a first exposed side and a first inward side; connecting a second device having a second exposed side and a second inward side facing the first inward side to the first device, the second device having planar dimensions less than planar dimensions of the first device; connecting a system connector to a perimeter of the first inward side, the system connector having an exposed leg partially vertical and an exposed foot partially horizontal; and applying an encapsulant exposing the first exposed side, the second exposed side, the exposed leg, and the exposed foot, the exposed leg offset from the encapsulant, the exposed foot on an end of the system connector opposite the first device. | 03-24-2011 |
20110316163 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH MOLDED INTERCONNECTS AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: providing an integrated circuit device; forming package interconnects adjacent the integrated circuit device, the package interconnects having an internal interconnect side with a lock structure; applying an encapsulation over the integrated circuit device and the package interconnects, the lock structure conformally filled with the encapsulation; and forming a base cavity with sides formed by the encapsulation and an external interconnect side of each of an adjacent pair of package interconnects facing one another, the base cavity having a cross-sectional length at least two times a cross-sectional width. | 12-29-2011 |
20120018866 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH ISLAND TERMINALS AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: providing a package paddle having an upper hole below a paddle top side, the upper hole bounded by an upper non-horizontal side with a curve surface; forming a terminal adjacent the package paddle; mounting an integrated circuit on the paddle top side; and forming an encapsulation within the upper hole. | 01-26-2012 |
20120032315 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH DIE PADDLE AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: providing a package paddle having a single integral structure with a paddle central portion surrounded by a paddle peripheral portion; forming a terminal adjacent the package paddle; mounting an integrated circuit over the paddle central portion; and forming an encapsulation over the integrated circuit and the terminal, the encapsulation free of delamination with the encapsulation directly on the paddle peripheral portion. | 02-09-2012 |
20120074547 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH LEAD ENCAPSULATION AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: forming a package paddle; forming a lead adjacent the package paddle, the lead having a hole in a lead body top side and a lead ridge protruding from a lead non-horizontal side; mounting an integrated circuit over the package paddle; connecting an electrical connector to the lead and the integrated circuit; and forming a fill layer within the hole. | 03-29-2012 |
20120146192 | INTEGRATED CIRCUIT MOUNTING SYSTEM WITH PADDLE INTERLOCK AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit mounting system includes: providing a die paddle with a component side having a die mount area and a recess with more than one geometric shape; applying an adhesive on the die mount area and in a portion of the recess; and mounting an integrated circuit device with an inactive side directly on the adhesive. | 06-14-2012 |
20120205811 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH TERMINAL LOCKS AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: providing a terminal having a cornered dimple formed therein as a simple concave polygon; mounting an integrated circuit above and coupled to the terminal; and forming an encapsulation encapsulating the integrated circuit and portions of the terminal. | 08-16-2012 |
20120280376 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH PAD CONNECTION AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: forming a peripheral lead having a peripheral lead bottom side, a peripheral lead top side, a peripheral lead non-horizontal side, a peripheral lead horizontal ridge, and a peripheral lead conductive plate, the peripheral lead horizontal ridge protruding from the peripheral lead non-horizontal side; forming a central lead adjacent to the peripheral lead; forming a first top distribution layer on the peripheral lead top side; connecting an integrated circuit to the first top distribution layer; applying an insulation layer directly on a bottom extent of the first top distribution layer and a peripheral lead ridge lower side of the peripheral lead horizontal ridge; and attaching a heatsink to the central lead under the integrated circuit. | 11-08-2012 |
20120280377 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH PAD CONNECTION AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: forming a peripheral lead having a peripheral lead bottom side, a peripheral lead top side, a peripheral lead non-horizontal side, a peripheral lead horizontal ridge, and a peripheral lead conductive plate, the peripheral lead horizontal ridge protruding from the peripheral lead non-horizontal side; forming a first top distribution layer on the peripheral lead top side, the first top distribution layer having a first top terminal; connecting an integrated circuit to the first top distribution layer, the integrated circuit having a central portion directly over a plurality of the first top terminal; and applying an insulation layer directly on a bottom extent of the first top distribution layer and a peripheral lead ridge lower side of the peripheral lead horizontal ridge. | 11-08-2012 |
20120280390 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH ROUTED CIRCUIT LEAD ARRAY AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: providing a terminal having a top with a depression; applying a dielectric material in the depression, the dielectric material having a gap formed therein and exposing a portion of the top therefrom; forming a trace within the gap and in direct contact with the top, the trace extending laterally over an upper surface of the dielectric material; and connecting an integrated circuit to the terminal through the trace. | 11-08-2012 |
20120280407 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH ELECTRICAL INTERFACE AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: forming an isolated contact having a contact protrusion, the contact protrusion having a lower protrusion surface, an upper protrusion surface, and a protrusion sidewall; forming a die paddle, adjacent to the isolated contact, having a die paddle protrusion, the die paddle protrusion having a lower die protrusion surface, an upper die protrusion surface, and a die protrusion sidewall; depositing a contact pad on the contact protrusion; depositing a die paddle pad on the die paddle protrusion; coupling an integrated circuit die to the contact protrusion; and molding an encapsulation on the integrated circuit die. | 11-08-2012 |
20120280408 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH FORMED INTERCONNECTS AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: providing a die paddle having an internal portion with a trench along a perimeter of the die paddle; forming an interconnect having a concave indentation and an upper portion, the upper portion, opposite the concave indentation, aligned horizontally to the internal portion; | 11-08-2012 |
20120286400 | Semiconductor Device with Optical Sensor and Method of Forming Interconnect Structure on Front and Backside of the Device - A semiconductor device includes a carrier and semiconductor die having an optically active region. The semiconductor die is mounted to the carrier to form a separation between the carrier and the semiconductor die. The semiconductor device further includes a passivation layer disposed over a surface of the semiconductor die and a glass layer disposed over a surface of the passivation layer. The passivation layer has a clear portion for passage of light to the optically active region of the semiconductor die. The semiconductor device further includes an encapsulant disposed over the carrier within the separation to form an expansion region around a periphery of the semiconductor die, a first via penetrating the expansion region, glass layer, and passivation layer, a second via penetrating the glass layer and passivation layer to expose a contact pad on the semiconductor die, and a conductive material filling the first and second vias. | 11-15-2012 |
20120326284 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH THERMAL EMISSION AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: forming a lead array having an innermost space with an innermost lead having an inner lead profile different around an inner non-horizontal side of the innermost lead; forming a middle lead having a middle lead profile the same around a lead side of the middle lead; placing an integrated circuit in the innermost space adjacent to the innermost lead; and forming a package encapsulation over the integrated circuit, the innermost lead, and the middle lead. | 12-27-2012 |
20130087902 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH THERMAL STRUCTURES AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: forming a thermal attach cluster includes: forming a heat collector having a heat dissipation surface, forming a cluster bridge, having a thermal surface, connected to the heat collector, forming a cluster pad, having an attachment surface, connected to the end of the cluster bridge opposite the heat collector; connecting an integrated circuit to the thermal attach cluster; and forming an encapsulation over the thermal attach cluster with the heat dissipation surface, the thermal surface, and the attachment surface exposed from and coplanar with the encapsulation. | 04-11-2013 |
20130099365 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH LEADFRAME LEAD ARRAY ROUTING AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: providing a leadframe with a grid lead and a support pad; connecting a redistribution layer to the grid lead, the redistribution layer over the support pad; mounting an integrated circuit over the redistribution layer; applying an encapsulation on the redistribution layer, the redistribution layer in an interior area of the leadframe and the interior area under the integrated circuit; forming a support pad residue on the bottom surface of the redistribution layer by removing the support pad under the encapsulation and the interior redistribution layer; and forming an insulation layer on the support pad residue and the grid lead. | 04-25-2013 |
20130099367 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH PLANARITY CONTROL AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: providing a leadframe having a partially removed portion including: a conductive pattern having a lower surface on a top frame surface of the leadframe, a contact protrusion and a support lead on the lower surface of the conductive pattern, the support lead for supporting the partially removed portion of the leadframe during an encapsulation process, and a contact pad on a bottom surface of the contact protrusion; mounting an integrated circuit die above the conductive pattern; applying an encapsulation on the integrated circuit die and the conductive pattern, the lower surface of the conductive pattern exposed from the encapsulation; and removing at least a portion of the leadframe to form a contact lead and expose a bottom surface of the encapsulation. | 04-25-2013 |
20130154072 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH PAD AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: forming a peripheral lead having a peripheral lead bottom side, a peripheral lead top side, a peripheral lead non-horizontal side, and a peripheral lead horizontal ridge protruding from the peripheral lead non-horizontal side; forming a first top distribution layer on the peripheral lead top side; connecting an integrated circuit to the first top distribution layer; and applying an insulation layer directly on a distribution layer bottom extent of the first top distribution layer and a peripheral lead ridge lower side of the peripheral lead horizontal ridge with a cavity in the portion of the insulation layer directly below the integrated circuit. | 06-20-2013 |
20130154080 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH LEADS AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: forming a lead; forming an interior conductive layer having an interior top side and an interior bottom side, the interior bottom side directly on the lead; mounting an integrated circuit over the lead, the integrated circuit having an inactive side and an active side; forming an encapsulation directly on the inactive side and the interior top side; and forming an insulation layer directly on the active side and a portion of the interior bottom side. | 06-20-2013 |
20130154105 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH ROUTABLE TRACE AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: providing routable traces including a first routable trace with a top plate and a second routable trace; mounting an integrated circuit partially over a second routable trace; forming an encapsulation over and around the first routable trace and the integrated circuit; forming a hole through the encapsulation to the top plate; and forming a protective coat directly on the encapsulation with the first routable trace between and in contact with the protective coat and the encapsulation. | 06-20-2013 |
20130154118 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH CONTACTS AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: forming an isolated contact having a contact protrusion; forming a die paddle, adjacent to the isolated contact, having a die paddle contour; depositing a contact pad on the contact protrusion; coupling an integrated circuit die to the contact protrusion; molding an encapsulation on the integrated circuit die; and depositing an organic filler on and between the isolated contact and the die paddle, the contact protrusion extended past the organic filler. | 06-20-2013 |
20130154119 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH TERMINALS AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: forming a lead having a lead top side; forming a lower interior conductive layer directly on the lead top side; forming an interior insulation layer directly on the lower interior conductive layer; forming an upper interior conductive layer directly on the interior insulation layer; and mounting an integrated circuit over the upper interior conductive layer. | 06-20-2013 |
20130154120 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH PACKAGE-ON-PACKAGE AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: forming a peripheral lead; forming an interior conductive layer directly on the peripheral lead; forming a vertical connector directly on the interior conductive layer, the vertical connector having a connector top side; connecting an integrated circuit to the interior conductive layer; and forming an encapsulation over the integrated circuit, the encapsulation having an encapsulation top side coplanar with the connector top side. | 06-20-2013 |
20130249065 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH ENCAPSULATION AND LEADFRAME ETCHING AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: providing a leadframe having a mounting region; applying a mounting structure in the mounting region; mounting an integrated circuit die on the mounting structure; forming an encapsulation on the integrated circuit die and having an encapsulation cavity, the encapsulation cavity shaped by the mounting structure; forming a lead having a lead protrusion from the leadframe, the lead protrusion below a horizontal plane of the integrated circuit die; and removing the mounting structure for exposing the integrated circuit die. | 09-26-2013 |
20130249068 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH EXTERNAL INTERCONNECT AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: providing a routable distribution layer on a leadframe; mounting an integrated circuit over the routable distribution layer; encapsulating with an encapsulation over the routable distribution layer; peeling the leadframe away from the routable distribution layer with a bottom distribution side of the routable distribution layer exposed from the encapsulation; and mounting an external interconnect on the routable distribution layer. | 09-26-2013 |
20130249077 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH TERMINALS AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: providing a leadframe having a mounting platform; applying an attach layer on the mounting platform; mounting an integrated circuit die on the attach layer; forming an encapsulation on the integrated circuit die and the attach layer, the mounting platform exposed from the encapsulation; and forming a terminal having a terminal protrusion from the leadframe, the terminal protrusion below a horizontal plane of the mounting platform. | 09-26-2013 |
20130249118 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH A GRID ARRAY WITH A LEADFRAME AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: forming a conductive trace having a terminal end and a circuit end; forming a terminal on the terminal end; connecting an integrated circuit die directly on the circuit end of the conductive trace, the integrated circuit die laterally offset from the terminal, the active side of the integrated circuit die facing the circuit end; and forming an insulation layer on the terminal and the integrated circuit die, the integrated circuit die covered by the insulation layer. | 09-26-2013 |
20130256861 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH ROUTABLE CIRCUITRY AND METHOD OF MANUFACTURE THEREOF - An integrated circuit packaging system, and a method of manufacture therefor, including: electrical terminals; circuitry protective material around the electrical terminals and formed to have recessed pad volumes; routable circuitry on the top surface of the circuitry protective material; and an integrated circuit die electrically connected to the electrical terminals. | 10-03-2013 |
20140011315 | Optical Semiconductor Device Having Pre-Molded Leadframe with Window and Method Therefor - A semiconductor device is made by providing a semiconductor die having an optically active area, providing a leadframe or pre-molded laminated substrate having a plurality of contact pads and a light transmitting material disposed between the contact pads, attaching the semiconductor die to the leadframe so that the optically active area is aligned with the light transmitting material to provide a light transmission path to the optically active area, and disposing an underfill material between the semiconductor die and leadframe. The light transmitting material includes an elevated area to prevent the underfill material from blocking the light transmission path. The elevated area includes a dam surrounding the light transmission path, an adhesive ring, or the light transmission path itself can be the elevated area. An adhesive ring can be disposed on the dam. A filler material can be disposed between the light transmitting material and contact pads. | 01-09-2014 |
20140165389 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH ROUTABLE GRID ARRAY LEAD FRAME - System and method of manufacturing an integrated circuit packaging system using routable grid array lead frame. Method includes providing a lead frame having top metal connector and bottom contact, and treating the top metal connector with an additive, or the bottom contact with an additive, or both. Concomitant to the treatment process, insulation cover or bottom encapsulation can be formed about the top metal connector or the bottom contact with respective openings. Upon coupling the interconnects to the lead frame the interconnects do not exceed the metal contacts by more than about 60% due to the treatment process. | 06-19-2014 |
20140167236 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH TRANSFERABLE TRACE LEAD FRAME - System and method of manufacturing an integrated circuit packaging system using transferable trace lead frame. A lead frame is provided having lower metal contacts. A masking layer can be formed on an upper surface of the lead frame for protection and shielding purposes. Routing layer and conductive lands may subsequently be formed by shaping the lead frame, along with bottom encapsulation. The masking layer may subsequently be removed for additional processing steps including connecting an integrated circuit die to the upper surface of the lead frame. | 06-19-2014 |
20140197548 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH MOLDED GRID-ARRAY MECHANISM AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: providing a lead-frame having a metal connector mounted thereon and having a peripheral mounting region; forming an insulation cover on the lead-frame and on the metal connector; connecting an integrated circuit die over the insulation cover; forming a top encapsulation on the integrated circuit die with the peripheral mounting region exposed from the top encapsulation; forming a routing layer, having a conductive land, from the lead-frame; and forming a bottom encapsulation partially encapsulating the routing layer and the insulation cover. | 07-17-2014 |
20140284791 | CORELESS INTEGRATED CIRCUIT PACKAGING SYSTEM AND METHOD OF MANUFACTURE THEREOF - A system and method for manufacturing an integrated circuit packaging system includes: forming a base substrate including: providing a sacrificial carrier: mounting a metallic sheet on the sacrificial carrier, applying a top trace to the metallic sheet, forming a conductive stud on the top trace, forming a base encapsulation over the metallic sheet, the top trace, and the conductive stud, the top trace exposed from a top surface of the base encapsulation, and removing the sacrificial carrier and the metallic sheet; mounting an integrated circuit device on the base substrate; and encapsulating the integrated circuit device and the base substrate with a top encapsulation. | 09-25-2014 |