Patent application number | Description | Published |
20080217617 | Thin Film Transistor, Wiring Board and Methods of Manufacturing the Same - A gate electrode or a gate wiring of a thin-film transistor has a four-layer structure including an adhesive base layer, a catalyst layer, a wiring metal layer, and a wiring metal anti-diffusion layer which are laminated in this order. With this structure, adhesion and flatness are improved. In this case, the adhesive base layer is formed by a resin having a structure capable of coordinating to a metal. Hence, adhesion with an insulating substrate can be improved. Further, the wiring metal anti-diffusion layer is formed on the wiring metal layer, so that diffusion of a wiring metal can be inhibited. Thus, characteristics of the thin-film transistor can be improved. | 09-11-2008 |
20080224725 | TEST CIRCUIT, WAFER, MEASURING APPARATUS, MEASURING METHOD, DEVICE MANUFACTURING METHOD AND DISPLAY APPARATUS - There is provided a wafer on which a plurality of electronic devices and circuits under test are to be formed, where each circuit under test includes a plurality of transistors under measurement provided in electrically parallel, a selecting section which sequentially selects the respective transistors under measurement, and an output section which sequentially outputs the source voltages of the transistors under measurement sequentially selected by the selecting section. | 09-18-2008 |
20080266434 | Solid-State Imaging Device, Optical Sensor and Method of Operating Solid-State Imaging Device - A solid-state imaging device and an optical sensor, which can enhance a wide dynamic range while keeping a high sensitivity with a high S/N ratio, and a method of operating a solid-state imaging device for enhancing a wide dynamic range while keeping a high sensitivity with a high S/N ratio are disclosed. An array of integrated pixels has a structure wherein each pixel comprises a photodiode PD for receiving light and generating and accumulating photoelectric charges and a storage capacitor element C | 10-30-2008 |
20080277715 | Dielectric film and formation method thereof, semiconductor device, non-volatile semiconductor memory device, and fabrication method for a semiconductor device - In a film formation method of a semiconductor device including a plurality of silicon-based transistors or capacitors, there exist hydrogen at least in a part of the silicon surface in advance, and the film formation method removes the hydrogen by exposing the silicon surface to a first inert gas plasma. Thereafter a silicon compound layer is formed on the surface of the silicon gas by generating plasma while using a mixed gas of a second inert gas and one or more gaseous molecules, such that there is formed a silicon compound layer containing at least a pat of the elements constituting the gaseous molecules, on the surface of the silicon gas. | 11-13-2008 |
20090045319 | Optical Sensor, Solid-State Imaging Device, and Operating Method of Solid-State Imaging Device - In an optical device such as an optical sensor or a solid-state imaging device having a photodiode for receiving light and producing photocharges and a transfer transistor (or an overflow gate) for transferring the photocharge, it is configured that photocharges overflowing from the photodiode in storage operation are stored into a plurality of storage capacitance elements through the transfer transistor or the overflow gate, thereby obtaining the optical device adapted to maintain a high sensitivity and a high S/N ratio and having a wide dynamic range. | 02-19-2009 |
20090058456 | MANUFACTURING SYSTEM, MANUFACTURING METHOD, MANAGING APPARATUS, MANAGING METHOD AND COMPUTER READABLE MEDIUM - There is provided a manufacturing system for manufacturing an electronic device through a plurality of manufacturing stages. The manufacturing system includes a plurality of manufacturing apparatuses performing processes corresponding to the plurality of manufacturing stages. The manufacturing system includes a manufacturing line that manufactures the electronic device, a manufacturing control section that causes the manufacturing line to manufacture a wafer having therein a test circuit including a plurality of transistors under measurement, a measuring section that measures an electrical characteristic of each of the plurality of transistors under measurement in the test circuit, an identifying section that identifies, among the plurality of manufacturing stages, a manufacturing stage in which a defect is generated, with reference to a distribution, on the wafer, of one or more transistors under measurement whose electrical characteristics do not meet a predetermined standard, and a setting changing section that changes a setting for a manufacturing apparatus that performs a process corresponding to the manufacturing stage in which the defect is generated. | 03-05-2009 |
20090081819 | METHOD AND APPARATUS FOR MANAGING MANUFACTURING EQUIPMENT, METHOD FOR MANUFACTURING DEVICE THEREBY - Provided is a method for managing manufacturing apparatuses used in a managed production line including a plurality of manufacturing processes for manufacturing an electronic device, each of the apparatuses being used in each of the processes, the method including: acquiring a property of a reference device manufactured in a predetermined reference production line including the manufacturing processes to be performed; performing at least one of the manufacturing processes in the managed production line, performing the other manufacturing processes in the reference production line, and manufacturing a comparison device; measuring a property of the comparison device; comparing the measured properties between the reference and the comparison devices; and judging whether the manufacturing apparatus used in the at least one manufacturing process is defective or not, based on a property difference between the reference and the comparison devices. | 03-26-2009 |
20090140305 | IMAGING DEVICE - A solid-state imaging device, a line sensor and an optical sensor for enhancing a wide dynamic range while keeping high sensitivity with a high S/N ratio, and a method of operating a solid-state imaging device for enhancing a wide dynamic range while keeping high sensitivity with a high S/N ratio are provided. The solid-state imaging device comprises an integrated array of a plurality of pixels, each of which comprises a photodiode PD for receiving light and generating photoelectric charges, a transfer transistor Tr | 06-04-2009 |
20090225210 | IMAGING DEVICE - A solid-state imaging device, a line sensor and an optical sensor for enhancing a wide dynamic range while keeping high sensitivity with a high S/N ratio, and a method of operating a solid-state imaging device for enhancing a wide dynamic range while keeping high sensitivity with a high S/N ratio are provided. The solid-state imaging device comprises an integrated array of a plurality of pixels, each of which comprises a photodiode PD for receiving light and generating photoelectric charges, a transfer transistor Tr | 09-10-2009 |
20100038722 | MIS TRANSISTOR AND CMOS TRANSISTOR - A MIS transistor, formed on a semiconductor substrate, assumed to comprise a semiconductor substrate ( | 02-18-2010 |
20100176423 | SOLID-STATE IMAGE SENSOR AND METHOD FOR PRODUCING THE SAME - A floating diffusion ( | 07-15-2010 |
20100182470 | SOLID-STATE IMAGE SENSOR AND IMAGING DEVICE - A pixel output line ( | 07-22-2010 |
20100188538 | SOLID-STATE IMAGE SENSOR AND DRIVE METHOD FOR THE SAME - An independent pixel output line ( | 07-29-2010 |
20100208115 | SOLID-STATE IMAGE SENSOR - A pixel area with a two-dimensional array of pixels ( | 08-19-2010 |
20100308839 | ELECTRONIC DEVICE IDENTIFYING METHOD - An electronic device that includes an actual operation circuit that operates during an actual operation of the electronic device, a second test circuit and a third test circuit that operate during a test of the electronic device, and a power supply section. The power supply section, during the actual operation of the electronic device, does not apply a power supply voltage to the second test circuit and applies power supply voltages to the actual operation circuit and the third test circuit. The power supply section, to obtain identification of the electronic device, applies a power supply voltage to the second test circuit. | 12-09-2010 |
20110018577 | TEST CIRCUIT, WAFER, MEASURING APPARATUS, MEASURING METHOD, DEVICE MANUFACTURING METHOD AND DISPLAY APPARATUS - There is provided a wafer on which a plurality of electronic devices and circuits under test are to be formed, where each circuit under test includes a plurality of transistors under measurement provided in electrically parallel, a selecting section which sequentially selects the respective transistors under measurement, and an output section which sequentially outputs the source voltages of the transistors under measurement sequentially selected by the selecting section. | 01-27-2011 |
20110110052 | MULTILAYER WIRING BOARD - A multilayer wiring board | 05-12-2011 |
20110209567 | DISPLAY APPARATUS - There is provided a wafer on which a plurality of electronic devices and circuits under test are to be formed, where each circuit under test includes a plurality of transistors under measurement provided in electrically parallel, a selecting section which sequentially selects the respective transistors under measurement, and an output section which sequentially outputs the source voltages of the transistors under measurement sequentially selected by the selecting section. | 09-01-2011 |
20110212552 | DEVICE MANUFACTURING METHOD - There is provided a wafer on which a plurality of electronic devices and circuits under test are to be formed, where each circuit under test includes a plurality of transistors under measurement provided in electrically parallel, a selecting section which sequentially selects the respective transistors under measurement, and an output section which sequentially outputs the source voltages of the transistors under measurement sequentially selected by the selecting section. | 09-01-2011 |
20120208375 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - In a semiconductor device formed on a silicon surface which has a substantial (110) crystal plane orientation, the silicon surface is flattened so that an arithmetical mean deviation of surface Ra is not greater than 0.15 nm, preferably, 0.09 nm, which enables to manufacture an n-MOS transistor of a high mobility. Such a flattened silicon surface is obtained by repeating a deposition process of a self-sacrifice oxide film in an oxygen radical atmosphere and a removing process of the self-sacrifice oxide film, by cleaning the silicon surface in deaerated H | 08-16-2012 |
20140312399 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A gate insulating film of a conventional semiconductor device is subjected to dielectric breakdown at a low electric field strength and thus its service life is short. This is because since the size of the asperity of at least one of a semiconductor layer-side interface and an electrode-side interface is large and, an electric field applied to the gate insulating film is locally concentrated and has a variation in its strength. This problem is solved by specifying the sizes of the asperities of both interfaces of the gate insulating film. | 10-23-2014 |
20140327800 | ANALOG-TO-DIGITAL CONVERTER AND SOLID-STATE IMAGING DEVICE - To obtain accurate digital data while using a successive approximation system when performing analog-to-digital conversion processing in a plurality of steps, an AD converter includes: a signal generation unit that generates a ramp voltage based on a count signal; a signal conversion unit including a circuit that holds an input signal voltage, a successive approximation capacitance group that outputs bias voltages according to a connection combination of capacitances having different capacitance values, and a unit that compares one of the ramp voltage and the bias voltage with the signal voltage; and a control unit generating a digital signal of the signal voltage based on a comparison result of the bias voltage and the comparison result of the ramp voltage while acquiring data for calibration of the capacitance group based on the connection combination and the ramp voltage. | 11-06-2014 |
20150029375 | SOLID-STATE IMAGE PICKUP APPARATUS - A solid-state image pickup apparatus including: two-dimensionally arrayed unit pixels, each including a PD performing optical-electrical conversion of an incident light; an FD and two output terminals provided for each of pixel groups, each including one or more unit pixels, the two output terminals being capable of outputting a noise signal and a signal-noise sum signal separately; first and second transfer lines to which the output terminals are connected in common and which are capable of holding noise signal voltage and signal-noise sum signal voltage, respectively; first switches arranged between the output terminals and the first transfer lines; second switches arranged between the output terminals and the second transfer lines; third and fourth switches provided for the transfer lines, respectively; and third and fourth transfer lines to which the transfer lines are connected in parallel via third and fourth switches, respectively. | 01-29-2015 |
20150029376 | SOLID-STATE IMAGE PICKUP APPARATUS - A solid-state image pickup apparatus includes: two-dimensionally arrayed unit pixels, each including a PD performing optical-electrical conversion of an incident light; an FD and an output terminal provided for each of pixel groups, each including one or more pixels, the terminal being capable of outputting a noise signal and a signal-noise sum signal separately; first lines to which the terminals are connected in common and which are capable of holding voltages based on signals outputted from the terminals; second lines provided in parallel with the first lines and capable of holding a voltage; inter-transfer-line capacitive elements connecting the second lines and the first lines; a reset switch resetting each of the second lines to a reset voltage; a readout switch provided for each of the second lines; and a third line to which the second lines are connected in parallel via the readout switches, respectively. | 01-29-2015 |