Patent application number | Description | Published |
20090138658 | Cache memory system for a data processing apparatus - A data processing apparatus is provided having a cache memory comprising a data storage array and a tag array and a cache controller coupled to the cache memory responsive to a cache access request from processing circuitry to perform cache look ups. The cache memory is arranged such that it has a first memory cell group configured to operate in a first voltage domain and a second memory cell group configured to operate in a second voltage domain that is different from the first voltage domain. A corresponding data processing method is also provided. | 05-28-2009 |
20100023917 | TOOL FOR MODIFYING MASK DESIGN LAYOUT - An embodiment of the invention provides a tool for modifying a mask design layout to be printed. The tool is executed by a computer system, and includes code for establishing a first level of correction for a mask design layout for a predetermined parametric yield without cost of correction to area of the mask design layout. The tool also includes code for correcting the mask design layout at said first level of correction based on a correction algorithm, the correction algorithm selecting a cell of the mask design layout having an edge placement error (EPE) for each gate feature in the cell. The correction algorithm selects the cell without loss to parametric yield as established by the predetermined parametric yield. | 01-28-2010 |
20100327842 | REFERENCE VOLTAGE GENERATOR HAVING A TWO TRANSISTOR DESIGN - An improved voltage reference generator is provided. The voltage reference generator comprises: a first transistor having a gate electrode biased to place the first transistor in a weak inversion mode; and a second transistor connected in series with said first transistor and having a gate electrode biased to place the second transistor in a weak inversion mode, where the threshold voltage of the first transistor is smaller than the threshold voltage of the second transistor and the gate electrode of the second transistor is electrically coupled to a drain electrode of the second transistor and the source electrode of the first transistor to form an output for a reference voltage. | 12-30-2010 |
20120293212 | LOW POWER REFERENCE CURRENT GENERATOR WITH TUNABLE TEMPERATURE SENSITIVITY - An improved reference current generator is provided. A voltage difference generator generates two voltages that are separated by a relatively small electrical potential. The two closely separated voltages are applied across a resistive element with relatively large impedance value resulting in a small and stable reference current. The result is a power efficient, temperature compensated reference current generator. | 11-22-2012 |
20150085406 | Electrostatic Discharge Clamp Circuit For Ultra-Low Power Applications - An electrostatic discharge clamp circuit is provided for low power applications. The clamp circuit includes: a detection circuit, a bias circuit and a shunting circuit having at least one shunt transistor. The detection circuit is configured to detect an occurrence of an electrostatic charge on a power supply node and trigger discharge of the electrostatic charge through the shunting circuit. The bias circuit is coupled between the detection circuit and the shunting circuit and applies a bias voltage to the gate terminal of the shunt transistor. During an electrostatic discharge event, the bias circuit is configured to generate a bias voltage that is substantially equal to the supply voltage; whereas, during the absence of an electrostatic discharge event, the bias circuit is configured to generate a bias voltage that is substantially half of the supply voltage. | 03-26-2015 |
Patent application number | Description | Published |
20100211719 | Crossbar circuitry and method of operation of such crossbar circuitry - Crossbar circuitry, and a method of operation of such crossbar circuitry, are provided. The crossbar circuitry has an array of data input paths and data output paths where the data output paths are transverse to the data input paths. At each intersection between a data input path and a data output path, a crossbar cell is provided that comprises a storage circuit programmable to store a routing value, and a transmission circuit. In a transmission mode of operation the transmission circuit is responsive to the routing value indicating that the data input path should be coupled to the data output path to detect the data input along the data input path, and to output an indication of that data on the data output path at the associated intersection. Control circuitry is used to issue control signals to the crossbar cells, and during a configuration mode of operation the control circuitry re-utilises at least one of the data output paths to program the storage circuitry of one or more of the crossbar cells. Such a construction of crossbar circuitry provides a very regular design, with uniform delay across all paths, and which requires significantly less control lines than typical prior art crossbar designs. Such crossbar circuitry is readily scalable to form large crossbars. | 08-19-2010 |
20100211720 | Crossbar circuitry and method of operation of such crossbar circuitry - Crossbar circuitry, and a method of operation of such crossbar circuitry, are provided. The crossbar circuitry has an array of data input paths and data output paths where the data output paths are transverse to the data input paths. At each intersection between a data input path and a data output path, a crossbar cell is provided that comprises a configuration storage circuit programmable to store a routing value, a transmission circuit, and an arbitration circuit. In a transmission mode of operation, the transmission circuit is responsive to the routing value being a first value, indicating that the data input path should be coupled to the data output path, to detect the data input along the data input path, and to output an indication of that data on the data output path at the associated intersection. In an arbitration mode of operation, the arbitration circuitry is operable in the presence of an asserted transmission request from the associated source circuit to operate in combination with the arbitration circuits of other crossbar cells associated with the same data output path to re-use the bit lines of the data output path to detect the presence of multiple asserted transmission requests for the same data output path. In the event of such multiple asserted transmission requests, the arbitration circuitry operates in combination with the other arbitration circuits to implement a predetermined priority scheme to cause the configuration storage circuit of only one crossbar cell associated with the same data output path to have its routing value programmed to the first value, thereby resolving conflict between the multiple asserted transmission requests according to the predetermined priority scheme. Such a construction of crossbar circuitry enables a very efficient resolution of conflicts to be performed, whilst providing a very regular design, with uniform delay across all paths, and which requires significantly less control lines that typical prior art crossbar designs. Such crossbar circuitry is readily scalable to form large crossbars. | 08-19-2010 |
20100217562 | Operating parameter control of an apparatus for processing data - An apparatus for processing data | 08-26-2010 |
20100220538 | Integrated circuit memory power supply - An integrated circuit memory | 09-02-2010 |
20100220542 | Integrated circuit memory access mechanisms - A memory cell | 09-02-2010 |
20110138098 | Crossbar circuitry for applying an adaptive priority scheme and method of operation of such crossbar circuitry - Crossbar circuitry has an array of data input and output paths where the data output paths are transverse to the data input paths. At each intersection between a data input path and a data output path, a crossbar cell is provided which includes a configuration storage circuit programmable to store a routing value, a transmission circuit, and an arbitration circuit. In a transmission mode of operation, the transmission circuit is responsive to the routing value being a first value, indicating that the data input path should be coupled to the data output path, to detect the data input along the data input path, and to output an indication of that data on the data output path at the associated intersection. In an arbitration mode of operation, the arbitration circuitry is operable to selectively modify the voltage on said plurality of bit lines in order to apply an adaptive priority scheme. | 06-09-2011 |
20110202786 | Stalling synchronisation circuits in response to a late data signal - A data processing circuitry for processing data is disclosed. The data processing circuitry comprises: a plurality of synchronisation circuits for capturing and transmitting the data in response to a clock signal and a plurality of combinational circuits arranged between the synchronisation circuits for processing the data, the plurality of synchronisation circuits being arranged in at least two groups; an error detecting circuit for determining if the data input to one of the plurality of synchronisation circuits is stable during a predetermined time and for signalling an error if the data input is not stable, the predetermined time being less than a half cycle of the clock signal; control circuitry responsive to said error detecting circuit signalling said error to transmit a control signal to at least one of said groups of synchronisation circuits that contains a subsequent synchronisation circuit that said synchronisation circuit with said unstable input is configured to transmit said data to; each of said group of synchronisation circuits being configured to respond to receipt of said control signal to stall for a clock cycle and to transmit a stall signal to at least one further group of synchronisation circuits that said group of synchronisation circuits is configured to transmit data to or receive data from; each of said group of synchronisation circuits being configured to respond to receipt of said stall signal provided they have not stalled in a preceding clock cycle to stall for a clock cycle and to transmit a stall signal to said at least one further group of synchronisation circuits. | 08-18-2011 |
20120047310 | Crossbar circuitry for applying a pre-selection prior to arbitration between transmission requests and method of operation of such crossbar circuitry - Crossbar circuitry has data input and output paths, and at each intersection between a data input and output path, a crossbar cell is provided. A transmission circuit is responsive to a stored routing value to couple a data input path to a selected data output path. Pre-selection circuitry cooperates with the pre-selection circuits of other crossbar cells on the same data output path to use the bit lines of the data output path to compare quality-of-service values associated with multiple asserted transmission requests and to determine a subset thereof which have a highest value of the quality-of-service values. Arbitration circuitry implements a predetermined priority scheme to choose from that subset of requests and to cause the configuration storage circuit of only one crossbar cell associated with the same data output path to have its routing value programmed to the first value, thereby resolving conflict between multiple asserted transmission requests. | 02-23-2012 |
20130205056 | APPARATUS AND METHOD FOR TRANSFERRING A DATA SIGNAL PROPAGATED ALONG A BIDIRECTIONAL COMMUNICATION PATH WITHIN A DATA PROCESSING APPARATUS - An apparatus including a first circuit and a second circuit connected in parallel to the bidirectional communication path, and one of the first and second circuits being an active circuit monitoring a value of the data signal on the bidirectional communication path whilst the other of the first and second circuits being a passive circuit that is not monitoring the value of the data signal. The active circuit initially starts in a low gain state, but on detection of a transition by transition detection circuitry, it enters a high gain state where the switch circuitry disconnects the transition detection circuitry from the bidirectional communication path, and the drive circuitry is activated in order to drive the data signal on the bidirectional communication path to the opposite value. Once the data signal has been driven to the opposite value, the active circuit and the passive circuits switch states. | 08-08-2013 |
20140306744 | STATIC SIGNAL VALUE STORAGE CIRCUITRY USING A SINGLE CLOCK SIGNAL - Signal value storage circuitry | 10-16-2014 |
20150015305 | DYNAMIC CIRCUITRY USING PULSE AMPLIFICATION TO REDUCE METASTABILITY - Synchronisation circuitry | 01-15-2015 |
Patent application number | Description | Published |
20100265735 | DISPLAY ASSEMBLY WITH LIGHT PIPE HAVING CENTRAL COMPARTMENT FOR LIGHT SOURCE - A display assembly includes a light pipe that has a front face adapted for emitting light to illuminate a display. The light pipe defines a compartment for receiving a light source. A light shield is disposed overlying the compartment. Channel segments are formed in the rear face and are symmetrical about the compartment. Light from the light source is extracted through the front face to create glow regions about the light shield, over the channel segments, and adjacent the edges of the light pipe. This results in symmetrically uniform illumination of the display while utilizing a single central light source. | 10-21-2010 |
20130120825 | HEADS-UP DISPLAY SYSTEM UTILIZING CONTROLLED REFLECTIONS FROM A DASHBOARD SURFACE - A heads-up display system is configured for use in a vehicle. The system includes a standard vehicle window (i.e. no special coatings), an image projector, and a vehicle dashboard equipped with a faceted reflective surface. The image projector is configured to project an image onto the faceted reflective surface. The faceted reflective surface is configured to reflect the image from the image projector onto a window surface of the standard vehicle window. The window surface is oriented to reflect the image from the faceted reflective surface toward an occupant. The faceted reflective surface may be disposed within a plurality of troughs separated by a plurality of diffuse reflecting partitions. The plurality of troughs may be configured to shield the occupant from extraneous reflections. The faceted reflective surface may include a plurality of electrically controlled facets. The plurality of electrically controlled reflective facets may be an array of electrowetting cells. | 05-16-2013 |
20130120850 | HEADS-UP DISPLAY SYSTEM - A heads-up display system suitable for use in a vehicle. The system includes a projector configured to project a projected image. A faceted reflector is included to overlay a dashboard area of the vehicle and define an array of reflective facets. Each facet is configured to reflect cooperatively a portion of the projected image to form a reflected image directed toward a windshield of the vehicle. A light diffusive layer is included to diffuse the reflected portion of the projected image such that the reflected image can be seen by an occupant of the vehicle as a reflection in the windshield. A light control film interposed between the windshield and the faceted reflector is included to propagate preferentially the projected image and thereby reduce the occurrence of ambient light washout of the reflected image being displayed. | 05-16-2013 |
20140147087 | CONTOURED DISPLAY - A contoured display that includes a faceplate configured to propagate an image in a collimated manner from an interface surface of the faceplate configured to receive the image from a display device to a display surface of the faceplate. The display surface is contoured to provide a three-dimensional (3D) contoured surface that provides designers with artistic freedom when designing a display shape, and a convenient way to contour a display surface to reduce the effects of glare on the display surface. | 05-29-2014 |