Patent application number | Description | Published |
20130167425 | LOCKING ADJUSTMENT DEVICE - A locking adjustment device for changing an adjustable setting of a device such as a riflescope locks in a baseline position to provide expedient feedback regarding an adjustment position of the adjustable setting. The device includes a guideway extending around an axis and a knob mountable over the guideway for rotation about the axis. The guideway includes a notch and a curved slide surface sized to slidably receive a guide tab carried by the knob. The guide tab is biased so as to urge at least a portion of the guide tab into the notch when the knob is rotated to a locked position, thereby preventing inadvertent rotation of the knob from the locked position. A button carried by the knob is depressible to urge the guide tab out of the notch and thereby allow the knob to be manually rotated away from the locked position. | 07-04-2013 |
20130174490 | HINGED LID FOR BATTERY COMPARTMENT IN A MANUALLY ROTATABLE ADJUSTMENT KNOB - A rotatable adjustment knob has a knob body mountable to an optical or electronic device for rotation about an axis extending outwardly from the device. The knob body has an opening into a battery compartment sized to receive a battery. A lid is pivotably attached to the knob body for movement between a closed position in which the lid covers the opening, and an open position in which the lid is pivoted away from the opening to provide access to the battery compartment. The lid remains attached to the knob body while in both the open and closed positions for rotation with the knob body about the axis. A resilient seal confronts the knob body and the lid while the lid is in the closed position to thereby seal the opening and the battery compartment. A latch releasably retains the lid in the closed position. | 07-11-2013 |
20140137458 | RIFLESCOPE ADJUSTMENT KNOB WITH INTERCHANGEABLE ADJUSTMENT INDICATOR RING - An adjustment device having a rotatable knob for changing an adjustable setting of an aiming device, such as a riflescope. The knob includes a removable indicator ring slidable onto the knob and bearing a scale to provide visual feedback to a shooter regarding an adjustment position of the adjustable setting. The knob further carries a releasable latch that may extend radially outward relative to the knob to retain the indicator ring on the knob when the latch is in the latched position. When the shooter desires to remove and replace the indicator ring, such as in response to a change in shooting conditions, the latch may be released to an unlatched position to allow the indicator ring to be moved off of the knob. The shooter may thereafter insert a replacement indicator ring on the knob. | 05-22-2014 |
20140259853 | DUAL FIELD OPTICAL AIMING SYSTEM FOR PROJECTILE WEAPONS - A system for aiming a projectile weapon includes a telescopic sight for use with a second sighting device, such as a reflex sight or other non-magnifying sight. The telescopic sight has an eye point spaced apart rearwardly from its eyepiece and positioned at a vertical plane containing a line of initial trajectory of the weapon to which the aiming system is mounted so that a line parallel to the line of initial trajectory does not intersect the eyepiece. The location of the eye point facilitates concurrent use of a second sighting device at a normal mounting height and viewable past the eyepiece, thereby allowing the viewer to change views between the telescopic sight and the second sighting device with little eye movement and essentially no head movement. | 09-18-2014 |
20140352487 | RIFLESCOPE ADJUSTMENT KNOB WITH INTERCHANGEABLE ADJUSTMENT INDICATOR RING - An adjustment device having a rotatable knob for changing an adjustable setting of an aiming device, such as a riflescope. The knob includes a removable indicator ring slidable onto the knob and bearing a scale to provide visual feedback to a shooter regarding an adjustment position of the adjustable setting. The knob further carries a releasable latch that may extend radially outward relative to the knob to retain the indicator ring on the knob when the latch is in the latched position. When the shooter desires to remove and replace the indicator ring, such as in response to a change in shooting conditions, the latch may be released to an unlatched position to allow the indicator ring to be moved off of the knob. The shooter may thereafter insert a replacement indicator ring on the knob. | 12-04-2014 |
Patent application number | Description | Published |
20110142228 | APPARATUS AND METHOD FOR EMPLOYING CONFIGURABLE HASH ALGORITHMS - A method for performing hash operations including: receiving a hash instruction that is part of an application program, where the hash instruction prescribes one of the hash operations and one of a plurality of hash algorithms; translating the hash instruction into a first plurality of micro instructions and a second plurality of micro instructions; and via a hash unit disposed within execution logic, executing the one of the hash operations. The executing includes first executing the first plurality of micro instructions within the hash unit to produce output data; second executing the second plurality of micro instructions within an x86 integer unit in parallel with the first executing to test a bit in a flags register, to update text pointer registers, and to process interrupts during execution of the hash operation; and storing a corresponding intermediate hash value to memory prior to allowing a pending interrupt to proceed. | 06-16-2011 |
20110142229 | APPARATUS AND METHOD FOR PERFORMING TRANSPARENT HASH FUNCTIONS - A method for performing hash operations including: receiving a hash instruction that prescribes one of the hash operations and one of a plurality of hash algorithms; translating the hash instruction into a first plurality of micro instructions and a second plurality of micro instructions; and via a hash unit, executing the one of the hash operations. The executing includes indicating whether the one of the hash operations has been interrupted by an interrupting event; first executing the first plurality of micro instructions within the hash unit to produce output data; second executing the second plurality of micro instructions within an x86 integer unit in parallel with the first executing to test a bit in a flags register, to update text pointer registers, and to process interrupts during execution of the hash operation; and storing a corresponding intermediate hash value to memory prior to allowing a pending interrupt to proceed. | 06-16-2011 |
20110202775 | ATOMIC HASH INSTRUCTION - A method for performing a hash operation, including providing an atomic hash instruction that directs a microprocessor to perform a the hash operation and to indicate whether the hash operation has been interrupted by an interrupting event; translating the atomic hash instruction into first and second micro instructions; via a hash unit, first executing the first micro instructions to accomplish the hash operation according to the hash mode; and via an integer unit, second executing the second micro instructions in parallel with the first executing to test a bit in a flags register, to update text pointer registers, and to process interrupts during execution of the hash operation. The atomic hash instruction has an opcode field, configured to prescribe the hash operation, and a hash mode field, configured to prescribe that the microprocessor accomplish the hash operation according to a one of a plurality of hash modes. | 08-18-2011 |
20110296202 | SWITCH KEY INSTRUCTION IN A MICROPROCESSOR THAT FETCHES AND DECRYPTS ENCRYPTED INSTRUCTIONS - A fetch unit fetches a sequence of blocks of encrypted instructions of an encrypted program from an instruction cache at a corresponding sequence of fetch address values. While fetching each block of the sequence, the fetch unit generates a decryption key as a function of key values and the corresponding fetch address value, and decrypts the encrypted instructions using the generated decryption key by XORing them together. A switch key instruction instructs the microprocessor to update the key values in the fetch unit while the fetch unit is fetching the sequence of blocks. The fetch unit inherently provides an effective decryption key length that depends upon the function and amount of key values used. Including one or more switch key instructions within the encrypted program increases the effective decryption key length up to the encrypted program length. | 12-01-2011 |
20110296203 | BRANCH AND SWITCH KEY INSTRUCTION IN A MICROPROCESSOR THAT FETCHES AND DECRYPTS ENCRYPTED INSTRUCTIONS - A microprocessor includes a fetch unit that fetches and decrypts an (atomic) branch and switch key instruction using first decryption key data. If the branch direction is not taken, the fetch unit fetches and decrypts the next sequential instruction after the branch and switch key instruction using the first decryption key data. If the direction is taken, the fetch unit fetches and decrypts a target instruction of the branch and switch key instruction using second decryption key data that is different from the first decryption key data. The instruction points to the decryption key data; alternatively, the microprocessor consults a mapping of target address ranges to decryption key data. An encryption program replaces conventional inter-program-chunk branch instructions with branch and switch key instructions before encrypting the program using information that divides the program into a sequence of chunks each chunk being a sequence of instructions and having distinct associated encryption key data. | 12-01-2011 |
20110296204 | MICROPROCESSOR THAT FACILITATES TASK SWITCHING BETWEEN ENCRYPTED AND UNENCRYPTED PROGRAMS - A microprocessor includes an architected register having a bit (may be x86 EFLAGS register reserved bit) set by the microprocessor. A fetch unit fetches encrypted instructions from an instruction cache and decrypts them (via XOR) prior to executing them, in response to the microprocessor setting the bit. The microprocessor saves the bit value to a stack in memory and then clears the bit in response to receiving an interrupt. The fetch unit fetches unencrypted instructions from the instruction cache and executes them without decrypting them after the microprocessor clears the bit. The microprocessor restores the saved value from the stack in memory to the bit in the architected register (and in one embodiment, also restores decryption key values) in response to executing a return from interrupt instruction. The fetch unit resumes fetching and decrypting the encrypted instructions in response to determining that the restored value of the bit is set. | 12-01-2011 |
20110296205 | MICROPROCESSOR THAT FACILITATES TASK SWITCHING BETWEEN MULTIPLE ENCRYPTED PROGRAMS HAVING DIFFERENT ASSOCIATED DECRYPTION KEY VALUES - A microprocessor includes a storage element having a plurality of locations each storing decryption key data associated with an encrypted program. A control register field (may be x86 EFLAGS register reserved field) specifies a storage element location associated with a currently executing encrypted program. The microprocessor restores from memory to the control register a previously saved value of the field in response to executing a return from interrupt instruction. A fetch unit fetches encrypted instructions of the currently executing encrypted program and decrypts them using the decryption key data stored the storage element location specified by the restored field value. A kill bit associated with each storage element location may be employed if the location is clobbered because more encrypted programs are multitasked than available locations in the storage element, in which case an exception is generated to re-load the clobbered decryption key data in response to the return from interrupt instruction. | 12-01-2011 |
20110296206 | BRANCH TARGET ADDRESS CACHE FOR PREDICTING INSTRUCTION DECRYPTION KEYS IN A MICROPROCESSOR THAT FETCHES AND DECRYPTS ENCRYPTED INSTRUCTIONS - A branch target address cache (BTAC) caches history information associated with branch and switch key instructions previously executed by a microprocessor. The history information includes a target address and an identifier (index into a register file) for identifying key values associated with each of the previous branch and switch key instructions. A fetch unit receives from the BTAC a prediction that the fetch unit fetched a previous branch and switch key instruction and receives the target address and identifier associated with the fetched branch and switch key instruction. The fetch unit also fetches encrypted instruction data at the associated target address and decrypts (via XOR) the fetched encrypted instruction data based on the key values identified by the identifier, in response to receiving the prediction. If the BTAC predicts correctly, a pipeline flush normally associated with the branch and switch key instruction is avoided. | 12-01-2011 |
20120096282 | MICROPROCESSOR THAT FETCHES AND DECRYPTS ENCRYPTED INSTRUCTIONS IN SAME TIME AS PLAIN TEXT INSTRUCTIONS - A fetch unit (a) fetches a block of instruction data from an instruction cache of the microprocessor; (b) performs an XOR on the block with a data entity to generate plain text instruction data; and (c) provides the plain text instruction data to an instruction decode unit. In a first instance the block comprises encrypted instruction data and the data entity is a decryption key. In a second instance the block comprises unencrypted instruction data and the data entity is Boolean zeroes. The time required to perform (a), (b), and (c) is the same in the first and second instances regardless of whether the block is encrypted or unencrypted. A decryption key generator selects first and second keys from a plurality of keys, rotates the first key, and adds/subtracts the rotated first key to/from the second key, all based on portions of the fetch address, to generate the decryption key. | 04-19-2012 |
20140195820 | APPARATUS FOR GENERATING A DECRYPTION KEY FOR USE TO DECRYPT A BLOCK OF ENCRYPTED INSTRUCTION DATA BEING FETCHED FROM AN INSTRUCTION CACHE IN A MICROPROCESSOR - An apparatus for generating a decryption key for use to decrypt a block of encrypted instruction data being fetched from an instruction cache in a microprocessor at a fetch address includes a first multiplexer that selects a first key value from a plurality of key values based on a first portion of the fetch address. A second multiplexer selects a second key value from the plurality of key values based on the first portion of the fetch address. A rotater rotates the first key value based on a second portion of the fetch address. An arithmetic unit selectively adds or subtracts the rotated first key value to or from the second key value based on a third portion of the fetch address to generate the decryption key. | 07-10-2014 |
20140195821 | METHOD FOR ENCRYPTING A PROGRAM FOR SUBSEQUENT EXECUTION BY A MICROPROCESSOR CONFIGURED TO DECRYPT AND EXECUTE THE ENCRYPTED PROGRAM - A method for encrypting a program for subsequent execution by a microprocessor configured to decrypt and execute the encrypted program includes receiving an object file specifying an unencrypted program that includes conventional branch instructions whose target address may be determined pre-run time. The method also includes analyzing the program to obtain chunk information that divides the program into a sequence of chunks each comprising a sequence of instructions and that includes encryption key data associated with each of the chunks. The encryption key data associated with each of the chunks is distinct. The method also includes replacing each of the conventional branch instructions that specifies a target address that is within a different chunk than the chunk in which the conventional branch instruction resides with a branch and switch key instruction. The method also includes encrypting the program based on the chunk information. | 07-10-2014 |
20140195822 | MICROPROCESSOR THAT SECURELY DECRYPTS AND EXECUTES ENCRYPTED INSTRUCTIONS - A microprocessor is provided with a method for decrypting encrypted instruction data into plain text instruction data and securely executing the same. The microprocessor includes a master key register file comprising a plurality of master keys. Selection logic circuitry in the microprocessor selects a combination of at least two of the plurality of master keys. Key expansion circuitry in the microprocessor performs mathematical operations on the selected master keys to generate a decryption key having a long effective key length. Instruction decryption circuitry performs an efficient mathematical operation on the encrypted instruction data and the decryption key to decrypt the encrypted instruction data into plain text instruction data. | 07-10-2014 |
20140195823 | MICROPROCESSOR THAT FACILITATES TASK SWITCHING BETWEEN ENCRYPTED AND UNENCRYPTED PROGRAMS - A microprocessor includes an architected register having a bit. The microprocessor sets the bit. The microprocessor also includes a fetch unit that fetches encrypted instructions from an instruction cache and decrypts them prior to executing them, in response to the microprocessor setting the bit. The microprocessor saves the value of the bit to a stack in memory and then clears the bit, in response to receiving an interrupt. The fetch unit fetches unencrypted instructions from the instruction cache and executes them without decrypting them, after the microprocessor clears the bit. The microprocessor restores the saved value from the stack in memory to the bit in the architected register, in response to executing a return from interrupt instruction. The fetch unit resumes fetching and decrypting the encrypted instructions, in response to determining that the restored value of the bit is set. | 07-10-2014 |
Patent application number | Description | Published |
20110011179 | Moister sensor - A moister sensor, for measuring moister in a building without leaving visible scars to the building surface, is provided. The moister sensor includes a flexible carrier carrying an antenna for receiving EM-radiation between 9 kHz and 11 MHz and a resonant circuit including a moister reactive element. The moister reactive element includes a hygroscopic electrolyte arranged between a first and a second electrode, wherein the electrolyte in the presence of moister forms mobile ions and provides a complex impedance at least in response to the alternating voltage, which complex impedance varies with the moister content of the electrolyte. | 01-20-2011 |
20130270533 | ORGANIC FIELD-EFFECT TRANSISTOR DEVICE - The invention relates to a organic field effect transistor device comprising: an organic semiconductor layer; a source electrode arranged in electronic contact with the said organic semiconductor; a drain electrode arranged in electronic contact with the said organic semiconductor; a gate electrode; an electrolyte layer arranged between said gate electrode and said organic semiconductor layer; wherein the organic semiconductor layer comprises a semiconducting polymeric material comprising one or more blocks of conjugated polymer combined with one or more blocks of copolymer; preferably an amphiphilic copolymer. Also a method of producing the device, and a polyanionic polymer is provided by the invention. | 10-17-2013 |
20130276850 | THERMOELECTRIC DEVICE - The present invention provides thermoelectric device comprising a first electrode, a second electrode, a first electrolyte composition capable of transporting cations, a second electrolyte composition capable of transporting anions and a connector comprising mobile cations and mobile anions, wherein the first electrolyte composition is connected to said first electrode by being in ionic contact and the second electrolyte composition is connected to said second electrode by being in ionic contact and said connector is in ionic contact with said first and said second electrolyte composition, such that an applied temperature difference over said electrolyte compositions or an applied voltage over said electrodes facilitate transport of ions to and/or from said electrodes via said electrolyte compositions. There is also provided a method for generating electric current and a method for generating a temperature difference. | 10-24-2013 |
20130276851 | THERMOELECTRIC DEVICE - The present invention provides a thermoelectric device comprising a first electrode, a second electrode, and conducting composition capable of conducting ions, wherein the first and second electrodes are ionically coupled via said conducting composition such that an applied temperature difference over said conducting composition or an applied voltage over said electrodes facilitate transport of ions to and/or from said electrodes via said conducting composition, and wherein said conducting composition capable of conducting ions comprises a polymeric electrolyte. There is also provided a method for generating electric current and a method for generating a temperature difference. | 10-24-2013 |
20140264515 | FERROELECTRIC FIELD-EFFECT TRANSISTOR - A ferroelectric field-effect transistor device includes: a semiconductor layer; a ferroelectric layer; and an ion conductor layer arranged between the semiconductor layer and the ferroelectric layer and in contact with the semiconductor layer. Methods for producing the ferroelectric field-effect transistor device and using the ferroelectric field-effect transistor device in non-volatile memory devices are also disclosed. | 09-18-2014 |