Patent application number | Description | Published |
20090137572 | 2-substituted-4-heteroaryl-pyrimidines useful for the treatment of proliferative disorders - The present invention relates to selected substituted pyrimidines their preparation, pharmaceutical compositions containing them and their use as inhibitors of one or more protein kinases, and hence their use in the treatment of proliferative disorders, viral disorders and/or other disorders. | 05-28-2009 |
20090215805 | 4-Heteroaryl Pyrimidine Derivatives and use thereof as Protein Kinase Inhibitors - The present invention relates to compounds of formula (I) or formula (II), or pharmaceutically acceptable salts thereof. Further aspects relate to pharmaceutical compositions comprising compounds according to the invention, and the use of said compounds in the preparation of a medicament for treating a variety of disorders, including proliferative disorders, viral disorders, stroke, etc. | 08-27-2009 |
20100035870 | Pyrimidin-4-yl-3, 4-Dihydro-2H-Pyrrolo[1,2A] Pyrazin-1-one Compounds - The present invention relates to compounds of formula (I), or pharmaceutically acceptable salts thereof, wherein Z is NR | 02-11-2010 |
20100292231 | Indazole Compounds for Treating Inflammatory Disorders, Demyelinating Disorders and Cancers - Compounds of formula (I) or formula (Ia) and a method of treating a patient suffering from certain inflammatory disorders, demyelinating disorders, FLT3-mediated disorders, CSF-1R-mediated disorders, cancers and leukemias, comprising administering to said patient a therapeutically effective amount of a compound of formula (I) or formula (Ia) or a pharmaceutically acceptable salt thereof. | 11-18-2010 |
Patent application number | Description | Published |
20150133427 | PRMT5 INHIBITORS AND USES THEREOF - Described herein are compounds of Formula (I), pharmaceutically acceptable salts thereof, and pharmaceutical compositions thereof. Compounds of the present invention are useful for inhibiting PRMT5 activity. Methods of using the compounds for treating PRMT5-mediated disorders are also described. | 05-14-2015 |
20150191432 | PRMT5 INHIBITORS AND USES THEREOF - Described herein are compounds of Formula (I), pharmaceutically acceptable salts thereof, and pharmaceutical compositions thereof. Compounds of the present invention are useful for inhibiting PRMT5 activity. Methods of using the compounds for treating PRMT5-mediated disorders are also described. | 07-09-2015 |
20150252031 | PRMT5 INHIBITORS AND USES THEREOF - Described herein are compounds of Formula (I), pharmaceutically acceptable salts thereof, and pharmaceutical compositions thereof. Compounds of the present invention are useful for inhibiting PRMT5 activity. Methods of using the compounds for treating PRMT5-mediated disorders are also described. | 09-10-2015 |
20150344433 | PRMT5 INHIBITORS CONTAINING A DIHYDRO- OR TETRAHYDROISOQUINOLINE AND USES THEREOF - Described herein are compounds of Formula (A), pharmaceutically acceptable salts thereof, and pharmaceutical compositions thereof. Compounds of the present invention are useful for inhibiting PRMT5 activity. Methods of using the compounds for treating PRMT5-mediated disorders are also described. | 12-03-2015 |
20150344434 | TETRAHYDRO- AND DIHYDRO-ISOQUINOLINE PRMT5 INHIBITORS AND USES THEREOF - Described herein are compounds of Formula (A), pharmaceutically acceptable salts thereof, and pharmaceutical compositions thereof. Compounds of the present invention are useful for inhibiting PRMT5 activity. Methods of using the compounds for treating PRMT5 mediated disorders are also described. | 12-03-2015 |
20150344457 | METHODS OF INHIBITING PRMT5 - Described herein are compounds of Formula (I) useful for inhibiting PRMT5 activity. The planes of Ring AA and Ring BB are between 75° and 105°. Ring AA-M-Ring BB (I) | 12-03-2015 |
20150344463 | PRMT5 INHIBITORS AND USES THEREOF - Described herein are compounds of Formula (A), pharmaceutically acceptable salts thereof, and pharmaceutical compositions thereof. Compounds of the present invention are useful for inhibiting PRMT5 activity. Methods of using the compounds for treating PRMT5-mediated disorders are also described. | 12-03-2015 |
20150361042 | PRMT5 INHIBITORS AND USES THEREOF - Described herein are compounds of formula (A), pharmaceutically acceptable salts thereof, and pharmaceutical compositions thereof. Compounds of the present invention are useful for inhibiting PRMT5 activity. Methods of using the compounds for treating PRMT5-mediated disorders are also described. | 12-17-2015 |
20160052922 | 1-PHENOXY-3-(ALKYLAMINO)-PROPAN-2-OL DERIVATIVES AS CARM1 INHIBITORS AND USES THEREOF - Provided herein are compounds of Formula (I): and pharmaceutically acceptable salts thereof, and pharmaceutical compositions thereof; wherein X, R | 02-25-2016 |
Patent application number | Description | Published |
20120264734 | Aryl- or Heteroaryl-Substituted Benzene Compounds - The present invention relates to aryl- or heteroaryl-substituted benzene compounds. The present invention also relates to pharmaceutical compositions containing these compounds and methods of treating cancer by administering these compounds and pharmaceutical compositions to subjects in need thereof. The present invention also relates to the use of such compounds for research or other non-therapeutic purposes. | 10-18-2012 |
20140213582 | PRMT5 INHIBITORS AND USES THEREOF - Described herein are compounds of Formula (I), pharmaceutically acceptable salts thereof, and pharmaceutical compositions thereof. Compounds of the present invention are useful for inhibiting PRMT5 activity. Methods of using the compounds for treating PRMT5-mediated disorders are also described. | 07-31-2014 |
20140221345 | PRMT5 INHIBITORS AND USES THEREOF - Described herein are compounds of Formula (I), pharmaceutically acceptable salts thereof, and pharmaceutical compositions thereof. Compounds of the present invention are useful for inhibiting PRMT5 activity. Methods of using the compounds for treating PRMT5-mediated disorders are also described. | 08-07-2014 |
20140323537 | ARGININE METHYLTRANSFERASE INHIBITORS AND USES THEREOF - Described herein are compounds of Formula (I), pharmaceutically acceptable salts thereof, and pharmaceutical compositions thereof. Compounds described herein are useful for inhibiting arginine methyltransferase activity. Methods of using the compounds for treating arginine methyltransferase-mediated disorders are also described. | 10-30-2014 |
20140329794 | PRMT5 INHIBITORS AND USES THEREOF - Described herein are compounds of Formula (I), pharmaceutically acceptable salts thereof, and pharmaceutical compositions thereof. Compounds of the present invention are useful for inhibiting PRMT5 activity. Methods of using the compounds for treating PRMT5-mediated disorders are also described. | 11-06-2014 |
Patent application number | Description | Published |
20130123234 | Aryl- or Heteroaryl-Substituted Benzene Compounds - The present invention relates to aryl- or heteroaryl-substituted benzene compounds. The present invention also relates to pharmaceutical compositions containing these compounds and methods of treating cancer by administering these compounds and pharmaceutical compositions to subjects in need thereof. The present invention also relates to the use of such compounds for research or other non-therapeutic purposes. | 05-16-2013 |
20130317026 | SUBSTITUTED 6,5-FUSED BICYCLIC HETEROARYL COMPOUNDS - The present invention relates to substituted 6,5-fused bicyclic heteroaryl compounds. The present invention also relates to pharmaceutical compositions containing these compounds and methods of treating cancer by administering these compounds and pharmaceutical compositions to subjects in need thereof. | 11-28-2013 |
20140057891 | Substituted 6,5-Fused Bicyclic Heteroaryl Compounds - The present invention relates to substituted 6,5-fused bicyclic heteroaryl compounds. The present invention also relates to pharmaceutical compositions containing these compounds and methods of treating cancer by administering these compounds and pharmaceutical compositions to subjects in need thereof. | 02-27-2014 |
20140142083 | Substituted Benzene Compounds - The present invention relates to substituted benzene compounds. The present invention also relates to pharmaceutical compositions containing these compounds and methods of treating cancer by administering these compounds and pharmaceutical compositions to subjects in need thereof. The present invention also relates to the use of such compounds for research or other non-therapeutic purposes. | 05-22-2014 |
20140288041 | Aryl- or Heteroaryl-Substituted Benzene Compounds - The present invention relates to aryl- or heteroaryl-substituted benzene compounds. The present invention also relates to pharmaceutical compositions containing these compounds and methods of treating cancer by administering these compounds and pharmaceutical compositions to subjects in need thereof. The present invention also relates to the use of such compounds for research or other non-therapeutic purposes. | 09-25-2014 |
20150065483 | Substituted 6,5-Fused Bicyclic Heteroaryl Compounds - The present invention relates to substituted 6,5-fused bicyclic heteroaryl compounds. The present invention also relates to pharmaceutical compositions containing these compounds and methods of treating cancer by administering these compounds and pharmaceutical compositions to subjects in need thereof. | 03-05-2015 |
20150266854 | Substituted 6,5-Fused Bicyclic Heteroaryl Compounds - The present invention relates to substituted 6,5-fused bicyclic heteroaryl compounds. The present invention also relates to pharmaceutical compositions containing these compounds and methods of treating cancer by administering these compounds and pharmaceutical compositions to subjects in need thereof. | 09-24-2015 |
20150353494 | ARYL- OR HETEROARYL-SUBSTITUTED BENZENE COMPOUNDS - The present invention relates to aryl- or heteroaryl-substituted benzene compounds. The present invention also relates to pharmaceutical compositions containing these compounds and methods of treating cancer by administering these compounds and pharmaceutical compositions to subjects in need thereof. The present invention also relates to the use of such compounds for research or other non-therapeutic purposes. | 12-10-2015 |
20160022693 | ARYL- OR HETEROARYL-SUBSTITUTED BENZENE COMPOUNDS - The present invention relates to aryl- or heteroaryl-substituted benzene compounds. The present invention also relates to pharmaceutical compositions containing these compounds and methods of treating cancer by administering these compounds and pharmaceutical compositions to subjects in need thereof. The present invention also relates to the use of such compounds for research or other non-therapeutic purposes. | 01-28-2016 |
Patent application number | Description | Published |
20100153658 | Deadlock Avoidance By Marking CPU Traffic As Special - Deadlocks are avoided by marking read requests issued by a parallel processor to system memory as “special.” Read completions associated with read requests marked as special are routed on virtual channel | 06-17-2010 |
20110072177 | VIRTUAL CHANNELS FOR EFFECTIVE PACKET TRANSFER - The invention sets forth a crossbar unit that includes multiple virtual channels, each virtual channel being a logical flow of data within the crossbar unit. Arbitration logic coupled to source client subsystems is configured to select a virtual channel for transmitting a data request or a data packet to a destination client subsystem based on the type of the source client subsystem and/or the type of data request. Higher priority traffic is transmitted over virtual channels that are configured to transmit data without causing deadlocks and/or stalls. Lower priority traffic is transmitted over virtual channels that can be stalled. | 03-24-2011 |
20130124838 | INSTRUCTION LEVEL EXECUTION PREEMPTION - One embodiment of the present invention sets forth a technique instruction level and compute thread array granularity execution preemption. Preempting at the instruction level does not require any draining of the processing pipeline. No new instructions are issued and the context state is unloaded from the processing pipeline. When preemption is performed at a compute thread array boundary, the amount of context state to be stored is reduced because execution units within the processing pipeline complete execution of in-flight instructions and become idle. If, the amount of time needed to complete execution of the in-flight instructions exceeds a threshold, then the preemption may dynamically change to be performed at the instruction level instead of at compute thread array granularity. | 05-16-2013 |
20130132711 | COMPUTE THREAD ARRAY GRANULARITY EXECUTION PREEMPTION - One embodiment of the present invention sets forth a technique instruction level and compute thread array granularity execution preemption. Preempting at the instruction level does not require any draining of the processing pipeline. No new instructions are issued and the context state is unloaded from the processing pipeline. When preemption is performed at a compute thread array boundary, the amount of context state to be stored is reduced because execution units within the processing pipeline complete execution of in-flight instructions and become idle. If, the amount of time needed to complete execution of the in-flight instructions exceeds a threshold, then the preemption may dynamically change to be performed at the instruction level instead of at compute thread array granularity. | 05-23-2013 |
20130152093 | Multi-Channel Time Slice Groups - A time slice group (TSG) is a grouping of different streams of work (referred to herein as “channels”) that share the same context information. The set of channels belonging to a TSG are processed in a pre-determined order. However, when a channel stalls while processing, the next channel with independent work can be switched to fully load the parallel processing unit. Importantly, because each channel in the TSG shares the same context information, a context switch operation is not needed when the processing of a particular channel in the TSG stops and the processing of a next channel in the TSG begins. Therefore, multiple independent streams of work are allowed to run concurrently within a single context increasing utilization of parallel processing units. | 06-13-2013 |
20140012904 | PROVIDING BYTE ENABLES FOR PEER-TO-PEER DATA TRANSFER WITHIN A COMPUTING ENVIRONMENT - Non-contiguous or tiled payload data are efficiently transferred between peers over a fabric. Specifically, a client transfers a byte enable message to a peer device via a mailbox mechanism, where the byte enable message specifies which bytes of the payload data being transferred via the data packet are to be written to the frame buffer on the peer device and which bytes are not to be written. The client transfers the non-contiguous or tiled payload payload data to the peer device. Upon receiving the payload data, the peer device writes bytes from the payload data into the target frame buffer for only those bytes enabled via the byte enable message. One advantage of the present invention is that non-contiguous or tiled data are transferred over a fabric with improved efficiency. | 01-09-2014 |
20140095759 | REPLICATED STATELESS COPY ENGINE - Techniques are disclosed for performing an auxiliary operation via a compute engine associated with a host computing device. The method includes determining that the auxiliary operation is directed to the compute engine, and determining that the auxiliary operation is associated with a first context comprising a first set of state parameters. The method further includes determining a first subset of state parameters related to the auxiliary operation based on the first set of state parameters. The method further includes transmitting the first subset of state parameters to the compute engine, and transmitting the auxiliary operation to the compute engine. One advantage of the disclosed technique is that surface area and power consumption are reduced within the processor by utilizing copy engines that have no context switching capability. | 04-03-2014 |
20140109102 | TECHNIQUE FOR IMPROVING PERFORMANCE IN MULTI-THREADED PROCESSING UNITS - A multi-threaded processing unit includes a hardware pre-processor coupled to one or more processing engines (e.g., copy engines, GPCs, etc.) that implement pre-emption techniques by dividing tasks into smaller subtasks and scheduling subtasks on the processing engines based on the priority of the tasks. By limiting the size of the subtasks, higher priority tasks may be executed quickly without switching the context state of the processing engine. Tasks may be subdivided based on a threshold size or by taking into account other consideration such as physical boundaries of the memory system. | 04-17-2014 |
20140281255 | PAGE STATE DIRECTORY FOR MANAGING UNIFIED VIRTUAL MEMORY - A system for managing virtual memory. The system includes a first processing unit configured to execute a first operation that references a first virtual memory address. The system also includes a first memory management unit (MMU) associated with the first processing unit and configured to generate a first page fault upon determining that a first page table that is stored in a first memory unit associated with the first processing unit does not include a mapping corresponding to the first virtual memory address. The system further includes a first copy engine associated with the first processing unit. The first copy engine is configured to read a first command queue to determine a first mapping that corresponds to the first virtual memory address and is included in a first page state directory. The first copy engine is also configured to update the first page table to include the first mapping. | 09-18-2014 |
20140281256 | FAULT BUFFER FOR RESOLVING PAGE FAULTS IN UNIFIED VIRTUAL MEMORY SYSTEM - A system for managing virtual memory. The system includes a first processing unit configured to execute a first operation that references a first virtual memory address. The system also includes a first memory management unit (MMU) associated with the first processing unit and configured to generate a first page fault upon determining that a first page table that is stored in a first memory unit associated with the first processing unit does not include a mapping corresponding to the first virtual memory address. The system further includes a first copy engine associated with the first processing unit. The first copy engine is configured to read a first command queue to determine a first mapping that corresponds to the first virtual memory address and is included in a first page state directory. The first copy engine is also configured to update the first page table to include the first mapping. | 09-18-2014 |
20140281263 | REPLAYING MEMORY TRANSACTIONS WHILE RESOLVING MEMORY ACCESS FAULTS - One embodiment of the present invention is a parallel processing unit (PPU) that includes one or more streaming multiprocessors (SMs) and implements a replay unit per SM. Upon detecting a page fault associated with a memory transaction issued by a particular SM, the corresponding replay unit causes the SM, but not any unaffected SMs, to cease issuing new memory transactions. The replay unit then stores the faulting memory transaction and any faulting in-flight memory transaction in a replay buffer. As page faults are resolved, the replay unit replays the memory transactions in the replay buffer—removing successful memory transactions from the replay buffer—until all of the stored memory transactions have successfully executed. Advantageously, the overall performance of the PPU is improved compared to conventional PPUs that, upon detecting a page fault, stop performing memory transactions across all SMs included in the PPU until the fault is resolved. | 09-18-2014 |
20140281296 | FAULT BUFFER FOR TRACKING PAGE FAULTS IN UNIFIED VIRTUAL MEMORY SYSTEM - A system for managing virtual memory. The system includes a first processing unit configured to execute a first operation that references a first virtual memory address. The system also includes a first memory management unit (MMU) associated with the first processing unit and configured to generate a first page fault upon determining that a first page table that is stored in a first memory unit associated with the first processing unit does not include a mapping corresponding to the first virtual memory address. The system further includes a first copy engine associated with the first processing unit. The first copy engine is configured to read a first command queue to determine a first mapping that corresponds to the first virtual memory address and is included in a first page state directory. The first copy engine is also configured to update the first page table to include the first mapping. | 09-18-2014 |
20140281357 | COMMON POINTERS IN UNIFIED VIRTUAL MEMORY SYSTEM - A system for managing virtual memory. The system includes a first processing unit configured to execute a first operation that references a first virtual memory address. The system also includes a first memory management unit (MMU) associated with the first processing unit and configured to generate a first page fault upon determining that a first page table that is stored in a first memory unit associated with the first processing unit does not include a mapping corresponding to the first virtual memory address. The system further includes a first copy engine associated with the first processing unit. The first copy engine is configured to read a first command queue to determine a first mapping that corresponds to the first virtual memory address and is included in a first page state directory. The first copy engine is also configured to update the first page table to include the first mapping. | 09-18-2014 |
20140281358 | MIGRATION SCHEME FOR UNIFIED VIRTUAL MEMORY SYSTEM - A system for managing virtual memory. The system includes a first processing unit configured to execute a first operation that references a first virtual memory address. The system also includes a first memory management unit (MMU) associated with the first processing unit and configured to generate a first page fault upon determining that a first page table that is stored in a first memory unit associated with the first processing unit does not include a mapping corresponding to the first virtual memory address. The system further includes a first copy engine associated with the first processing unit. The first copy engine is configured to read a first command queue to determine a first mapping that corresponds to the first virtual memory address and is included in a first page state directory. The first copy engine is also configured to update the first page table to include the first mapping. | 09-18-2014 |
20150082001 | TECHNIQUES FOR SUPPORTING FOR DEMAND PAGING - One embodiment of the present invention includes techniques to support demand paging across a processing unit. Before a host unit transmits a command to an engine that does not tolerate page faults, the host unit ensures that the virtual memory addresses associated with the command are appropriately mapped to physical memory addresses. In particular, if the virtual memory addresses are not appropriately mapped, then the processing unit performs actions to map the virtual memory address to appropriate locations in physical memory. Further, the processing unit ensures that the access permissions required for successful execution of the command are established. Because the virtual memory address mappings associated with the command are valid when the engine receives the command, the engine does not encounter page faults upon executing the command. Consequently, in contrast to prior-art techniques, the engine supports demand paging regardless of whether the engine is involved in remedying page faults. | 03-19-2015 |
Patent application number | Description | Published |
20120139928 | DATA PACKER FOR PACKING AND ALIGNING WRITE DATA - A data packer of an input/output hub of a computer system packs and formats write data that is supplied to it before the write data is written into a memory unit of the computer system. More particularly, the data packer accumulates write data received from lower bandwidth clients for delivery to a high bandwidth memory interface. Also, the data packer aligns the write data, so that when the write data is read out from the write data packer, no further alignment is needed. | 06-07-2012 |
20120147019 | DATA PACKER FOR PACKING AND ALIGNING WRITE DATA - A data packer of an input/output hub of a computer system packs and formats write data that is supplied to it before the write data is written into a memory unit of the computer system. More particularly, the data packer accumulates write data received from lower bandwidth clients for delivery to a high bandwidth memory interface. Also, the data packer aligns the write data, so that when the write data is read out from the write data packer, no further alignment is needed. | 06-14-2012 |
20120147024 | DATA PACKER FOR PACKING AND ALIGNING WRITE DATA - A data packer of an input/output hub of a computer system packs and formats write data that is supplied to it before the write data is written into a memory unit of the computer system. More particularly, the data packer accumulates write data received from lower bandwidth clients for delivery to a high bandwidth memory interface. Also, the data packer aligns the write data, so that when the write data is read out from the write data packer, no further alignment is needed. | 06-14-2012 |
20150199280 | METHOD AND SYSTEM FOR IMPLEMENTING MULTI-STAGE TRANSLATION OF VIRTUAL ADDRESSES - A system and method are provided for implementing multi-stage translation of virtual addresses. The method includes the steps of receiving, at a first memory management unit, a memory request including a virtual address in a first address space, translating the virtual address to generate a second virtual address in a second address space, and transmitting a modified memory request including the second virtual address to a second memory management unit. The second memory management unit is configured to translate the second virtual address to generate a physical address in a third address space. The physical address is associated with a location in a memory. | 07-16-2015 |
Patent application number | Description | Published |
20080241978 | LIGHT EMITTING DEVICE PROCESSES - Light-emitting devices, and related components, processes, systems and methods are disclosed. | 10-02-2008 |
20080248602 | LIGHT EMITTING DEVICE PROCESSES - Light-emitting devices, and related components, processes, systems and methods are disclosed. | 10-09-2008 |
20090023239 | LIGHT EMITTING DEVICE PROCESSES - Light-emitting devices, and related components, processes, systems and methods are disclosed. | 01-22-2009 |
20090137072 | LIGHT EMITTING DEVICE METHODS - Light-emitting device methods are disclosed. | 05-28-2009 |
20110263128 | SELECTIVE WET ETCHING AND TEXTURED SURFACE PLANARIZATION PROCESSES - The present invention relates to systems and methods associated with selective wet etching and textured surface planarization. The systems and methods described herein can be used to etch a component of a multi-layer stack, such as a GaN layer. In some embodiments, the multi-layer stack can include a substrate having a patterned surface and a light generating region. The substrate can be removed from the first multi-layer stack to form a second multi-layer stack. In some embodiments, the pattern on the surface of the substrate can leave behind a pattern on a surface of the second multi-layer stack. Accordingly, in some cases, the surface of the second multi-layer stack can be wet etched, for example, to smoothen the surface. In some embodiments, removing the substrate can expose an N-face of a GaN layer, and the wet etch can be performed such that the N-face of the GaN layer is etched. In some embodiments, the multi-layer stack includes a light generating region and can be part of a light emitting device. | 10-27-2011 |
20120261711 | ELECTRONIC DEVICE CONTACT STRUCTURES - Electronic devices involving contact structures, and related components, systems and methods associated therewith are described. The contact structures are particularly suitable for use in a variety of light-emitting devices, including LEDs. | 10-18-2012 |
20130146932 | LIGHT-EMITTING DIODE ARCHITECTURES FOR ENHANCED PERFORMANCE - The present invention relates to light-emitting diodes (LEDs), and related components, processes, systems, and methods. In certain embodiments, an LED that provides improved optical and thermal efficiency when used in optical systems with a non-rectangular input aperture (e.g., a circular aperture) is described. In some embodiments, the emission surface of the LED and/or an emitter output aperture can be shaped (e.g., in a non-rectangular shape) such that enhanced optical and thermal efficiencies are achieved. In addition, in some embodiments, chip designs and processes that may be employed in order to produce such devices are described. | 06-13-2013 |
20140057375 | WAVELENGTH CONVERTING MATERIAL DEPOSITION METHODS AND ASSOCIATED ARTICLES - Systems and methods related to the arrangement of regions containing wavelength-converting materials, and associated articles, are provided. | 02-27-2014 |
20150207036 | ELECTRONIC DEVICE CONTACT STRUCTURES - Electronic devices involving contact structures, and related components, systems and methods associated therewith are described. The contact structures are particularly suitable for use in a variety of light-emitting devices, including LEDs. | 07-23-2015 |