Patent application number | Description | Published |
20080199302 | Fuel pump for engine - A fuel pump includes a bearing element disposed in proximity to an impeller. The bearing element is configured to form a fuel seal with the impeller and to drain fuel leaked from the pump chamber back into the pump chamber. The bearing element minimizes leakage of fuel from the pump chamber into an engine coupled to the impeller. The fuel pump also includes redundant lip seals configured to provide redundant sealing relative to a shaft of the impeller within the fuel pump in order to minimize engine oil from entering the pump chamber and to minimize fuel from entering the engine. Integration of both the bearing element and the redundant lip seals as part of the fuel pump results in the fuel pump having a relatively compact size. | 08-21-2008 |
20090031992 | FUEL INJECTOR MOUNTING ASSEMBLY FOR AN AIRCRAFT ENGINE FUEL DELIVERY SYSTEM - A fuel injector mounting assembly is configured to limit or constrain movement of a fuel injector relative to a corresponding cylinder assembly. For example, the fuel injector mounting assembly includes a base that is secured to a cylinder assembly's housing and a fuel conduit. The fuel conduit includes a first fuel conduit portion which operates in conjunction with a cylinder assembly's fuel manifold to capture a fuel injector between the fuel injector mounting assembly and the cylinder assembly's fuel manifold. The fuel conduit also includes a second fuel conduit portion which is secured to a compliant fuel line. With such a configuration of the fuel injector mounting assembly, both ends of the fuel injector are secured to the cylinder assembly to minimize any relative motion in the fuel injector's seals relative to either the cylinder assembly's fuel manifold or to the compliant fuel line. | 02-05-2009 |
20090058183 | Power source for aircraft engine controller systems - An aircraft engine power distribution system for an aircraft engine controller, such as a FADEC, is provided where the power source is independent from the conventional airframe power system, without the need for a back-up battery. The aircraft engine power distribution system includes a magnetic generator operated by an aircraft engine. The aircraft engine power distribution system also includes a power distributor that rectifies the generator output and provides the rectified power to the engine controller as its primary source of power. In this configuration, as long as the aircraft engine is able to operate the magnetic generator, the engine controller receives power. Accordingly, the engine controller operates regardless of the operational status of the airframe power system. | 03-05-2009 |
20100043750 | AIRCRAFT ENGINE CRANKSHAFT POSITION AND ANGULAR VELOCITY DETECTION APPARATUS - A crankshaft detection system includes a pickup element mounted to an end of a crankshaft and disposed within a rear portion of the aircraft engine's crankcase. The crankshaft detection system also includes pickup element sensor secured to a mounting location formed in the rear portion of the aircraft engine's crankcase and disposed in proximity to the pickup element. As the crankshaft rotates the pickup element relative to the pickup element sensor, the pickup element causes the pickup element sensor to generate a signal indicative of the angular velocity and rotational position of the crankshaft. In order to optimize engine performance, in response to the signal, the controller controls a spark event associated with each the cylinder assembly of the engine such that ignition of the fuel and air mixture occurs within each cylinder assembly at a time prior to each piston of each cylinder assembly reaching a top dead center position. | 02-25-2010 |
Patent application number | Description | Published |
20080198678 | PROGRAMMABLE SRAM SOURCE BIAS SCHEME FOR USE WITH SWITCHABLE SRAM POWER SUPPLY SETS OF VOLTAGES - A memory circuit has a high voltage and low voltage supply nodes. One of a first and second sets of voltages is selectively applied to the supply nodes of the memory circuit in dependence upon memory operational mode. If in active read/write mode, then the first set of voltages is selectively applied. Conversely, if in standby no-read/no-write mode, then the second set of voltages is selectively applied. A low voltage in the second set of voltages is greater than a low voltage in the first set of voltages by a selected one of a plurality of low offset voltages, and a high voltage in the second set of voltages is less than a high voltage in the first set of voltages by a selected one of a plurality of high offset voltages. The offset voltages are provided by diode-based circuits that are selectively active. Selective activation is provided by either selectably blowable fuse elements or selectively activated switching elements. | 08-21-2008 |
20080198679 | SRAM WITH SWITCHABLE POWER SUPPLY SETS OF VOLTAGES - A circuit includes a memory cell having a high voltage supply node and a low voltage supply node. Power multiplexing circuitry is provided to selectively apply one of a first set of voltages and a second set of voltages to the high and low voltage supply nodes of the cell in dependence upon a current operational mode of the cell. If the cell is in active read or write mode, then the multiplexing circuitry selectively applies the first set of voltages to the high and low voltage supply nodes. Conversely, if the cell is in standby no-read or no-write mode, then the multiplexing circuitry selectively applies the second set of voltages to the high and low voltage supply nodes. The second set of voltages are offset from the first set of voltages. More particularly, a low voltage in the second set of voltages is higher than a low voltage in the first set of voltages, and wherein a high voltage in the second set of voltages is less than a high voltage in the first set of voltages. The cell can be a member of an array of cells, in which case the selective application of voltages applies to the array depending on the active/standby mode of the array. The array can comprise a block or section within an overall memory device including many blocks or sections, in which case the selective application of voltages applies to individual blocks/sections depending on the active/standby mode of the block/section itself. | 08-21-2008 |
20080211513 | INITIATION OF FUSE SENSING CIRCUITRY AND STORAGE OF SENSED FUSE STATUS INFORMATION - An integrated circuit includes at least one circuit trimming fuse. A fuse sensor circuit is connected to the trimming fuse and operates in response to a fuse sensing initiation signal to initiate sensing of a state of the trimming fuse and generate an output indicative of the sensed state. A latch circuit, including multiple latch locations, redundantly latches the output indicative of the sensed state. A majority logic state in the latch locations is determined by a polling circuit coupled to the multiple latch locations. The polling circuit outputs that majority logic state as a fuse state output indicative of the sensed state of the fuse. A register in the integrated circuit is loadable with a value. A comparison circuit compares the loaded value in the register to a correct fuseword value and, if there is a match, generates the fuse sensing initiation signal for application to the fuse sensor circuit. | 09-04-2008 |
20100165709 | ROBUST SRAM MEMORY CELL CAPACITOR PLATE VOLTAGE GENERATOR - An SRAM having two capacitors connected in series between respective bit storage nodes of each memory cell. The two inverters of the memory cell are powered by a positive voltage and a low voltage. The two capacitors are connected to each other at a common node. A leakage current generator is coupled to the common node. The leakage current generator supplies to the common node a leakage current to maintain a voltage which is approximately halfway between the voltages of the high and low SRAM supplies. | 07-01-2010 |
20130182523 | ROBUST SRAM MEMORY CELL CAPACITOR PLATE VOLTAGE GENERATOR - An SRAM having two capacitors connected in series between respective bit storage nodes of each memory cell. The two inverters of the memory cell are powered by a positive voltage and a low voltage. The two capacitors are connected to each other at a common node. A leakage current generator is coupled to the common node. The leakage current generator supplies to the common node a leakage current to maintain a voltage which is approximately halfway between the voltages of the high and low SRAM supplies. | 07-18-2013 |