Patent application number | Description | Published |
20080279014 | MULTI-PHASE WORDLINE ERASING FOR FLASH MEMORY - Erasing wordlines at the same time can cause undesirable results because some wordlines are affected by electromagnetic waves of other wordlines. However, other wordlines are not affected because they are next to contacts. Therefore, it can be beneficial to erase wordlines in a multi-phase sequence that allows for erasing wordlines without an impact from other wordlines. | 11-13-2008 |
20090155992 | HIGH K STACK FOR NON-VOLATILE MEMORY - A memory device may include a source region and a drain region formed in a substrate and a channel region formed in the substrate between the source and drain regions. The memory device may further include a first oxide layer formed over the channel region, the first oxide layer having a first dielectric constant, and a charge storage layer formed upon the first oxide layer. The memory device may further include a second oxide layer formed upon the charge storage layer, a layer of dielectric material formed upon the second oxide layer, the dielectric material having a second dielectric constant that is greater than the first dielectric constant, and a gate electrode formed upon the layer of dielectric material. | 06-18-2009 |
20090159958 | ELECTRONIC DEVICE INCLUDING A SILICON NITRIDE LAYER AND A PROCESS OF FORMING THE SAME - An electronic device can include a silicon nitride layer. In an embodiment, the silicon nitride layer can include boron, grains, or both. The silicon nitride layer may be used as part of a charge storage layer within a nonvolatile memory cell within the electronic device. In a particular embodiment, the boron within the silicon nitride layer may be no greater than approximately 9 atomic % of the layer. The boron can be incorporated into the silicon nitride layer as it is being formed. The layer can be formed using chemical vapor deposition, physical vapor deposition, another suitable formation process, or any combination thereof. | 06-25-2009 |
20090189212 | ELECTRONIC DEVICE HAVING A DOPED REGION WITH A GROUP 13 ATOM - An electronic device includes a memory cell. The memory cell includes a semiconductor region, a first current-carrying electrode adjacent to the semiconductor region, and a first dopant-containing region adjacent to a first current-carrying electrode. The semiconductor region includes a Group 14 atom and the first dopant-containing region includes a Group 13 atom. The Group 13 atom has an atomic number greater than the atomic number of the Group 14 atom. | 07-30-2009 |
20100027350 | FLASH MEMORY PROGRAMMING AND VERIFICATION WITH REDUCED LEAKAGE CURRENT - A flash memory system configured in accordance with an example embodiment of the invention employs a virtual ground array architecture. During programming operations, target memory cells are biased with a positive source bias voltage to reduce or eliminate leakage current that might otherwise conduct through the target memory cells. A positive source bias voltage may also be applied to target memory cells during verification operations (program verify, soft program verify, erase verify) to reduce or eliminate leakage current that might otherwise introduce errors in the verification operations. | 02-04-2010 |
20100240210 | STRAPPING CONTACT FOR CHARGE PROTECTION - A semiconductor device includes a substrate and a memory cell formed on the substrate. The memory cell includes a word line. The semiconductor device also includes a protection area formed in the substrate, a conductive structure configured to extend the word line to the protection area, and a contact configured to short the word line and the protection area. | 09-23-2010 |
20100314753 | SYSTEM AND METHOD FOR REDUCING PROCESS-INDUCED CHARGING - A semiconductor device includes a substrate, a memory cell formed on the substrate, and a contact to the substrate. The contact is formed in an area away from the memory cell and functions to raise the potential of the substrate. | 12-16-2010 |
20130237022 | METHOD AND APPARATUS FOR PROTECTION AGAINST PROCESS-INDUCED CHARGING - A semiconductor device ( | 09-12-2013 |
20140233339 | APPARATUS AND METHOD TO REDUCE BIT LINE DISTURBS - A non-volatile memory device comprising a memory cell array including a plurality of non-volatile memory cells arranged in rows and columns, wherein memory cells arranged in a same row share a word line and memory cells arranged in a same column share a bit line; and at least an address decoder to provide a negative voltage to at least one non-accessed word line in said array when a programming or erasure voltage is provided along a shared bit line. | 08-21-2014 |
Patent application number | Description | Published |
20090135659 | ROOM TEMPERATURE DRIFT SUPPRESSION VIA SOFT PROGRAM AFTER ERASE - Providing for suppression of room temperature electronic drift in a flash memory cell is provided herein. For example, a soft program pulse can be applied to the flash memory cell immediately after an erase pulse. The soft program pulse can help to mitigate dipole effects caused by non-combined electrons and holes in the memory cell. Specifically, by utilizing a relatively low gate voltage, the soft program pulse can inject electrons into the flash memory cell proximate a distribution of uncombined holes associated with the erase pulse in order to facilitate rapid combination of such particles. Rapid combination in this manner reduces dipole effects caused by non-combined distributions of opposing charge within the memory cell, reducing room temperature program state drift | 05-28-2009 |
20090161466 | EXTENDING FLASH MEMORY DATA RETENSION VIA REWRITE REFRESH - Providing for extended data retention of flash memory devices by program state rewrite is disclosed herein. By way of example, a memory cell or group of memory cells can be evaluated to determine a program state of the cell(s). If the cell(s) is in a program state, as opposed to a natural or non-programmed state, a charge level, voltage level and/or the like can be rewritten to a default level associated with the program state, without erasing the cell(s) first. Accordingly, conventional mechanisms for refreshing cell program state that require rewriting and erasing, typically degrading storage capacity of the memory cell, can be avoided. As a result, data stored in flash memory can be refreshed in a manner that mitigates loss of memory integrity, providing substantial benefits over conventional mechanisms that can degrade memory integrity at a relatively high rate. | 06-25-2009 |
20100128521 | APPLYING NEGATIVE GATE VOLTAGE TO WORDLINES ADJACENT TO WORDLINE ASSOCIATED WITH READ OR VERIFY TO REDUCE ADJACENT WORDLINE DISTURB - Systems, methods, and devices that facilitate applying a predefined negative gate voltage to wordlines adjacent to a selected wordline associated with a memory cell selected during a read or verify operation to facilitate reducing adjacent wordline disturb are presented. A memory component can comprise an optimized operation component that can apply a predefined negative gate voltage to wordlines adjacent to a selected wordline associated with a memory cell selected for a read or verify operation, based at least in part on predefined operation criteria, to facilitate reducing adjacent wordline disturb in the selected memory cell to facilitate reducing a shift in the voltage threshold and maintain a desired operation window. The optimized operation component optionally can include an evaluator component that can facilitate determining whether a negative gate voltage applied to adjacent wordlines is to be adjusted to facilitate reducing adjacent wordline disturb below a predetermined threshold amount. | 05-27-2010 |
20120122285 | MEMORY DEVICE HAVING TRAPEZOIDAL BITLINES AND METHOD FO FABRICATING SAME - A memory device and a method of fabrication are provided. The memory device includes a semiconductor substrate and a charge trapping dielectric stack disposed over the semiconductor substrate. A gate electrode is disposed over the charge trapping dielectric stack, where the gate electrode electrically defines a channel within a portion of the semiconductor substrate. The memory device includes a pair of bitlines, where the bitlines have a lower portion and a substantially trapezoidal shaped upper portion. | 05-17-2012 |
20140015138 | Leakage Reducing Writeline Charge Protection Circuit - Methods and systems of fabricating a wordline protection structure are described. As described, the wordline protection structure includes a polysilicon structure formed adjacent to a memory core region. The polysilicon structure includes first doped region positioned on a core side of the polysilicon structure and a second doped region positioned on a spine side of the polysilicon structure. An un-doped region positioned between the first and second doped regions. A conductive layer is formed on top of the polysilicon structure and arranged so that it does not contact the un-doped region at either the transition between the first doped region and the un-doped region or the second doped region and un-doped region. | 01-16-2014 |
20150103601 | MULTI-PASS SOFT PROGRAMMING - Disclosed herein are system, method and computer program product embodiments for utilizing soft programming a nonvolatile memory. An embodiment operates by sequentially applying a single soft programming voltage pulse to all memory cells along each word line in the nonvolatile memory that fail soft programming verification in a first phase. This sequential application of the single soft programming voltage pulse in the first phase may repeat a predetermined number of times or until a threshold is met. Once the predetermined number of times completes, or the threshold is met, soft programming proceeds to a second phase where soft programming remains with each word line until all memory cells along the word line passes soft programming verification. | 04-16-2015 |
Patent application number | Description | Published |
20090216559 | SYSTEM FOR PROVIDING ANONYMOUS ACCESS TO HEALTH INFORMATION - A system for providing anonymous access to health information may include an interface, a memory and a web portal. The interface may be operative to receive a test result of a biological sample of an individual and a unique identifier associated with the test result. The individual may not be identifiable by the unique identifier. The memory may be operative to store a record in a database. The record may include the test result and the unique identifier associated with the test result. The web portal may be coupled with the database and may be operative to receive the unique identifier from a user. The web portal may retrieve the record comprising of the unique identifier, and display the test result stored in the record to the user. | 08-27-2009 |
20140147526 | ANTIOXIDANT DIETARY SUPPLEMENT AND RELATED METHOD - A supplement including a blend of turmeric, quercetin and rosemary, or holy basil, wasabi, and broccoli seed extract which are present in a balanced and predetermined ratio, and which stimulate the Antioxidant Response Element (ARE), Quinone Reductase, and/or induce related gene expression, for example, heme oxygenase-1 (HMOX-1) expression. The blend of ingredients can be formed as or in a dietary supplement adapted for administration to a subject. The dietary supplement can be formulated so that the turmeric, quercetin and rosemary are present in a predetermined ratio of 1:3:5, or holy basil, wasabi, and broccoli seed extract in a predetermined ratio of 1:1:0.2. Additional ingredients can be included in the supplement. The supplement can synergistically affect natural antioxidant response pathways within cells of a subject to whom the supplement is administered. A related method of use is also provided. | 05-29-2014 |
Patent application number | Description | Published |
20140377386 | PLANT-BASED INHIBITORS OF KETOHEXOKINASE FOR THE SUPPORT OF WEIGHT MANAGEMENT - A composition for inhibiting ketohexokinase, for example, ketohexokinase-C (KHK-C) activity, may include a plant extract exhibiting at least IC50 (i.e., 50% KHK-C inhibition at a concentration in the range of from about 0.1 μg/mL to about 1000 μg/mL. The composition may be in a form suitable for oral ingestion. A method for inhibiting KHK-C activity in a subject may include administering a plant extract that exhibits at least 50% KHK-C inhibition at a concentration from about 0.1 μg/mL to about 1000 μg/mL. The administering may be done to treat or prevent at least one of sugar addiction, obesity, or metabolic syndrome. The administering may be done to provide a diminished craving in the subject from at least one member selected from the group consisting of craving of sugar, fructose, fructose-containing sugars, carbohydrates, and combinations thereof. The subject may be pre-diabetic, diabetic and or insulin resistant. | 12-25-2014 |
20150258158 | COMPOSITIONS AND METHODS FOR INHIBITION OF TRIGLYCERIDE SYNTHESIS VIA SYNERGISTIC COMBINATION OF BOTANICAL FORMULATIONS - Compositions and methods for inhibition of triglyceride synthesis via synergistic combination of botanical extracts are described. Specifically, the present invention relates to treating or preventing weight gain or obesity, promoting weight loss, appetite suppression, or the like, as well as managing skin oil production through a synergistic inhibition of diacylglycerol acyltransferase-I (DGAT-I) enzyme involved in the triglyceride synthesis and modulation of sterol regulatory element binding protein Ic (SREBP-Ic) and/or peroxisome proliferator activated receptor gamma coactivator I-alpha (PGCIα). | 09-17-2015 |