Cosmin
Adam P. Cosmin, San Jose, CA US
Patent application number | Description | Published |
---|---|---|
20090135649 | Scalable Electrically Eraseable And Programmable Memory (EEPROM) Cell Array - A non-volatile memory (NVM) system includes a plurality of NVM cells fabricated in a dual-well structure. Each NVM cell includes an access transistor and an NVM transistor, wherein the access transistor has a drain region that is continuous with a source region of the NVM transistor. The drain regions of each NVM transistor in a column of the array are commonly connected to a corresponding bit line. The control gates of each NVM transistor in a row of the array are commonly connected to a corresponding word line. The source regions of each of the access transistors in the array are commonly coupled. The NVM cells are programmed and erased without having to apply the high programming voltage V | 05-28-2009 |
20090196105 | Scalable Electrically Eraseable And Programmable Memory (EEPROM) Cell Array - A non-volatile memory (NVM) system includes a plurality of NVM cells fabricated in a dual-well structure. Each NVM cell includes an access transistor and an NVM transistor, wherein the access transistor has a drain region that is continuous with a source region of the NVM transistor. The drain regions of each NVM transistor in a column of the array are commonly connected to a corresponding bit line. The control gates of each NVM transistor in a row of the array are commonly connected to a corresponding word line. The source regions of each of the access transistors in the array are commonly coupled. The NVM cells are programmed and erased without having to apply the high programming voltage V | 08-06-2009 |
A. Peter Cosmin, Santa Clara, CA US
Patent application number | Description | Published |
---|---|---|
20090003074 | Scalable Electrically Eraseable And Programmable Memory (EEPROM) Cell Array - A non-volatile memory (NVM) system includes a plurality of NVM cells fabricated in a dual-well structure. Each NVM cell includes an access transistor and an NVM transistor, wherein the access transistor has a drain region that is continuous with a source region of the NVM transistor. The drain regions of each NVM transistor in a column of the array are commonly connected to a corresponding bit line. The control gates of each NVM transistor in a row of the array are commonly connected to a corresponding word line. The source regions of each of the access transistors in the array are commonly coupled. The NVM cells are programmed and erased without having to apply the high programming voltage V | 01-01-2009 |
20120140565 | Scalable Electrically Eraseable And Programmable Memory - A non-volatile memory including one or more EEPROM cell pairs. Each EEPROM cell pair includes three transistors and stores two data bits, effectively providing a 1.5 transistor EEPROM cell. An EEPROM cell pair includes a first non-volatile memory transistor connected to a first bit line, a second non-volatile memory transistor connected to a second bit line, and a source access transistor coupled to common source line. The source access transistor includes: a first diffusion region continuous with a source region of the first non-volatile memory transistor and a second diffusion region continuous with a source region of the second non-volatile memory transistor. | 06-07-2012 |
A. Peter Cosmin, San Jose, CA US
Patent application number | Description | Published |
---|---|---|
20080291729 | Non-Volatile Memory With High Reliability - A non-volatile memory (NVM) system includes a set of NVM cells, each including: a NVM transistor; an access transistor coupling the NVM transistor to a corresponding bit line; and a source select transistor coupling the NVM transistor to a common source. The NVM cells are written by a two-phase operation that includes an erase phase and a program phase. A common set of bit line voltages are applied to the bit lines during both the erase and programming phases. The access transistors are turned on and the source select transistors are turned off during the erase and programming phases. A first control voltage is applied to the control gates of the NVM transistors during the erase phase, and a second control voltage is applied to the control gates of the NVM transistors during the program phase. Under these conditions, the average required number of Fowler-Nordheim tunneling operations is reduced. | 11-27-2008 |
Dan Cosmin, Richmond Hill CA
Patent application number | Description | Published |
---|---|---|
20140150581 | POWER SWING DOOR ACTUATOR - In an aspect, a swing door actuation system is provided for moving a door about a vertical axis between open closed positions relative to a vehicle body. The system includes a housing connectable to one of the swing door and the vehicle body, an extensible member that moves relative to the housing, and connects to the other of the swing door and the vehicle body, a motor connected to a gear train that is non-backdrivable, and a normally engaged clutch. The motor is operatively connected to a clutch input end through the gear train. The output end is operatively connected to the extensible member. The clutch is disengageable to disconnect the motor from the extensible member. The clutch has a slip torque that is sufficiently high to prevent movement of the door when the door is exposed to less than a selected external torque and the motor is stopped. | 06-05-2014 |