Patent application number | Description | Published |
20090135151 | HIGH TRANSMITTANCE TOUCH PANEL - A touch panel includes: a transparent substrate; and a transparent multi-layered structure disposed on the substrate and including transparent inner and outer anti-reflection layers and a transparent touch control layer that is sandwiched between the inner and outer anti-reflection layers and that is made from an electrically conductive material. The inner anti-reflection layer has an anti-reflection film. At least one of the outer anti-reflection layer and the anti-reflection film has an optical thickness sufficient for generating destructive interference among reflections from the substrate, the outer anti-reflection layer, the anti-reflection film, and the touch control layer. | 05-28-2009 |
20090135159 | TOUCH PANEL ASSEMBLY - A touch panel assembly includes: a transparent front cover adapted to cover a screen of a display; and a touch control unit including a transparent multi-layered structure deposited on the transparent front cover. The multi-layered structure defines a plurality of transparent sensor areas, each of which is operable to sense an object when the object touches or closely approaches a location on the transparent front cover that corresponds to the respective one of the sensor areas. | 05-28-2009 |
20090135160 | CAPACITIVE TYPE TOUCH PANEL - A capacitive type touch panel includes: a transparent substrate; and a transparent touch control unit disposed on the substrate and including a plurality of spaced apart transparent key pads that are made from a transparent electrically conductive material, and a transparent electrically conductive reference potential member that is associated operatively and electrically with the transparent key pads to generate a charge distribution between two adjacent ones of the transparent key pads, thereby forming virtual key pads among the transparent key pads. | 05-28-2009 |
Patent application number | Description | Published |
20120302079 | Connection unit for fluorescent tubes - A connection unit for fluorescent tubes includes a base connected to each of two ends of a light unit and the base has an extension. Two conductive plates are connected to two reception areas of the extension. A cover is removably connected to the base and has a room and a recessed area is defined in the top of the cover. A rotatable member is removably connected to the recessed area and has a face board which has a reception hole communicating with the room. A shank is connected to the periphery of the reception hole and the rotatable member is rotatable about an axis of the recessed area. The base and the conductive plates are pulled out from the recessed area and the room respectively. | 11-29-2012 |
20120302080 | Connection unit for fluorescent tubes - A connection unit for fluorescent tubes includes a base having an extension which has an opening and an engaging portion is defined along an inner periphery of the opening. A cover is removably mounted to the base and a rotatable member is located in the cover. The cover has a terminal entrance defined in the base portion thereof so that terminals of a fluorescent tube are inserted into the terminal entrance. A shank extends from the base portion and a disk is connected to a distal end of the shank. The disk is engaged with the engaging portion of the base. The extension of the base and the cover position the disk so that the rotatable member is secured when being rotated. | 11-29-2012 |
20130033880 | LAMP TUBE SOCKET STRUCTURE - A lamp tube socket structure includes a base, an elastic element, an abutting element, a cover and a metal clip, and the base has an actuating portion, a support pillar extended transversally from the actuating portion and comprised of two wings, and an elastic element is contained in the support pillar, and the abutting element is passed and installed to the two wings of the support pillar and pushed by the elastic element, and the cover has a covering portion, an embedding hole formed on the covering portion, and the cover is combined with the base, and a metal clip containing portion is formed between the covering portion and the actuating portion. | 02-07-2013 |
20130157492 | ROTATING LAMP TUBE SOCKET STRUCTURE - A rotating lamp tube socket structure includes a seat body, a cover and a rotating element, and the rotating element is pivotally turned with respect to a cover to an installing position or a conducting position, such that when the rotating element is pivotally turned to the installing position, an elastic element is compressed to retract in a direction towards the cover, and when the rotating element is pivotally turned to the conducting position, an elastic resilience of the elastic element props the rotating element to be protruded towards the outside. | 06-20-2013 |
Patent application number | Description | Published |
20110193144 | SEMICONDUCTOR DEVICE HAVING ELEVATED STRUCTURE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes a semiconductor substrate; a gate stack overlying the substrate, a spacer formed on sidewalls of the gate stack, and a protection layer overlying the gate stack for filling at least a portion of a space surrounded by the spacer and the top surface of the gate stack. A top surface of the spacer is higher than a top surface of the gate stack. | 08-11-2011 |
20120009690 | IN-SITU SPECTROMETRY - The present disclosure provides a system for in-situ spectrometry. The system includes a wafer-cleaning machine that cleans a surface of a semiconductor wafer using a cleaning solution. The system also includes a spectrometry machine that is coupled to the wafer-cleaning machine. The spectrometry machine receives a portion of the cleaning solution from the wafer-cleaning machine. The portion of the cleaning solution collects particles from the wafer during the cleaning. The spectrometry machine is operable to analyze a particle composition of a portion of the wafer based on the portion of the cleaning solution, while the wafer remains in the wafer-cleaning machine during the particle composition analysis. | 01-12-2012 |
20130034948 | Method of Manufacturing a Semiconductor Device - A method for fabricating a semiconductor device is disclosed. An exemplary method includes a providing substrate. A dielectric layer is formed over the semiconductor substrate and a stop layer is formed over the dielectric layer. The stop layer and the dielectric layer comprise a different material. The method further includes forming a patterned hard mask layer over the stop layer and etching the semiconductor substrate through the patterned hard mask layer to form a plurality of trenches. The method also includes depositing an isolation material on the semiconductor substrate and substantially filling the plurality of trenches. Thereafter, performing a CMP process on the semiconductor substrate, wherein the CMP process stops on the stop layer. | 02-07-2013 |
20140042491 | GATE ELECTRODE OF FIELD EFFECT TRANSISTOR - This description relates to a gate electrode of a field effect transistor. An exemplary structure for a field effect transistor includes a substrate; a gate electrode over the substrate including a first top surface and a sidewall; a source/drain (S/D) region at least partially disposed in the substrate on one side of the gate electrode; a spacer on the sidewall distributed between the gate electrode and the S/D region; and a contact etch stop layer (CESL) adjacent to the spacer and further comprising a portion extending over the S/D region, wherein the portion has a second top surface substantially coplanar with the first top surface. | 02-13-2014 |
20140162446 | METHOD FOR REMOVING HARD MASK OXIDE AND MAKING GATE STRUCTURE OF SEMICONDUCTOR DEVICES - A method includes forming a first gate above a semiconductor substrate, forming a hard mask on the first gate, and forming a contact etch stop layer (CESL) on the hard mask. No hard mask is removed between the step of forming the hard mask and the step of forming the CESL. The method further includes forming an interlayer dielectric (ILD) layer over the CESL, and performing one or more CMP processes to planarize the ILD layer, remove the CESL on the hard mask, and remove at least one portion of the hard mask. | 06-12-2014 |
20140191333 | METHOD OF PROTECTING AN INTERLAYER DIELECTRIC LAYER AND STRUCTURE FORMED THEREBY - This description relates to a method including forming an interlayer dielectric (ILD) layer and a dummy gate structure over a substrate and forming a cavity in a top portion of the ILD layer. The method further includes forming a protective layer to fill the cavity. The method further includes planarizing the protective layer. A top surface of the planarized protective layer is level with a top surface of the dummy gate structure. This description also relates to a semiconductor device including first and second gate structures and an ILD layer formed on a substrate. The semiconductor device further includes a protective layer formed on the ILD layer, the protective layer having a different etch selectivity than the ILD layer, where a top surface of the protective layer is level with the top surfaces of the first and second gate structures. | 07-10-2014 |
20140197499 | Self Aligned Contact Formation - The present disclosure relates to methods of forming a self-aligned contact and related apparatus. In some embodiments, the method forms a plurality of gate lines interspersed between a plurality of dielectric lines, wherein the gate lines and the dielectric lines extend in a first direction over an active area. One or more of the plurality of gate lines are into a plurality of gate line sections aligned in the first direction. One or more of the plurality of dielectric lines are cut into a plurality of dielectric lines sections aligned in the first direction. A dummy isolation material is deposited between adjacent dielectric sections in the first direction and between adjacent gate line sections in the first direction. One or more self-aligned metal contacts are then formed by replacing a part of one or more of the plurality of dielectric lines over the active area with a contact metal. | 07-17-2014 |
20140213048 | Method of Making a FinFET Device - A FinFET device is fabricated by first receiving a FinFET precursor. The FinFET precursor includes a substrate, fins on the substrate, isolation regions on sides of the fins and dummy gate stacks on the substrate including wrapping a portion of the fin, which is referred to as a gate channel region. The dummy gate stacks is removed to form a gate trench and a gate dielectric layer is deposited in the gate trench. A metal stressor layer (MSL) is conformably deposited on the gate dielectric layer. A capping layer is deposited on the MSL. A thermal treatment is applied to the MSL to achieve a volume expansion. Then the capping layer is removed and a metal gate (MG) is formed on the MSL. | 07-31-2014 |
20140256124 | IN-SITU METAL GATE RECESS PROCESS FOR SELF-ALIGNED CONTACT APPLICATION - A method of producing a metal gate structure. The method includes forming a gate structure above a semiconductor substrate and performing one or more chemical metal planarization (CMP) processes to planarize the formed gate structure using a CMP tool. An in situ gate etching process is performed in a CMP cleaner of the CMP tool to form a gate recess. A contact etch stop layer (CESL) can then be deposited in the formed gate recess and one or more CMP processes performed to planarize the CESL. | 09-11-2014 |
20150108651 | SELF ALIGNED CONTACT FORMATION - The present disclosure relates to methods of forming a self-aligned contact and related apparatus. In some embodiments, the method forms a plurality of gate lines interspersed between a plurality of dielectric lines, wherein the gate lines and the dielectric lines extend in a first direction over an active area. One or more of the plurality of gate lines are into a plurality of gate line sections aligned in the first direction. One or more of the plurality of dielectric lines are cut into a plurality of dielectric lines sections aligned in the first direction. A dummy isolation material is deposited between adjacent dielectric sections in the first direction and between adjacent gate line sections in the first direction. One or more self-aligned metal contacts are then formed by replacing a part of one or more of the plurality of dielectric lines over the active area with a contact metal. | 04-23-2015 |
20150129795 | CHEMICAL MECHANICAL POLISHING METHOD USING SLURRY COMPOSITION CONTAINING N-OXIDE COMPOUND - The present disclosure relates to a chemical mechanical polishing (CMP) slurry composition that provides for a high metal to dielectric material selectivity along with a low rate of metal recess formation. In some embodiments, the disclosed slurry composition has an oxidant and an etching inhibitor. The oxidant has a compound with one or more oxygen molecules. The etching inhibitor has a nitrogen-oxide compound. The etching inhibitor reduces the rate of metal and dielectric material (e.g., oxide) removal, but does so in a manner that reduces the rate of dielectric material removal by a larger amount, so as to provide the slurry composition with a high metal (e.g., germanium) to dielectric material removal selectivity and with a low rate of metal recess formation. | 05-14-2015 |
20150129990 | SEMICONDUCTOR DEVICE HAVING ELEVATED STRUCTURE - A semiconductor device includes a gate stack overlying a substrate. The semiconductor device further includes a spacer on sidewalls of the gate stack, where a top surface of the spacer is above a top surface of the gate stack. Additionally, the semiconductor device includes a protection layer overlying the gate stack and filling at least a portion of a space surrounded by the spacer above the top surface of the gate stack. Furthermore, the semiconductor device includes a contact hole over the spacer, where the contact hole extends over the gate stack, and where a sidewall of the contact hole has a step-wise shape. | 05-14-2015 |
20150221751 | METHOD OF MAKING A FINFET DEVICE - A FinFET device is fabricated by first receiving a FinFET precursor. The FinFET precursor includes a substrate, fins on the substrate, isolation regions on sides of the fins and dummy gate stacks on the substrate including wrapping a portion of the fin, which is referred to as a gate channel region. The dummy gate stacks is removed to form a gate trench and a gate dielectric layer is deposited in the gate trench. A metal stressor layer (MSL) is conformably deposited on the gate dielectric layer. A capping layer is deposited on the MSL. A thermal treatment is applied to the MSL to achieve a volume expansion. Then the capping layer is removed and a metal gate (MG) is formed on the MSL. | 08-06-2015 |
Patent application number | Description | Published |
20130085362 | METHOD FOR IDENTIFYING STIMULATION TARGET - A method for identifying a stimulation target is provided, which uses microelectrode recording and electrical impedance tomography techniques together in a composite probe. The composite probe includes at least a microelectrode recording sensor and a plurality of microelectrodes, so that after the composite probe is guided and implanted to a depth suitable for the stimulation target based on microelectrode recording signals, tissue structures surrounding the composite probe are delineated by using the plurality of microelectrodes, and the boundary of the stimulation target and the precise location of the composite probe within the stimulation target are determined. Accordingly, the present invention provides a quick and accurate direction for surgeons, eliminating the problem of not knowing the exact location of the implanted probe within the stimulation target as in the case during deep brain stimulation surgeries. | 04-04-2013 |
20130172718 | METHOD FOR IMPROVING IMAGING RESOLUTION OF ELECTRICAL IMPEDANCE TOMOGRAPHY - The present disclosure provides a method for improving imaging resolution of electrical impedance tomography (EIT). More specifically, the present disclosure forms virtual electrode(s) using an electric current steering technique, which is used to improve imaging resolution of an EIT system without physically increasing a number of conducting electrodes. The EIT system of the present disclosure may includes a plurality of conducting electrodes, at least one signal generator, at least one signal receiver and at least one electric current steering device. In other words, the present disclosure applies both the electric current steering technique and the virtual electrode technique to EIT. Consequently, imaging resolution of EIT can be improved without physically increasing the number of conducting electrodes. | 07-04-2013 |
Patent application number | Description | Published |
20120276726 | METHOD FOR FABRICATING SEMICONDUCTOR POWER DEVICE - A method for fabricating a semiconductor power device includes the following steps. First, a substrate having thereon at least a semiconductor layer and a pad layer is provided. Then, at least a trench is etched into the pad layer and the semiconductor layer followed by depositing a dopant source layer in the trench and on the pad layer. A process is carried out thermally driving in dopants of the dopant source layer into the semiconductor layer. A rapid thermal process is performed to mend defects in the dopant source layer and defects between the dopant source layer and the semiconductor layer. Finally, a polishing process is performed to remove the dopant source layer from a surface of the pad layer. | 11-01-2012 |
20120289037 | METHOD FOR FABRICATING SEMICONDUCTOR POWER DEVICE - A method for fabricating a semiconductor power device includes the following steps. First, a substrate having at least a semiconductor layer and a pad layer thereon is provided. At least a trench is etched into the pad layer and the semiconductor layer. Then, a dopant source layer is deposited in the trench and on the pad layer followed by thermally driving in dopants of the dopant source layer into the semiconductor layer. A polishing process is performed to remove the dopant source layer from a surface of the pad layer and a thermal oxidation process is performed to eliminate micro-scratches formed during the polishing process. Finally, the pad layer is removed to expose the semiconductor layer. | 11-15-2012 |
20140118715 | Laser Interference Lithography Apparatus Using Fiber as Spatial Filter and Beam Expander - In a laser interference lithography apparatus, a laser source provides a first laser beam, and an optics assembly is optically coupled to the laser source and receives and processes the first laser beam into one or multiple second laser beams. An exposure stage carries a to-be-exposed object. The fiber assembly receives and processes the second laser beam(s) into one or multiple single mode and stable coherent third laser beams without spatial noise. An interference pattern is generated on the to-be-exposed object using the third laser beam(s). The apparatus is configured without a pin hole spatial filter and a beam expander being disposed on an optical path from an output end of the laser source to the exposure stage. | 05-01-2014 |
Patent application number | Description | Published |
20080197885 | Circuit for detecting maximal frequency of pulse frequency modulation and method thereof - The circuit for detecting the maximal frequency of the pulse frequency modulation includes an oscillator-controlling unit, a delay circuit and a master-slave register. The oscillator-controlling unit is connected to an oscillator, which generates the pulse frequency modulation signals, and includes a first-half pulse-generating module and a second-half pulse-generating module. The delay circuit is connected to the second-half pulse-generating module. The master-slave register includes a clock, an input end and an output end, wherein the input end is connected to the oscillator-controlling unit, and the clock is connected to the delay circuit. | 08-21-2008 |
20080205099 | Power transistor circuit and the method thereof - The power transistor circuit with high-voltage endurance includes a first power transistor, a second power transistor and an enabling circuit. The first power transistor includes a first voltage endurance and a first inner resistance, while the second power transistor includes a second voltage endurance and a second inner resistance. The first voltage endurance and the first inner resistance are smaller than the second voltage endurance and the second inner resistance, respectively. The drain of the second power transistor is connected to the drain of the first power transistor and the enabling circuit. The enabling circuit enables the second power transistor first, and when the drain voltage of the first power transistor is smaller than the first endurance, the enabling circuit then enables the first power transistor. | 08-28-2008 |
20080218284 | Circuit and method for switching PFM and PWM - The switching method between pulse frequency modulation and pulse width modulation signals is first based on an output voltage of a power transistor to generate a corresponding pulse frequency modulation signal. Next, it is determined whether the corresponding pulse frequency modulation signal has reached its maximal frequency. If so, the initial pulse width modulation signal is adjusted to have the same width as the pulse frequency modulation signal. Thereafter, the adjusted pulse width modulation signal is outputted. | 09-11-2008 |
20080224673 | Circuit for starting up a synchronous step-up DC/DC converter and the method thereof - The low voltage circuit for starting up a synchronous step-up DC/DC converter, which connects to a voltage source through an inductor, includes a P-type power transistor, an N-type power transistor and a controller. The P-type power transistor includes a body diode, and one end of the P-type power transistor acts as a power source of an oscillator. The N-type power transistor connects the P-type power transistor in series, and both of the power transistors are not enabled at the same time. The oscillator electrically connects to the controller, which enables the P-type power transistor at initialization time, and enables the N-type power transistor a period after the initialization time. | 09-18-2008 |
20080231348 | Circuit for fixing peak current of an inductor and method thereof - The circuit for fixing the peak current of an inductor includes an operating current, a ramp-type boost converter and a comparator. The magnitude of the operating current is proportional to that of the voltage source of the inductor. The ramp-type boost converter is connected to the operating current. One input end of the comparator is connected to a reference voltage, and the other end is connected to the output of the ramp-type boost converter. The output of the comparator is connected to the gate of a power transistor, which controls the turn-on time of the inductor. | 09-25-2008 |
20080231386 | Oscillation circuit and the method for using the same - The oscillation circuit includes an output current mirror, a P-N complementary current mirror, a P-type current mirror and an N-type current mirror. The P-N complementary current mirror has the same structure as the output current mirror but has current that is only 1/k times the current of the output current mirror, wherein k is greater than 1. The P-type current mirror connects to the P-N complementary current mirror, and has current that is m times the current of the P-N complementary current mirror, where m is greater than 1. The N-type current mirror has one end connected to the P-type current mirror and another end connected to the output current mirror. The N-type current mirror has current that is n times the current of the P-type current mirror, where | 09-25-2008 |
20120025860 | Burn-in socket and testing fixture using the same - A burn-in socket for carrying an electronic device to let the electronic device electrically connect to a circuit board via the burn-in socket is provided. The electronic device has a body and at least a lead. The burn-in socket comprises a frame and a carrier, the frame has an opening and a plurality of first aligning portions, wherein the opening fits onto the contour of the body, and the first aligning portions surrounds the opening. The carrier has a plurality of second aligning portions. The frame is assembled to the carrier with the conjunction of the first aligning portions and the second aligning portions. The body is capable of fitting into the opening to let the lead electrically connect to the circuit board via the carrier. | 02-02-2012 |
Patent application number | Description | Published |
20090216946 | RAID1 SYSTEM AND READING METHOD FOR ENHANCING READ PERFORMANCE - Concerning the operations of a redundant array of independent disks 1 system, a reading process is carried out by skipping the even-address storage units in a first storage device, sequentially fetching the data of the odd-address storage units in the first storage device for forming a first data stream, skipping the odd-address storage units in a second storage device, sequentially fetching the data of the even-address storage units in the second storage device for forming a second data stream, and merging the first data stream and the second data stream for generating a readout data stream. | 08-27-2009 |
20090254741 | HOST PERIPHERAL SYSTEM AND METHOD FOR LOADING AN EXTERNAL PROGRAM CODE TO A HOST FOR SETTING UP A TRANSMISSION MECHANISM WHEN BOOTING - When booting a host, a host peripheral system sends a boot code to the host for controlling the booting operation of the host via a serial transmission line, and loads an external program code into the host. After setting up a transmission mechanism through executing the external program code, the host can forward a write command to the host peripheral system for writing the data provided by the external program code to the command identification sector of the non-volatile memory of the host peripheral system, and the host peripheral system is capable of identifying the data as a command and executes functional operations corresponding to the command. After finishing the functional operations, the host peripheral system forwards a finish signal to the host, and the host is able to send a read command for fetching the data signal generated in the functional operations. | 10-08-2009 |
20090287882 | RAID_5 CONTROLLER AND ACCESSING METHOD WITH DATA STREAM DISTRIBUTION AND AGGREGATION OPERATIONS BASED ON THE PRIMITIVE DATA ACCESS BLOCK OF STORAGE DEVICES - By taking advantage of parallel data processing and transmission techniques, the data access rate of a redundant array of independent disks (RAID) level 5 can be boosted significantly. A data distribution and aggregation unit is utilized to distribute a data stream into a plurality of data sub-streams based on the primitive data access block of storage devices as a processing unit of data writing, or to aggregate a plurality of data sub-streams to form a data stream based on the primitive data access block of storage devices as a processing unit of data reading. An exclusive OR operation unit capable of parallel data processing is introduced for performing data processing on the plurality of data sub-streams simultaneously. The data transmission of each data sub-stream is controlled individually by one of a plurality of transmission controllers. | 11-19-2009 |
20110022744 | Storage Control Method and Related Storage Control Device for a Computer System - A storage control method for a computer system for automatically executing off line at a proper time includes a storage controller generating a command for accessing a storage device, receiving and transmitting the command through a port multiplier, and the port multiplier performing off line when a ready packet is not received from the storage device or the storage device is absent. | 01-27-2011 |
20110119416 | Storage Control Method and Related Storage Control Device for a Computer System - A storage control method for a computer system for automatically executing connection at a proper time includes a storage control device generating a command for accessing a storage device, outputting the command through a port multiplier, and the computer system transmitting a signal to the port multiplier to form a connection state with the storage control device when a connection request is received by the storage control device. | 05-19-2011 |
20110125963 | ELECTRONIC DEVICE WITH DATA BACKUP/RESTORE CAPABILITY - An electronic device with data backup/restore capability includes a connection port, an internal storage device, a storage device controller, a processor and a bridge circuit. The internal storage device is used for storing data. The storage device controller is coupled to the connection port and the internal storage device, for controlling data accessing and data backup/restore operations of the internal storage device. The processor is used for controlling the operation of the electronic device. The bridge circuit is coupled between the storage device controller and the processor. | 05-26-2011 |