Patent application number | Description | Published |
20110267757 | TABLET COMPUTER CASE AND ASSOCIATED METHODS - Tablet computer cases and associated methods are disclosed and described. In one embodiment, a tablet computer case may include a first panel configured to releasably engage and hold a tablet computer of a predetermined size and shape, a second panel having a keyboard a hinge rotatably attaching the two panels, and a communication connector that allows the keyboard to communicate with the tablet computer. | 11-03-2011 |
20120106059 | Tablet Computer Case and Associated Methods - Tablet computer cases and associated methods are disclosed and described. In one embodiment, a tablet computer case may include a first panel configured to releasably engage and hold a tablet computer of a predetermined size and shape, a second panel having a keyboard a hinge rotatably attaching the two panels, and a communication connector that allows the keyboard to communicate with the tablet computer. | 05-03-2012 |
20120106060 | Tablet Computer Case and Associated Methods - Tablet computer cases and associated methods are disclosed and described. In one embodiment, a tablet computer case may include a first panel configured to releasably engage and hold a tablet computer of a predetermined size and shape, a second panel having a keyboard a hinge rotatably attaching the two panels, and a communication connector that allows the keyboard to communicate with the tablet computer. | 05-03-2012 |
20120106061 | Tablet Computer Case and Associated Methods - Tablet computer cases and associated methods are disclosed and described. In one embodiment, a tablet computer case may include a first panel configured to releasably engage and hold a tablet computer of a predetermined size and shape, a second panel having a keyboard a hinge rotatably attaching the two panels, and a communication connector that allows the keyboard to communicate with the tablet computer. | 05-03-2012 |
20120106062 | Tablet Computer Case and Associated Methods - Tablet computer cases and associated methods are disclosed and described. In one embodiment, a tablet computer case may include a first panel configured to releasably engage and hold a tablet computer of a predetermined size and shape, a second panel having a keyboard a hinge rotatably attaching the two panels, and a communication connector that allows the keyboard to communicate with the tablet computer. | 05-03-2012 |
20120106078 | Tablet Computer Case and Associated Methods - Tablet computer cases and associated methods are disclosed and described. In one embodiment, a tablet computer case may include a first panel configured to releasably engage and hold a tablet computer of a predetermined size and shape, a second panel, and a hinge rotatably attaching the two panels. | 05-03-2012 |
Patent application number | Description | Published |
20090111227 | Method for Forming Trench Gate Field Effect Transistor with Recessed Mesas Using Spacers - A method for forming a field effect transistor with an active area and a termination region surrounding the active area includes forming a well region in a first silicon region, where the well region and the first silicon region are of opposite conductivity type. Gate trenches extending through the well region and terminating within the first silicon region are formed. A recessed gate is formed in each gate trench. A dielectric cap is formed over each recessed gate. The well region is recessed between adjacent trenches to expose upper sidewalls of each dielectric cap. A blanket source implant is carried out to form a second silicon region in an upper portion of the recessed well region between every two adjacent trenches. A dielectric spacer is formed along each exposed upper sidewall of the dielectric cap, with every two adjacent dielectric spacers located between every two adjacent gate trenches forming an opening over the second silicon region. The second silicon region is recessed through the opening between every two adjacent dielectric spacers so that only portions of the second silicon region directly below the dielectric spacers remain. The remaining portions of the second silicon region form source regions. | 04-30-2009 |
20100015769 | Power Device With Trenches Having Wider Upper Portion Than Lower Portion - A method of forming a semiconductor device includes the following. A masking layer with opening is formed over a silicon layer. The silicon layer is isotropically etched through the masking layer openings so as to remove bowl-shaped portions of the silicon layer, each of which includes a middle portion and outer portions extending directly underneath the masking layer. The outer portions form outer sections of corresponding trenches. Additional portions of the silicon layer are removed through the masking layer openings so as to form a middle section of the trenches which extends deeper into the silicon layer than the outer sections of the trenches. A first doped region of a first conductivity type is formed in an upper portion of the silicon layer. An insulating layer is formed within each trench, and extends directly over a portion of the first doped region adjacent each trench sidewall. Silicon is removed from adjacent each trench until, of the first doped region, only the portions adjacent the trench sidewalls remain. The remaining portions of the first doped region adjacent the trench sidewalls form source regions which are self-aligned to the trenches. | 01-21-2010 |
20100317168 | LATERAL DRAIN MOSFET WITH IMPROVED CLAMPING VOLTAGE CONTROL - A lateral MOSFET having a substrate, first and second epitaxial layers grown on the substrate and a gate electrode formed on a gate dielectric which in turn is formed on a top surface of the second epitaxial layer. The second epitaxial layer comprises a drain region which extends to a top surface of the epitaxial layer and is proximate to a first edge of the gate electrode, a source region which extends to a top surface of the second epitaxial layer and is proximate to a second edge of the gate electrode, a heavily doped body under at least a portion of the source region, and a lightly doped well under the gate dielectric located near the transition region of the first and second epitaxial layers. A PN junction between the heavily doped body and the first epitaxial region under the heavily doped body has an avalanche breakdown voltage that is substantially dependent on the doping concentration in the upper portion of the first epitaxial layer that is beneath the heavily doped body. | 12-16-2010 |
20110003449 | Power Device With Trenches Having Wider Upper Portion Than Lower Portion - A method of forming a semiconductor device includes the following. Removing portions of a silicon layer such that a trench having sidewalls which fan out near the top of the trench to extend directly over a portion of the silicon layer is formed in the silicon layer; and forming source regions in the silicon layer adjacent the trench sidewall such that the source regions extend into the portions of the silicon layer directly over which the trench sidewalls extend. | 01-06-2011 |
20120119291 | Power device with self-aligned source regions - A field effect transistor (FET) includes a plurality of trenches extending into a silicon layer, each trench having upper sidewalls that fan out. Contact openings extend into the silicon layer between adjacent trenches such that each trench and an adjacent contact opening form a common upper sidewall portion. Body regions extend between adjacent trenches. Source regions that are self-aligned to corresponding trenches extend in the body regions adjacent opposing sidewalls of each trench, and have a conductivity type opposite that of the body regions. | 05-17-2012 |
20120156845 | METHOD OF FORMING A FIELD EFFECT TRANSISTOR AND SCHOTTKY DIODE - A method for forming a field effect transistor and Schottky diode includes forming a well region in a first portion of a silicon region where the field effect transistor is to be formed but not in a second portion of the silicon region where the Schottky diode is to be formed. Gate trenches are formed extending into the silicon region. A recessed gate is formed in each gate trench. A dielectric cap is formed over each recessed gate. Exposed surfaces of the well region are recessed to form a recess between every two adjacent trenches. Without masking any portion of the active area, a zero-degree blanket implant is performed to form a heavy body region of the second conductivity type in the well region between every two adjacent trenches. | 06-21-2012 |
20120319197 | FIELD EFFECT TRANSISTOR AND SCHOTTKY DIODE STRUCTURES - In accordance with an embodiment a structure can include a monolithically integrated trench field-effect transistor (FET) and Schottky diode. The structure can include a first gate trench extending into a semiconductor region, a second gate trench extending into the semiconductor region, and a source region flanking a side of the first gate trench. The source region can have a substantially triangular shape, and a contact opening extending into the semiconductor region between the first gate trench and the second gate trench. The structure can include a conductor layer disposed in the contact opening to electrically contact the source region along at least a portion of a slanted sidewall of the source region, and the semiconductor region along a bottom portion of the contact opening. The conductor layer can form a Schottky contact with the semiconductor region. | 12-20-2012 |
20140203355 | FIELD EFFECT TRANSISTOR AND SCHOTTKY DIODE STRUCTURES - In accordance with an embodiment a structure can include a monolithically integrated trench field-effect transistor (FET) and Schottky diode. The structure can include a first gate trench extending into a semiconductor region, a second gate trench extending into the semiconductor region, and a source region flanking a side of the first gate trench. The source region can have a substantially triangular shape, and a contact opening extending into the semiconductor region between the first gate trench and the second gate trench. The structure can include a conductor layer disposed in the contact opening to electrically contact the source region along at least a portion of a slanted sidewall of the source region, and the semiconductor region along a bottom portion of the contact opening. The conductor layer can form a Schottky contact with the semiconductor region. | 07-24-2014 |