Rachamadugu
Arun Rachamadugu, Atlanta, GA US
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20090140784 | HIGH-SPEED PULSE SHAPING FILTER SYSTEMS AND METHODS - A first system and method relates to an analog current-mode method using branch systems. In the analog current-mode implementation, multiple branches systems can be scaled according to filter coefficients and switched using known data points. Positive coefficients can add current to the summing node, while negative coefficients can remove current from the summing node. Switches can be implemented with quick charge/discharge paths in order to operate at very high data rates. A second system and method relates to a digital look-up table based high-speed implementation. In the digital implementation, outputs can be pre-calculated as an n-bit output word that drives an n-bit DAC. Each bit of the n-bit word can then described as an independent function of the known data points. Each such function can be implemented as a high-speed combinational logic block. Both systems and methods enable the implementation of pulse shaping filters for multi-gigabit per second data transmission. | 06-04-2009 |
Raghavendra Rachamadugu, Hyderabad IN
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20080295085 | INTEGRATED CODE REVIEW TOOL - A code review tool system includes a developer on a developer node, a reviewer on a reviewer node, and a server on a server node. The developer node and the reviewer node include an integrated code review tool. The integrated code review tool includes functionality for a developer to specify source code files to be reviewed and a list of reviewer identifiers. The integrated code review tool also includes functionality to associate the reviewer's comments and/or proposed code changes with context information identifying a location in the source code files. The reviewer's comments, proposed code changes, and associated context information is sent to the developer. The developer may then see the reviewer's comments and proposed code changes in context with the location in the source code to which the comments and code changes pertain. | 11-27-2008 |
Raghavendra Rachamadugu, Sunnyvale, CA US
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20150178118 | GUEST CUSTOMIZATION - A system for guest customization includes a processor and a data storage device. A service operating system is stored on the data storage device that, when executed by the processor, boots a virtual machine into maintenance mode. A response file creation module is stored on the storage device that, when executed by the processor, creates a response file. A customization agent is embedded within the service operating system that when executed by the processor on its startup, automatically performs customizations based on the response file including at least one of including adding or removing files within the data storage device and injecting main operating system or virtual machine agent startup scripts to complete customization once the virtual machine is rebooted into the main operating system. | 06-25-2015 |
Raghavendra Rachamadugu, Fremont, CA US
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20140040887 | CUSTOMIZED VIRTUAL MACHINE CREATION - A method of creating a customized virtual machine comprises, with a processor, booting a virtual machine into a service operating system, with a customization agent, customizing a main operating system while the virtual machine is in maintenance mode, and rebooting the virtual machine into the main operating system of the virtual machine. A computer program product for creating a customized virtual machine comprises a computer readable storage medium comprising computer usable program code embodied therewith, the computer usable program code comprising computer usable program code to, when executed by a processor, boot a virtual machine into a service operating system, and computer usable program code to, when executed by a processor, customize a main virtual operating system while the virtual machine is in maintenance mode. | 02-06-2014 |
Sreenivas Rachamadugu, Leesburg, VA US
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20080219638 | Method and system for dynamic control of digital media content playback and advertisement delivery - An approach provides control of digital media. A stream of digital media that includes an advertisement is received. The stream is selectively skipped to avoid the advertisement. In addition, the amount of advertisement played back is tracked. Further, tracking information is generated based on the tracking. | 09-11-2008 |
20110217023 | DIGITAL MEDIA ASSET MANAGEMENT SYSTEM AND METHOD FOR SUPPORTING MULTIPLE USERS - An approach provides editing of digital media. A platform, as maintained by a service provider, provides a remote proxy editing capability of a plurality of media streams. A first one of the media streams is transmitted to a player of a first customer of the service provider. Further, the method comprises transmitting a second one of the media streams to a player of a second customer of the service provider. | 09-08-2011 |
20110274410 | METHOD AND SYSTEM FOR DYNAMIC CONTROL OF DIGITAL MEDIA CONTENT PLAYBACK AND ADVERTISEMENT DELIVERY - An approach provides control of digital media. A stream of digital media that includes an advertisement is received. The stream is selectively skipped to avoid the advertisement. In addition, the amount of advertisement played back is tracked. Further, tracking information is generated based on the tracking. | 11-10-2011 |
20120084404 | METHOD AND SYSTEM FOR PROVIDING A PERSONAL VIDEO RECORDER UTILIZING NETWORK-BASED DIGITAL MEDIA CONTENT - An approach provides for recording and editing digital media. A digital media stream is generated from an input signal (such as a live broadcast feed). The digital media stream is transmitted to a browser application configured to concurrently record and edit the digital media stream. | 04-05-2012 |
20140059575 | METHOD AND SYSTEM FOR PROVIDING A PERSONAL VIDEO RECORDER UTILIZING NETWORK-BASED DIGITAL MEDIA CONTENT - An approach provides for recording and editing digital media. A digital media stream is generated from an input signal (such as a live broadcast feed). The digital media stream is transmitted to a browser application configured to concurrently record and edit the digital media stream. | 02-27-2014 |
Vinod Rachamadugu, Andhra Pradesh IN
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20130322194 | Conditional Read-Assist Feature to Accelerate Access Time in an Electronic Device - An electronic storage device includes a bit cell circuit, feedback circuit, and read accelerator circuit. The bit cell circuit is adapted for connection with true and complementary bit lines. The feedback circuit includes a first transistor which is coupled to a first voltage potential and responsive to the complementary bit line. The read accelerator circuit includes second, third, and fourth transistors coupled between the feedback circuit and a second voltage potential. The second transistor is responsive to a read line, the third transistor is responsive to the true bit line, and the fourth transistor is responsive to the complementary bit line. The read accelerator circuit is configured to provide a discharge path for at least one of the true bit line and the complementary bit line during a read access of the bit cell. Embodiments of a corresponding electronic read access accelerator device and method are also provided. | 12-05-2013 |
Vinod Rachamadugu, Bangalore IN
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20150103604 | MEMORY ARRAY ARCHITECTURES HAVING MEMORY CELLS WITH SHARED WRITE ASSIST CIRCUITRY - A memory device includes a memory array having a plurality of memory cells each having first and second power supply nodes, first and second virtual power supply nodes, a latch circuit, and a write assist circuit. The latch circuit includes a first and second inverters in a cross-coupled inverter configuration. The first inverter is connected between the first virtual power supply node and the second power supply node, and the second inverter is connected between the second virtual power supply node and the second power supply node. The write assist circuit selectively supplies power to the first and second virtual power supply nodes during memory access operations, and is controlled by a first control signal to switchably connect the first power supply node to and from the first and second virtual power supply nodes, and a second control signal to switchably connect the one or both of the first and second virtual power supply nodes to a virtual power supply node of an adjacent memory cell of an adjacent row in the memory array. | 04-16-2015 |
Vinod Rachamadugu, Kurnool IN
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20120155151 | Memory Device Having Memory Cells with Enhanced Low Voltage Write Capability - A memory device includes a memory array comprising a plurality of memory cells. At least a given one of the memory cells comprises a pair of cross-coupled inverters and associated write assist circuitry. The write assist circuitry comprises first switching circuitry coupled between a supply node of a device of the first inverter and a supply node of the memory cell, and second switching circuitry coupled between a supply node of a device of the second inverter and the supply node of the memory cell. The first and second switching circuitry are separately controlled such that during a write operation of the memory cell the supply node of one of the devices is connected to the supply node of the memory cell while the supply node of the other device is not connected to the supply node of the memory cell but is instead permitted to float. | 06-21-2012 |
20120206951 | HIGH DENSITY CAM ARRAY ARCHITECTURES WITH ADAPTIVE CURRENT CONTROLLED MATCH-LINE DISCHARGE - An integrated circuit having a CAM array includes a plurality of CAM cells organized in rows and columns where each row corresponds to an address word and each column corresponds to a bit position, and a match line for each row connected to be shared by CAM cells in that row. The CAM array also includes a feedback circuit for each row connected to limit a discharge voltage for a corresponding match line in that row. In another aspect, a method of operating an integrated circuit having a CAM array includes organizing a plurality of CAM cells in rows and columns where each row corresponds to an address word and each column corresponds to a bit position, and sharing a match line with CAM cells in each row. The method also includes limiting a discharge voltage for the match line. | 08-16-2012 |
20120212996 | MEMORY DEVICE HAVING MEMORY CELLS WITH WRITE ASSIST FUNCTIONALITY - A memory device includes a memory array comprising a plurality of memory cells. At least a given one of the memory cells comprises a pair of cross-coupled inverters and associated write assist circuitry. The write assist circuitry comprises first switching circuitry coupled between a supply node of a device of the first inverter and a supply node of the memory cell, and second switching circuitry coupled between a supply node of a device of the second inverter and the supply node of the memory cell. The first and second switching circuitry are separately controlled, with the first switching circuitry being controlled using a wordline and an uncomplemented bitline of the memory device, and the second switching circuitry being controlled using the wordline and a complemented bitline of the memory device. | 08-23-2012 |
20130170273 | Content-Addressable Memory Architecture for Routing Raw Hit Lines Using Minimal Base Metal Layers - A CAM circuit includes a plurality of core memory cells, each cell including comparison logic for generating a local match signal based on a comparison between stored data in the cell and a compare value. The CAM circuit includes a plurality of local match lines, each local match line coupled with a corresponding cell and adapted to convey the local match signal generated by the cell. The CAM circuit includes combination logic for receiving respective local match signals generated by a subset of the cells and for generating an output word match signal having a value indicative of the local match signals. The subset of cells is arranged with at least one block having a word size that is limited based on available space for routing tracks used to convey the local match signals and at least one word match signal in a base metal layer across the cells. | 07-04-2013 |
20140153346 | Read Assist Scheme for Reducing Read Access Time in a Memory - A read circuit includes a precharge circuit, coupled with at least a subset of bit lines and a sense circuit in a memory, and a transmission gate. The precharge circuit receives a first control signal and is operative during a first mode to set the bit lines to a first voltage level and to set an input to the sense circuit to a second voltage level. The transmission gate connects a given one of the bit lines with the sense circuit during a second mode as a function of a second control signal, such that when reading a first logic level from the selected memory cell, when the input of the sense circuit is connected with the given bit line, the given bit line is discharged to at least a third voltage, which is between the first and second voltage levels, thereby reducing a read access time in the memory. | 06-05-2014 |