Patent application number | Description | Published |
20110001600 | TWO- OR MULTIPHASE TRANSFORMER - The disclosure relates to a transformer having a yoke which has a crosspiece and at least two limbs, over which limbs a coil is placed in each case, and having at least one carrier on which the crosspiece is fixed and which has bearing faces for the coils. At least two supporting blocks for each coil are mounted on each bearing surface. The supporting blocks are fitted with elastic compensation elements on the coil-side carrying face and have, on their longitudinal side faces, which run perpendicular to a carrying surface, at least one strip which extends the creepage path and runs in the longitudinal direction and parallel to the carrying surface of the supporting block. | 01-06-2011 |
20110032064 | METHOD FOR PRODUCTION OF A WINDING BLOCK FOR A COIL OF A TRANSFORMER AND WINDING BLOCK PRODUCED IN THIS WAY - A method is disclosed for production of a winding block for a coil of a transformer, having at least one winding composed of electrically conductive wire or strip material with a plurality of turns. An insulating layer is composed of electrically insulating fiber material with a specific number of windings of the insulating fiber material. The turns composed of electrical conductive material are fitted independently of the turns of the insulating material and, after a predetermined number of turns of electrically conductive material have been fitted, a smaller number of turns of electrically insulating material are fitted over the same section onto these turns of electrically conductive material, such that electrically insulating material which remains before reaching a number of turns of electrically conductive material is used as edge insulation. | 02-10-2011 |
20110163835 | WINDING FOR A TRANSFORMER - A transformer has a coil including a plurality of layers of wound conductive material and layers in between made of wound insulation material. The layers of insulation material are wound in stages. The layers of insulation material are applied at an angle to the winding axis of the coil. | 07-07-2011 |
20110221556 | TRANSFORMER - A transformer is provided with at least one core leg on which three windings are arranged side by side, whose discharges are designed to be mutually insulated. Each winding is formed by a near-core low-voltage winding, which are each wound by an associated high-voltage winding, and the discharges of the low-voltage windings are axially designed, so that the lateral spacing of the windings to each other is minimized. | 09-15-2011 |
20130293340 | TRANSFORMER WINDING - An exemplary transformer winding including at least two hollow-cylindrical, axially adjacent winding modules, which are arranged about a common winding axis and have an electrical conductor wound in layers, and a common electrical insulting layer, through which the winding modules are enveloped. The insulating layer has at least one annular, radial depression or annular, radial elevation, which is salient transversely to the winding axis on the radial outer face of said insulating layer. | 11-07-2013 |
Patent application number | Description | Published |
20140027880 | INTEGRATED INDUCTOR FOR INTEGRATED CIRCUIT DEVICES - A three-dimensional inductor is formed in an integrated circuit die using conductive through-body-vias which pass through the body of the die and contact one or more metal interconnect layers on the front side of the die and terminate on the back side of the die. In another embodiment, the through-body-vias may pass through a dielectric material disposed in a plug in the body of the die. In yet another aspect, a transformer may be formed by coupling multiple inductors formed using through-body-vias. In still another aspect, a three-dimensional inductor may include conductors formed of stacks of on chip metallization layers and conductive through-layer-vias disposed in insulation layers between metallization layers. Other embodiments are described. | 01-30-2014 |
20140092574 | INTEGRATED VOLTAGE REGULATORS WITH MAGNETICALLY ENHANCED INDUCTORS - Magnetically enhanced inductors integrated with microelectronic devices at chip-level. In embodiments, magnetically enhanced inductors include a through substrate vias (TSVs) with fill metal to carry an electrical current proximate to a magnetic layer disposed on a substrate through which the TSV passes. In certain magnetically enhanced inductor embodiments, a TSV fill metal is disposed within a magnetic material lining the TSV. In certain magnetically enhanced inductor embodiments, a magnetically enhanced inductor includes a plurality of interconnected TSVs disposed proximate to a magnetic material layer on a side of a substrate. In embodiments, voltage regulation circuitry disposed on a first side of a substrate is integrated with one or more magnetically enhanced inductors utilizing a TSV passing through the substrate. In further embodiments, integrated circuitry on a same substrate as the magnetically enhanced inductor, or on another substrate stacked thereon, completes the VR and/or is powered by the VR circuitry. | 04-03-2014 |
20140183691 | RESONANT CLOCKING FOR THREE-DIMENSIONAL STACKED DEVICES - Resonant clocking for three-dimensional stacked devices. An embodiment of an apparatus includes a stack including integrated circuit dies; and through silicon vias through at least one of the dies, wherein at least a first through silicon via of the through silicon vias includes a capacitive structure or an inductive structure, the first through silicon via being formed in a first die of the plurality of dies. The apparatus includes a resonant circuit, the first through silicon via used as a first circuit element of the resonant circuit. | 07-03-2014 |
20140198013 | BACKSIDE REDISTRIBUTION LAYER PATCH ANTENNA - A patch antenna system comprising: an integrated circuit die having an active side including an active layer, and a backside; a dielectric layer formed on the backside; and a redistribution layer formed on the dielectric layer wherein the redistribution layer forms an array of patches. The patch antenna further comprises a plurality of through-silicon vias (TSV), wherein the TSVs electrically connect the array of patches to the active layer. | 07-17-2014 |