Patent application number | Description | Published |
20110078663 | Method and Apparatus for Cross-Browser Testing of a Web Application - An apparatus for cross-browser testing of a web application is disclosed, including: a first broker residing among a plurality of browsers for receiving information of a user action from a browser operated by a user among the plurality of browsers and for transmitting the information of the user action to other browsers so that the other browsers can execute the user action; a second broker residing between the plurality of browsers and the web application for receiving at least one web request generated by executing the user action from the plurality of browsers and for determining whether to be able to merge the at least one web request, so as to determine whether the plurality of browsers are compatible with the web application. An associated method is also provided. | 03-31-2011 |
20120136219 | EMOTION SCRIPT GENERATING, EXPERIENCING, AND EMOTION INTERACTION - An emotion script generating apparatus, comprising means to receive emotion data, in which the emotion data is obtained according to measurable physiological parameters reflective of a user's emotions; and means to generate emotion script using the emotion data based on a predefined template. An emotion script experiencing apparatus, comprising means to receive emotion script, wherein the emotion script is generated using emotion data and is based on a predefined template, the emotion data capable of being obtained according to measurable physiological parameters reflective of a user's emotions; and means to affect a user by using emotion data extracted from the emotion script, so as to cause the user to experience the emotion script. | 05-31-2012 |
20120190937 | EMOTION SCRIPT GENERATING, EXPERIENCING, AND EMOTION INTERACTION - An emotion script generating method includes receiving a user's emotion data, and generating emotion script using the emotion data based on a predefined template. | 07-26-2012 |
20120198422 | Cross-Browser Testing of a Web Application - An apparatus for cross-browser testing of a web application is disclosed, including: a first broker residing among a plurality of browsers for receiving information of a user action from a browser operated by a user among the plurality of browsers and for transmitting the information of the user action to other browsers so that the other browsers can execute the user action; a second broker residing between the plurality of browsers and the web application for receiving at least one web request generated by executing the user action from the plurality of browsers and for determining whether to be able to merge the at least one web request, so as to determine whether the plurality of browsers are compatible with the web application. An associated method is also provided. | 08-02-2012 |
Patent application number | Description | Published |
20100283926 | METHOD AND RESULTING CAPACITOR STRUCTURE FOR LIQUID CRYSTAL ON SILICON DISPLAY DEVICES - In a specific embodiment, the present invention provides an LCOS device. The device has a semiconductor substrate, e.g., silicon substrate. The device has a transistor formed within the semiconductor substrate. The transistor has a first node, a second node, and a row node. A first capacitor structure is coupled to the transistor. The first capacitor structure includes a first polysilicon layer coupled to the second node of the transistor. The first capacitor structure also has a first capacitor insulating layer overlying the first polysilicon layer and a second polysilicon layer overlying the insulating layer. The second polysilicon layer is coupled to a reference potential, e.g., ground. The device has a second capacitor structure coupled to the transistor. The second capacitor structure has a first metal layer coupled to the reference potential, a second capacitor insulating layer, and a second metal layer coupled to the second node of the transistor. A pixel electrode comprises the first metal layer. The pixel electrode is coupled to the second node of the transistor. A mirror surface is on the pixel electrode. The device has a light shielding layer formed from a portion of the second metal layer. | 11-11-2010 |
20110109856 | METHOD AND STRUCTURE FOR ELECTRO-PLATING ALUMINUM SPECIES FOR TOP METAL FORMATION OF LIQUID CRYSTAL ON SILICON DISPLAYS - Method and structure for electro-plating aluminum species for top metal formation of liquid crystal on silicon displays. In a specific embodiment, the invention provides a method for fabricating a liquid crystal on silicon display device. The method includes providing a substrate, e.g., semiconductor wafer, silicon wafer, silicon on insulator. The method includes forming a transistor layer (e.g., MOS transistors) overlying the substrate. The method includes forming an interlayer dielectric layer (e.g., PSG, BPSG, FSG) overlying the transistor layer. The method includes forming a first conductive layer overlying the interlayer dielectric layer and forming a second interlayer dielectric layer overlying the first conductive layer. A dual damascene via structure is formed within the second interlayer dielectric layer. The method deposits a barrier metal layer (e.g., TiN, Ti/TiN) within the dual damascene via structure to form a liner that covers exposed regions of the dual damascene via structure. | 05-12-2011 |
20120012960 | METHOD AND SYSTEM OF EMBEDDED MICROLENS - A method of making an embedded microlens includes providing a substrate having a photo-sensing region, forming a dielectric film overlying the substrate, forming a mask having a circular opening over the dielectric film, the opening being center-aligned over the photo-sensing region, and etching the dielectric film to form a cavity under the mask by introducing an isotropic etchant through the opening, the cavity being characterized by a truncated plano-convex shape having a flat circular bottom and curved peripheral sides convex towards the dielectric film. The method further includes removing the mask, depositing a lens material with a higher refractive index than that of the dielectric film to fill the cavity, planarizing the lens material to form the embedded microlens in the cavity having a smooth top surface, and forming a color filter layer overlying the microlens. The dielectric film includes silicon dioxide having a refractive index of 1.5 or less. | 01-19-2012 |
20120092604 | METHOD AND STRUCTURE FOR TOP METAL FORMATION OF LIQUID CRYSTAL ON SILICON DEVICES - The present invention provides an LCOS device having improved bonding pad features. The device has a substrate, a transistor layer overlying the substrate and an interlayer dielectric layer overlying the transistor layer. A first conductive layer is overlying the interlayer dielectric layer and a second interlayer dielectric layer is overlying the first conductive layer. An enlarged opening for a bonding pad structure is in a first portion of the second interlayer dielectric layer. A barrier metal layer is formed within the enlarged opening to form a liner that covers exposed regions of the enlarged opening. A metal material is overlying the liner to fill the enlarged opening. A thickness of an aluminum material is overlying the metal material. The device has a bonding pad structure formed from a first portion of the thickness of the aluminum material and is coupled to the metal material in the enlarged opening. | 04-19-2012 |
20120168902 | METHOD FOR FABRICATING A CAPACITOR AND CAPACITOR STRUCTURE THEREOF - A method for fabricating a capacitor includes providing a substrate having a first surface and a second surface, and forming a plurality of openings in the substrate, the openings are separated from each other by a shape of the substrate, each opening having sidewalls and a bottom. The method further includes submitting the substrate including the openings to an oxidation process to form an oxide layer covering the sidewalls and the bottom of the openings, and a portion of a surface of the substrate, wherein a shape of the substrate disposed between a pair of two adjacent openings is completely oxidized to form an insulation layer between the pair of two adjacent openings; and depositing a conductive material layer over the oxide layer in the openings such that the conductive material layer is electrically continuous and such that the pair of adjacent openings form a capacitor. | 07-05-2012 |
20120171835 | METHOD FOR PROCESSING A GLASS SUBSTRATE - A method for processing a glass substrate is disclosed. A glass substrate including a first surface, a second surface, and a side surface between the first surface and the second surface is provided. An opaque conductive layer is formed on the second surface and a part of the side surface close to the second surface. Thereafter, a semiconductor process is performed on the first surface. Thereafter, the opaque conductive layer on the second surface and the part of the side surface close to the second surface is removed. The problem of transporting a transparent glass substrate by some semiconductor tools is solved without increasing tool cost by enabling the sensing and transportation of glass substrates with optical sensor and/or electrical chuck. The fabrication of devices with a glass substrate is also achieved. | 07-05-2012 |
20120193732 | MEMS DEVICE AND METHOD FOR FORMING THE SAME - An MEMS device and a method for forming the same are provided. The MEMS device comprises a first interlayer dielectric layer on a semiconductor substrate; a cavity in the first interlayer dielectric layer; first openings in the first interlayer dielectric layer over the cavity and connected with the cavity, each first opening comprising a lower portion and an upper portion having non-aligned sidewalls, convex sections are formed in the first interlayer dielectric layer between the lower and upper portions; an electrode being suspended in the cavity and movable relative to the substrate; a second interlayer dielectric layer on the first interlayer dielectric layer; second openings in the second interlayer dielectric layer and connected with the first openings, each second opening is disposed at a location that does not extend past the convex section; a third interlayer dielectric layer fully filling at least the second openings to seal the cavity. | 08-02-2012 |
Patent application number | Description | Published |
20110057118 | Method of Indirect Emission by Nano-materials - A method of indirect emission by nano-materials includes providing an infrared up-conversion phosphor 1 (weight ratio) and a long-wave ultraviolet phosphor 0.01-10 (weight ratio); treating both surfaces of the infrared up-conversion phosphor and the long-wave ultraviolet phosphor; mixing the infrared up-conversion phosphor and the long-wave ultraviolet phosphor; exciting the infrared up-conversion phosphor by a near-infrared laser with a wavelength of 980 mn to emit blue light as a secondary excitation lightsource; exciting the long-wave ultraviolet phosphor by the blue light to emit a visible light. Biological reactions can be conveniently detected by detecting the visible light. | 03-10-2011 |
20140125989 | SIX-AXIS FOUR-SUBDIVIDING INTERFEROMETER - Six-axis four-subdividing interferometer comprising a six-axis light splitting system and an interference module which are sequentially arranged along the incident direction of polarization orthogonal double-frequency laser, wherein the six-axis light splitting system comprises five 45-degree plane beam splitters and four 45-degree full-reflecting minors. | 05-08-2014 |
20140132952 | DEVICE AND METHOD FOR DETECTING OPTICAL PERFORMANCE OF BEAM SHAPING ELEMENT - A detection apparatus and method for testing optical performance of beam shaping element used in ultraviolet lithography machine; The apparatus comprises visible wavelength laser and other optical units placed along the optical axis including, in order from laser side, (a) beam expander lens group, (b) beam splitter, (c) first far field imaging lens, (d) adjustable aperture or (e) CCD image sensor, (f) second far field imaging lens and (g) energy sensor. The detection apparatus is suitable be employed to detect the optical performance of beam shaping element working at any ultraviolet band, and provides the features of low cost, easy operation and quick measurement. | 05-15-2014 |
20140160489 | FOUR-AXIS FOUR-SUBDIVIDING INTERFEROMETER - Four-axis four-subdividing interferometer comprising a four-axis light splitting module and an interference module which are sequentially arranged along the incident direction of polarization orthogonal double-frequency laser. The four-axis light splitting system comprises three 50% plane beam splitters and three 45-degree plane reflecting mirrors. The invention comprises a four-axis four-subdividing plane mirror interferometer and a four-axis four-subdividing differential interferometer. In the differential interferometer, an adjustable 45-degree reflecting minor is used to guide the reference light to a reference reflecting minor which is arranged in the same direction as a measurement minor and fixed on the moving object. | 06-12-2014 |
20140347665 | DEVICE AND METHOD FOR MEASURING PHASE RETARDATION DISTRIBUTION AND FAST AXIS AZIMUTH ANGLE DISTRIBUTION IN REAL TIME - Device and method for measuring phase retardation distribution and fast axis azimuth angle distribution of birefringence sample in real time. The device consists of a collimating light source, a circular polarizer, a diffractive beam-splitting component, a quarter-wave plate, an analyzer array, a charge coupled device (CCD) image sensor and a computer with an image acquisition card. The method can measure the phase retardation distribution and the fast axis azimuth angle distribution of the birefringence sample in real time and has large measurement range. The measurement result is immune to the light-intensity fluctuation of the light source. | 11-27-2014 |
Patent application number | Description | Published |
20080299444 | HYDROGEN STORAGE ELECTRODE - An electrode includes a hydrogen storage material wherein the electrode has a discharge capacity of greater than about 200 mHh/g. The electrode may include an electrically conductive substrate; and a material capable of storing hydrogen on a surface thereof supported by the substrate. The hydrogen storage material is formed by contacting a powder composition with a first solution prior to electrode fabrication and by contacting the hydrogen storage material to a second solution subsequent to electrode fabrication; and the first solution comprises a first reducing agent and a first alkaline base, and the second solution comprises a second reducing agent and a second alkaline base. | 12-04-2008 |
20090159448 | ELECTROLYSIS DEVICE, METHOD, AND WASHER USING SUCH A DEVICE - An electrolysis device, for producing alkaline water from water, includes an electrolysis vessel, a pair of high porous electrodes arranged in the electrolysis vessel, and a cell unit arranged between the positive and negative electrodes. The pair of high porous electrodes respectively serve as a positive electrode and a negative electrode. The cell unit includes a bipolar membrane element and at least one cation exchangeable membrane. The bipolar membrane element has a cation exchangeable side and an anion exchangeable side. The cation exchangeable side is closer to the negative electrode than the anion exchangeable side. The cation exchangeable membrane is arranged between the anion exchangeable side of the bipolar membrane element and the positive electrode, so as to define an alkalic chamber between the bipolar membrane element and the cation exchangeable membrane. | 06-25-2009 |
20100178546 | ELECTROCHEMICAL CELL - An electrochemical cell is provided that includes a housing that is polygonal in cross-section having a plurality of peripherally spaced corners. The electrochemical cell also includes an ion-conducting separator disposed in the housing. The ion-conducting separator has an anode surface defining a portion of an anode compartment and a cathode surface defining a portion of a cathode compartment. The electrochemical cell also includes an anode current collector system comprising at least one biasing component. The biasing component has a span section, a bias section and an interface section. The bias section is in wicking contact with the anode surface of the separator. The number of biasing components in the anode current collector system differs from the number of the peripherally spaced corners. An energy storage device including a plurality of the electrochemical cells in thermal and/or in electrical communication with each other. A method for forming the biasing component is provided. | 07-15-2010 |
20140030608 | HIGH TEMPERATURE MELT INTEGRITY SEPARATOR - A heat-resistant material based on an amorphous thermoplastic polymer that is resistant to, but highly compatible with electrolyte solutions is disclosed. In an aspect, the heat-resistant material is used to form a separator for a battery cell and/or an electrolytic capacitor cell. | 01-30-2014 |
20140167329 | HIGH TEMPERATURE MELT INTEGRITY BATTERY SEPARATORS VIA SPINNING - A method for preparing a high temperature melt integrity separator, the method comprising spinning a polymer by one or more of a mechanical spinning process and an electro-spinning process to produce fine fibers. | 06-19-2014 |
20150035490 | BATTERY MANAGEMENT SYSTEM AND METHOD - A battery system has a battery module including a number M of series-connected batteries. The battery system is further provided with a number N (102-05-2015 | |
Patent application number | Description | Published |
20110066486 | SYSTEM AND METHOD FOR EFFICIENT CREATION AND RECONCILIATION OF MACRO AND MICRO LEVEL TEST PLANS - A method includes creating a macro plan for a test project, creating a micro plan for the test project, wherein the micro plan and the macro plan are based on at least one common parameter, and reconciling the macro plan and the micro plan by identifying deviations between the macro plan and the micro plan based on the at least one common parameter. | 03-17-2011 |
20110066490 | SYSTEM AND METHOD FOR RESOURCE MODELING AND SIMULATION IN TEST PLANNING - A method includes generating a test model based on at least one of test group dependencies and test group constraints and generating a resource base. The method includes generating a cost model and generating a resource allocation plan based on the test model, the resource base, and the cost model. | 03-17-2011 |
20110067005 | SYSTEM AND METHOD TO DETERMINE DEFECT RISKS IN SOFTWARE SOLUTIONS - A method is implemented in a computer infrastructure having computer executable code tangibly embodied on a computer readable storage medium having programming instructions. The programming instructions are operable to receive one or more risk factors, receive one or more contexts, identify one or more context relationships and associate the one or more contexts with the one or more risk factors. Additionally, the programming instructions are operable to map the one or more risk factors for an associated context to a software defect related risk consequence to determine a risk model and execute a risk-based testing based on the risk model to determine a defect related risk evaluation for a software development project. | 03-17-2011 |
20110161936 | METHOD AND APPARATUS FOR REGRESSION TESTING SELECTION FOR A FRAMEWORK-BASED APPLICATION - A selection method and related application is provided for a framework-based application having programming applications with both language program files and configuration files. In one embodiment, the method comprises abstracting a frame configuration model instance by analyzing configuration files prior to any modifications made to the program. The frame configuration model instance denoting individual configuration nodes in the framework model and further defining relationship between one or more code units in the configuration nodes and program code units in the application. Then one or more control test cases are constructed by profiling select test cases of the application, wherein the control flow consists of code units traversed during test case execution and control flow of said code units. Subsequently, an extended control flow is obtained by correlating configuration nodes in the framework configuration model instance with the code units in said control flow. | 06-30-2011 |
20130290073 | SYSTEM AND METHOD FOR EFFICIENT CREATION AND RECONCILIATION OF MACRO AND MICRO LEVEL TEST PLANS - A method includes creating a macro plan for a test project, creating a micro plan for the test project, wherein the micro plan and the macro plan are based on at least one common parameter, and reconciling the macro plan and the micro plan by identifying deviations between the macro plan and the micro plan based on the at least one common parameter. | 10-31-2013 |
20130339921 | SYSTEM AND METHOD TO DETERMINE DEFECT RISKS IN SOFTWARE SOLUTIONS - A method is implemented in a computer infrastructure having computer executable code tangibly embodied on a computer readable storage medium having programming instructions. The programming instructions are operable to receive one or more risk factors, receive one or more contexts, identify one or more context relationships and associate the one or more contexts with the one or more risk factors. Additionally, the programming instructions are operable to map the one or more risk factors for an associated context to a software defect related risk consequence to determine a risk model and execute a risk-based testing based on the risk model to determine a defect related risk evaluation for a software development project. | 12-19-2013 |
20140040276 | METHOD AND APPARATUS FOR PROCESSING TIME SERIES DATA - The present invention relates to processing of time series data. There is disclosed a method and apparatus for processing time series data, the method comprising: receiving a time series data set, wherein each element of the time series data set contains a timestamp and an original value associated with the timestamp, and times represented by all timestamps constitute a time series having fixed time intervals; converting each original value into a coded value occupying a smaller storage space, according to a predetermined monotone numerical compression coding scheme; dividing the times represented by all timestamps into a plurality of time intervals having a predetermined length; assembling coded values corresponding to all timestamps within each time interval into a data package such that the data package contains coded values arranged in an order of timestamps; and storing in a database record each data package and its associated identification of a time interval. | 02-06-2014 |
20140122022 | PROCESSING TIME SERIES DATA FROM MULTIPLE SENSORS - Processing time sequence data for multiple sensors, wherein the multiple sensors are divided into multiple sensor groups and each data comprises a time stamp and a value associated with the timestamp. The method comprises: receiving time series data from each sensor; assigning the time series data received to a sensor group to which the sensor belongs; storing time series data in a first database of a first memory, such that multiple time series data assigned to the same sensor group in the multiple sensor groups are stored in at least one database record of the first database; obtaining the time series data of each sensor among the multiple sensors from the first database; storing time series data in a second database of a second memory, such that the multiple time series data from the same sensor are stored in at least one database record of the second database. | 05-01-2014 |
20140136277 | SYSTEM AND METHOD TO DETERMINE DEFECT RISKS IN SOFTWARE SOLUTIONS - A method is implemented in a computer infrastructure having computer executable code tangibly embodied on a computer readable storage medium having programming instructions. The programming instructions are operable to receive one or more risk factors, receive one or more contexts, identify one or more context relationships and associate the one or more contexts with the one or more risk factors. Additionally, the programming instructions are operable to map the one or more risk factors for an associated context to a software defect related risk consequence to determine a risk model and execute a risk-based testing based on the risk model to determine a defect related risk evaluation for a software development project. | 05-15-2014 |
20150039591 | METHOD AND APPARATUS FOR PROLIFERATING TESTING DATA - Embodiments of the present invention provide information processing systems and methods for proliferating testing data based on sample testing data. In one embodiment, a difference is determined by comparing a desired query result to a query result acquired by executing a query statement on sample testing data. Sample testing data can then be proliferated based, at least in part, on the difference and data generation constraint conditions. | 02-05-2015 |
20150067636 | SYSTEM AND METHOD FOR RESOURCE MODELING AND SIMULATION IN TEST PLANNING - A method includes generating a test model based on at least one of test group dependencies and test group constraints and generating a resource base. the method includes generating a cost model and generating a resource allocation plan based on the test model, the resource base, and the cost model. | 03-05-2015 |
Patent application number | Description | Published |
20100292984 | METHOD FOR QUICKLY INPUTTING CORRELATIVE WORD - The present invention provides a text input method, which is integrated in a text input program or device supporting word input (e.g., software/hardware keyboard, input method, etc.) and assists a user in easily inputting a word or a phrase (e.g., various tense forms of a verb, etc.) relating to a certain word. The user may fast input a specific word relating to the certain word by a specific operation (e.g., clicking a software or hardware key, moving a screen contact point, etc.) or by a combination of a plurality of operations. | 11-18-2010 |
20110007004 | SOFTWARE KEYBOARD INPUT METHOD FOR REALIZING COMPOSITE KEY ON ELECTRONIC DEVICE SCREEN - A software keyboard input method for implementing compound keys on an electronic device screen is provided to assist a user in fast inputting a text with convenience and efficiency. Two letters are displayed on a key. The user performs a ambiguous input by directly clicking a key, and performs a precise input by moving a contact point via which a fast selection of a symbol and a fast switching of a uppercase letter are realized. With the software keyboard input method for implementing compound keys on an electronic device screen, information can be inputted on the electronic device screen easily and accurately. The method is of convenient usage and flexibility. | 01-13-2011 |
20110090151 | SYSTEM CAPABLE OF ACCOMPLISHING FLEXIBLE KEYBOARD LAYOUT - A system of implementing flexible keyboard layout for inputting text into an electronic device, where a user's input is mapped to a character set based on a keyboard layout, and an input sequence is formed. The user may customize different keyboard layouts and switch among these different layouts arbitrarily. Also, an auto error-correction may be achieved, and smart words selection may be achieved based on context. With the system of the invention, the design cost of the portable device manufactures may be reduced significantly. | 04-21-2011 |
Patent application number | Description | Published |
20110199842 | DRAM CELL UTILIZING FLOATING BODY EFFECT AND MANUFACTURING METHOD THEREOF - The present invention discloses a DRAM cell utilizing floating body effect and a manufacturing method thereof. The DRAM cell includes a first N type semiconductor region provided on a buried oxide layer, a P type semiconductor region provided on the first N type semiconductor region, a gate region provided on the P type semiconductor region, and an electrical isolation region surrounding the P type semiconductor region and the N type semiconductor region. A diode is taken as a storage node. Via a tunneling effect between bands, holes gather in the floating body, which is defined as a first storage state; via forward bias of PN junction, holes are emitted out from the floating body or electrons are injected into the floating body, which is defined as a second storage state. The present invention provides a highly efficient DRAM cell utilizing floating body effect with high density, which has low power consumption, has simple manufacturing process, and is compatible to the conventional CMOS and conventional logic circuit manufacturing process. | 08-18-2011 |
20110221002 | MOS-TYPE ESD PROTECTION DEVICE IN SOI AND MANUFACTURING METHOD THEREOF - The present invention discloses a MOS ESD protection device for SOI technology and a manufacturing method for the device. The MOS ESD protection device comprises: an epitaxial silicon layer grown on top of an SOI substrate; a first side-wall spacer disposed on both sides of the epitaxial silicon layer so as to isolate the ESD protection device from the intrinsic active structures; a source region and a drain region disposed respectively on two sides of the epitaxial silicon layer; a poly silicon gate and a gate dielectric formed on top of the epitaxial silicon layer; and a second side-wall spacer disposed on both sides of the poly silicon gate of . ESD leakage current passes down to the SOI substrate for protection. Because ESD protection device and intrinsic MOS transistor are located in the same plane, this fabrication process can be inserted in the current MOS process flow. | 09-15-2011 |
20110233727 | VERTICAL SOI BIPOLAR JUNCTION TRANSISTOR AND MANUFACTURING METHOD THEREOF - The present invention discloses a vertical SOI bipolar junction transistor and a manufacturing method thereof. The bipolar junction transistor includes an SOI substrate from down to up including a body region, a buried oxide layer and a top silicon film; an active region located in the top silicon film formed by STI process; a collector region located in the active region deep close to the buried oxide layer formed by ion implantation; a base region located in the active region deep close to the top silicon film formed by ion implantation; an emitter and a base electrode both located over the base region; a side-wall spacer located around the emitter and the base electrode. The present invention utilizing a simple double poly silicon technology not only can improve the performance of the transistor, but also can reduce the area of the active region in order to increase the integration density. Furthermore, the present invention utilizes side-wall spacer process to improve the compatibility of SOI BJT and SOI CMOS, which simplifies the SOI BiCMOS process and thus reduce the cost. | 09-29-2011 |
20110291191 | MOS Structure with Suppressed SOI Floating Body Effect and Manufacturing Method thereof - The present invention discloses a MOS structure with suppressed floating body effect including a substrate, a buried insulation layer provided on the substrate, and an active area provided on the buried insulation layer comprising a body region, a first conductive type source region and a first conductive type drain region provided on both sides of the body region respectively and a gate region provide on top of the body region, wherein the active area further comprises a highly doped second conductive type region between the first conductive type source region and the buried insulation layer. For manufacturing this structure, implant ions into a first conductive type source region via a mask having an opening thereon forming a highly doped second conductive type region under the first conductive type source region and above the buried insulation layer. The present invention will not increase chip area and is compatible with conventional CMOS process. | 12-01-2011 |
20110291235 | COPPER INTERCONNECTION STRUCTURE WITH MIM CAPACITOR AND A MANUFACTURING METHOD THEREOF - The present invention discloses a copper interconnection structure with MIM capacitor and a manufacturing method thereof. The method firstly makes a copper conductive pattern in a copper interconnection structure and a copper through hole bolt connected with the copper conductive pattern; etch away an insulation layer around the copper through hole bolt and deposit a etch stop layer, so as to expose the top and side surface of the copper through hole bolt and part of the top surface of the copper conductive pattern; deposit a dielectric layer on the obtained structure and fill a protection material in the recession area of the obtained structure; etch a trench for receiving other copper conductive patterns; remove the protection material; plate copper in the recession area, and plate copper in the trench, so as to obtain a copper interconnection structure with MIM capacitor. | 12-01-2011 |
20110292723 | DRAM CELL UTILIZING FLOATING BODY EFFECT AND MANUFACTURING METHOD THEREOF - The present invention discloses a DRAM cell utilizing floating body effect and a manufacturing method thereof. The DRAM cell includes a P type semiconductor region provided on a buried oxide layer, an N type semiconductor region provided on the P type semiconductor region, a gate region provided on the N type semiconductor region, and an electrical isolation region surrounding the P type semiconductor region and the N type semiconductor region. A diode of floating body effect is taken as a storage node. Via a tunneling effect between bands, electrons gather in the floating body, which is defined as a first storage state; via forward bias of PN junction, electrons are emitted out from the floating body or holes are injected into the floating body, which is defined as a second storage state. The present invention provides a highly efficient DRAM cell utilizing floating body effect with high density, which has low power consumption, has simple manufacturing process, and is compatible to the conventional CMOS and conventional logic circuit manufacturing process. | 12-01-2011 |
20120009741 | SOI MOS DEVICE HAVING A SOURCE/BODY OHMIC CONTACT AND MANUFACTURING METHOD THEREOF - The present invention discloses a manufacturing method of SOI MOS device having a source/body ohmic contact. The manufacturing method comprises steps of: firstly creating a gate region, then performing high dose source and drain light doping to form the lightly doped N-type source region and lightly doped N-type drain region; forming an insulation spacer surrounding the gate region; performing large tilt heavily-doped P ion implantation in an inclined direction via a mask with an opening at the position of the N type Si source region and implanting P ions into the space between the N type Si source region and the N type drain region to form a heavily-doped P-type region; finally forming a metal layer on the N type Si source region, then allowing the reaction between the metal layer and the remained Si material underneath to form silicide by heat treatment. In the device prepared by the method of the present invention, an ohmic contact is formed between the silicide and the heavily-doped P-type region nearby in order to release the holes accumulated in body region of the SOI MOS device and eliminate floating body effects thereof. Besides, the device of the present invention also has following advantages, such as limited chip area, simplified fabricating process and great compatibility with traditional CMOS technology. | 01-12-2012 |
20120012931 | SOI MOS DEVICE HAVING BTS STRUCTURE AND MANUFACTURING METHOD THEREOF - The present invention discloses a SOI MOS device having BTS structure and manufacturing method thereof. The source region of the SOI MOS device comprises: two heavily doped N-type regions, a heavily doped P-type region formed between the two heavily doped N-type regions, a silicide formed above the heavily doped N-type regions and the heavily doped P-type region, and a shallow N-type region which is contact to the silicide; an ohmic contact is formed between the heavily doped P-type region and the silicide thereon to release the holes accumulated in body region of the SOI MOS device and eliminate floating body effects thereof without increasing the chip area and also overcome the disadvantages such as decreased effective channel width of the devices in the BTS structure of the prior art. The manufacturing method comprises steps of: forming a heavily doped P-type region via ion implantation, forming a metal layer above the source region and forming a silicide via the heat treatment between the metal layer and the Si underneath. The device in the present invention could be fabricated via simplified fabricating process with great compatibility with traditional CMOS technology. | 01-19-2012 |
20120018809 | MOS DEVICE FOR ELIMINATING FLOATING BODY EFFECTS AND SELF-HEATING EFFECTS - A MOS device having low floating charge and low self-heating effects are disclosed. The device includes a connective layer coupling the active gate channel to the Si substrate. The connective layer provides electrical and thermal passages during device operation, which could eliminate floating effects and self-heating effects. An example of a MOS device having a SiGe connector between a Si active channel and a Si substrate is disclosed in detail and a manufacturing process is provided. | 01-26-2012 |
20120021571 | Method of Reducing Floating Body Effect of SOI MOS Device Via a Large Tilt Ion Implantation - The present invention discloses a method of reducing floating body effect of SOI MOS device via a large tilt ion implantation including a step of: (a) implanting ions in an inclined direction into an NMOS with a buried insulation layer forming a highly doped P region under a source region of the NMOS and above the buried insulation layer, wherein the angle between a longitudinal line of the NMOS and the inclined direction is ranging from 15 to 45 degrees. Through this method, the highly doped P region under the source region and a highly doped N region form a tunnel junction so as to reduce the floating body effect. Furthermore, the chip area will not be increased, manufacturing process is simple and the method is compatible with conventional CMOS process. | 01-26-2012 |
20120025267 | MOS DEVICE FOR ELIMINATING FLOATING BODY EFFECTS AND SELF-HEATING EFFECTS - A SOI MOS device for eliminating floating body effects and self-heating effects are disclosed. The device includes a connective layer coupling the active gate channel to the Si substrate. The connective layer provides electrical and thermal passages during device operation, which could eliminate floating body effects and self-heating effects. An example of a MOS device having a SiGe connector between a Si active channel and a Si substrate is disclosed in detail and a manufacturing process is provided. | 02-02-2012 |
20120112283 | ESD PROTECTION DEVICES FOR SOI INTEGRATED CIRCUIT AND MANUFACTURING METHOD THEREOF - The present invention discloses an ESD protection structure in a SOI CMOS circuitry. The ESD protection structure includes a variety of longitudinal (vertical) PN junction structures having significantly enlarged junction areas for current flow. The resulting devices achieve increased heavy current release capability. Processes of fabricating varieties of the ESD protection longitudinal PN junction are also disclosed. Compatibility of the disclosed fabrication processes with current SOI technology reduces implementation cost and improves the integration robustness. | 05-10-2012 |
20120115287 | MANUFACTURING METHOD OF SOI MOS DEVICE ELIMINATING FLOATING BODY EFFECTS - The present invention discloses a manufacturing method of SOI MOS device eliminating floating body effects. The active area of the SOI MOS structure according to the present invention includes a body region, a N-type source region, a N-type drain region, a heavily doped P-type region, wherein the N-type source region comprises a silicide and a buried insulation region and the heavily doped P-type region is located between the silicide and the buried insulation region. The heavily doped P-type region contacts to the silicide, the body region, the buried insulation layer and the shallow trench isolation (STI) structure respectively. The manufacturing method of the device comprises steps of forming a heavily doped P-type region via ion implantation method, forming a metal layer on a part of the surface of the source region, then obtaining a silicide by the heat treatment of the metal layer and the Si material below. The present invention utilizes the silicide and the heavily doped P-type region to form an ohmic contact in order to release the holes accumulated in the body region of SOI MOS device and eliminate SOI MOS floating body effects. Besides, the manufacturing process is simple and can be easily implement. Further, the manufacturing process according to the present invention will not increase chip area and is compatible with conventional CMOS process. | 05-10-2012 |
20120205743 | PD SOI DEVICE WITH A BODY CONTACT STRUCTURE - The present invention discloses a PD SOI device with a body contact structure. The active region of the PD SOI device includes: a body region; a gate region, which is inverted-L shaped, formed on the body region; a N-type source region and a N-type drain region, formed respectively at the two opposite sides of the anterior part the body region; a body contact region, formed at one side of the posterior part of the body region, which is side-by-side with the N-type source region; and a first silicide layer, formed on the body contact region and the N-type source region, which is contact to both of the body contact region and the N-type source region. The body contact region of the device is formed on the border of the source region and the leading-out terminal of the gate electrode. It can suppress floating body effect of the PD SOI device meanwhile not increasing the chip area, thereby overcoming the shortcoming in the prior art that the chip area is enlarged when the traditional body contact structure is employed. Furthermore, the fabrication process provided herein is simple and compatible to the CMOS technology. | 08-16-2012 |
20130020652 | METHOD FOR SUPPRESSING SHORT CHANNEL EFFECT OF CMOS DEVICE - A method for manufacturing a gate-last high-K CMOS structure comprising a first transistor and a second transistor, which is formed in a Si substrate includes: implanting acceptor impurity into a gate recess of the first transistor to form a first buried-layer heavily doping region under a channel of the first transistor; and implanting donor impurity into a gate recess of the second transistor to form a second buried-layer heavily doping region under a channel of the second transistor. | 01-24-2013 |
20130065385 | METHOD FOR PREPARING SPACER TO REDUCE COUPLING INTERFERENCE IN MOSFET - The present invention provides a method for preparing spacer to reduce coupling interference in MOSFET, which includes the steps of: forming a gate oxide layer on the semiconductor substrate; forming a gate on the gate oxide layer; and depositing a low-K dielectric material on the gate and the semiconductor substrate, and doping with carbon during deposition to form a carbon-containing low-K dielectric layer and then forming the spacer by an etching process. | 03-14-2013 |
Patent application number | Description | Published |
20100128501 | SYSTEMS AND METHODS FOR CONSTANT VOLTAGE MODE AND CONSTANT CURRENT MODE IN FLYBACK POWER CONVERTER WITH PRIMARY-SIDE SENSING AND REGULATION - System and method for regulating a power converter. The system includes a first signal generator configured to receive at least an input signal and generate at least a first output signal associated with demagnetization and a second output signal associated with sampling. Additionally, the system includes a sampling component configured to receive at least the input signal and the second output signal, sample the input signal based on at least information associated with the second output signal, and generate at least a third output signal associated with one or more sampled magnitudes. Moreover, the system includes an error amplifier configured to receive at least the third output signal and a first threshold voltage and generate at least a fourth output signal with a capacitor, the capacitor being coupled to the error amplifier. | 05-27-2010 |
20120013321 | SYSTEMS AND METHODS OF PRIMARY-SIDE SENSING AND REGULATION FOR FLYBACK POWER CONVERTER WITH HIGH STABILITY - System and method for regulating an output voltage of a power conversion system. The system includes an error amplifier coupled to a capacitor. The error amplifier is configured to receive a reference voltage, a first voltage, and an adjustment current and to generate a compensation voltage with the capacitor. The first voltage is associated with a feedback voltage. Additionally, the system includes a current generator configured to receive the compensation voltage and generate the adjustment current and a first current, and a signal generator configured to receive the first current and a second current. The signal generator is further configured to receive a sensing voltage and to generate a modulation signal. Moreover, the system includes the gate driver directly or indirectly coupled to the signal generator and configured to generate a drive signal based on at least information associated with the modulation signal. | 01-19-2012 |
20120075891 | SYSTEMS AND METHODS FOR CONSTANT VOLTAGE MODE AND CONSTANT CURRENT MODE IN FLYBACK POWER CONVERTERS WITH PRIMARY-SIDE SENSING AND REGULATION - System and method for regulating a power converter. The system includes a first signal generator configured to receive a first sensed signal and generate an output signal associated with demagnetization. The first sensed signal is related to a first winding coupled to a secondary winding for a power converter, and the secondary winding is associated with at least an output current for the power converter. Additionally, the system includes a ramping signal generator configured to receive the output signal and generate a ramping signal, and a first comparator configured to receive the ramping signal and a first threshold signal and generate a first comparison signal based on at least information associated with the ramping signal and the first threshold signal. Moreover, the system includes a second comparator configured to receive a second sensed signal and a second threshold signal and generate a second comparison signal. | 03-29-2012 |
20120319742 | SYSTEMS AND METHODS FOR DRIVING A BIPOLAR JUNCTION TRANSISTOR BY ADJUSTING BASE CURRENT WITH TIME - System and method for driving a bipolar junction transistor for a power converter. The system includes a current generator configured to output a drive current signal to a bipolar junction transistor to adjust a primary current flowing through a primary winding of a power converter. The current generator is further configured to output the drive current signal to turn on the bipolar junction transistor during a first time period, a second time period, and a third time period, the second time period separating the first time period from the third time period, drive the bipolar junction transistor to operate in a hard-saturation region during the first time period and the second time period, and drive the bipolar junction transistor to operate in a quasi-saturation region during the third time period. | 12-20-2012 |
20130058137 | SYSTEMS AND METHODS OF PRIMARY-SIDE SENSING AND REGULATION FOR FLYBACK POWER CONVERTER WITH HIGH STABILITY - System and method for regulating an output voltage of a power conversion system. The system includes an error amplifier coupled to a capacitor. The error amplifier is configured to receive a reference voltage, a first voltage, and an adjustment current and to generate a compensation voltage with the capacitor. The first voltage is associated with a feedback voltage. Additionally, the system includes a current generator configured to receive the compensation voltage and generate the adjustment current and a first current, and a signal generator configured to receive the first current and a second current. The signal generator is further configured to receive a sensing voltage and to generate a modulation signal. Moreover, the system includes the gate driver directly or indirectly coupled to the signal generator and configured to generate a drive signal based on at least information associated with the modulation signal. | 03-07-2013 |
20130272033 | SYSTEMS AND METHODS FOR CONSTANT VOLTAGE MODE AND CONSTANT CURRENT MODE IN FLYBACK POWER CONVERTERS WITH PRIMARY-SIDE SENSING AND REGULATION - System and method for regulating a power converter. The system includes a first signal generator configured to receive a first sensed signal and generate an output signal associated with demagnetization. The first sensed signal is related to a first winding coupled to a secondary winding for a power converter, and the secondary winding is associated with at least an output current for the power converter. Additionally, the system includes a ramping signal generator configured to receive the output signal and generate a ramping signal, and a first comparator configured to receive the ramping signal and a first threshold signal and generate a first comparison signal based on at least information associated with the ramping signal and the first threshold signal. Moreover, the system includes a second comparator configured to receive a second sensed signal and a second threshold signal and generate a second comparison signal. | 10-17-2013 |
20130308350 | SYSTEMS AND METHODS FOR CONSTANT VOLTAGE MODE AND CONSTANT CURRENT MODE IN FLYBACK POWER CONVERTERS WITH PRIMARY-SIDE SENSING AND REGULATION - System and method for regulating a power converter. The system includes a first signal generator configured to receive at least an input signal and generate at least a first output signal associated with demagnetization and a second output signal associated with sampling. Additionally, the system includes a sampling component configured to receive at least the input signal and the second output signal, sample the input signal based on at least information associated with the second output signal, and generate at least a third output signal associated with one or more sampled magnitudes. Moreover, the system includes an error amplifier configured to receive at least the third output signal and a first threshold voltage and generate at least a fourth output signal with a capacitor, the capacitor being coupled to the error amplifier. | 11-21-2013 |
20130317436 | INFUSION PUMP - An infusion pump comprises a housing ( | 11-28-2013 |
20140022824 | SYSTEMS AND METHODS OF PRIMARY-SIDE SENSING AND REGULATION FOR FLYBACK POWER CONVERTER WITH HIGH STABILITY - System and method for regulating an output voltage of a power conversion system. The system includes an error amplifier coupled to a capacitor. The error amplifier is configured to receive a reference voltage, a first voltage, and an adjustment current and to generate a compensation voltage with the capacitor. The first voltage is associated with a feedback voltage. Additionally, the system includes a current generator configured to receive the compensation voltage and generate the adjustment current and a first current, and a signal generator configured to receive the first current and a second current. The signal generator is further configured to receive a sensing voltage and to generate a modulation signal. Moreover, the system includes the gate driver directly or indirectly coupled to the signal generator and configured to generate a drive signal based on at least information associated with the modulation signal. | 01-23-2014 |
20140078790 | SYSTEMS AND METHODS FOR VOLTAGE CONTROL AND CURRENT CONTROL OF POWER CONVERSION SYSTEMS WITH MULTIPLE OPERATION MODES - System and method for regulating a power conversion system. A system controller for regulating a power conversion system includes an operation-mode-selection component and a driving component. The operation-mode-selection component is configured to receive a first signal related to an output load of the power conversion system and a second signal related to an input signal received by the power conversion system and output a mode-selection signal based on at least information associated with the first signal and the second signal. The driving component is configured to receive the mode-selection signal and generate a drive signal based on at least information associated with the mode-selection signal, the driving signal corresponding to a switching frequency. | 03-20-2014 |
20140121602 | INFUSION PUMP - An infusion pump comprises a housing ( | 05-01-2014 |
20140204627 | SYSTEMS AND METHODS FOR DRIVING A BIPOLAR JUNCTION TRANSISTOR BY ADJUSTING BASE CURRENT WITH TIME - System and method for driving a bipolar junction transistor for a power converter. The system includes a current generator configured to output a drive current signal to a bipolar junction transistor to adjust a primary current flowing through a primary winding of a power converter. The current generator is further configured to output the drive current signal to turn on the bipolar junction transistor during a first time period, a second time period, and a third time period, the second time period separating the first time period from the third time period, drive the bipolar junction transistor to operate in a hard-saturation region during the first time period and the second time period, and drive the bipolar junction transistor to operate in a quasi-saturation region during the third time period. | 07-24-2014 |
20140362621 | SYSTEMS AND METHODS FOR TWO-LEVEL PROTECTION OF POWER CONVERSION SYSTEMS - Systems and methods are provided for protecting a power conversion system. A system controller includes a two-level protection component and a driving component. The two-level protection component is configured to detect an output power of a power conversion system and generate a protection signal based on at least information associated with the output power. The driving component is configured to generate a drive signal based on at least information associated with the protection signal and output the drive signal to a switch associated with a primary current flowing through a primary winding of the power conversion system. The driving component is further configured to generate the drive signal corresponding to a first switching frequency to generate the output power equal to a first power threshold and generate the drive signal corresponding to a second switching frequency to generate the output power equal to a second power threshold. | 12-11-2014 |
20150085540 | Systems and Methods for Over-Temperature Protection and Over-Voltage Protection for Power Conversion Systems - Systems and methods are provided for protecting a power conversion system. A system controller includes a first controller terminal and a second controller terminal. The first controller terminal is configured to provide a drive signal to close and open a switch to affect a first current flowing through a primary winding of a power conversion system. The second controller terminal is configured to receive first input signals during one or more first switching periods and receive second input signals during one or more second switching periods. The system controller is configured to determine whether a temperature associated with the power conversion system is larger than a predetermined temperature threshold, and in response to the temperature associated with the power conversion system being larger than the predetermined temperature threshold, generate the drive signal to cause the switch open and remain open to protect the power conversion system. | 03-26-2015 |
Patent application number | Description | Published |
20100109730 | PWM CONTROL CIRCUIT HAVING ADJUSTABLE MINIMUM DUTY CYCLE - A pulse width modulated (PWM) controller includes a triangle wave generation circuit generating a triangle wave signal to oscillate between an upper limit voltage and a lower limit voltage. The upper limit voltage and the lower limit voltage are adjustable in response to changes in the power supply voltage. A pulse generation circuit is coupled to the triangle wave generation circuit and a minimum duty cycle setting voltage, and is configured to generate a PWM pulse signal with a minimum duty cycle determined by the relative magnitude of the triangle wave signal and the minimum duty cycle reference voltage. In an embodiment, the minimum duty cycle is increased when the power supply voltage is lower than a predetermined reference voltage. | 05-06-2010 |
20100164581 | PULSED WIDTH MODULATED CONTROL METHOD AND APPARATUS - A pulse width modulated (PWM) controller has an input terminal for receiving a pulsed input signal having a first duty cycle, a power supply terminal for receiving a power supply voltage. a minimum duty cycle reference voltage signal, and a control circuit for providing a pulse-width-modulated (PWM) output signal having a second duty cycle related to the first duty cycle of the pulsed input signal. The PWM output control signal having a minimum duty cycle that is adjustable in response to a change in the power supply voltage. In an embodiment, the second duty cycle and the first duty cycle are correlated in a substantially linear relationship. In an embodiment, the PWM control circuit also has a triangle wave generation circuit for generating a triangle wave signal configured to oscillate between an upper limit voltage and a lower limit voltage, which are adjustable in response to a change in the power supply voltage. | 07-01-2010 |
20110299247 | System and Method for Regulating Motor Rotation Speed - The present invention relates to a system and method controlling motor rotation speed and provides a cooling system and method configured to control a temperature associated with an integrated circuit. The cooling system includes a brushless motor, a temperature monitoring input, a clock input, and a motor controller. The motor controller is configured to control the rotational speed of the motor using at least a speed control method by comparing the environmental temperature signal to a predetermined threshold: if the environmental temperature signal is less than the predetermined threshold T | 12-08-2011 |
20140028286 | AMPLIFIER CIRCUITS AND METHODS - A chopper amplifier circuit for sensing Hall voltage with reduced offsets includes a Hall sampling circuit with a first switching circuit for selectively coupling each of four nodes of a Hall plate to either a power source or a ground terminal. The circuit also includes a differential amplifier and a second switching circuit configured for selectively coupling each of the four nodes to inputs of the differential amplifier. A Hall voltage signal retaining circuit includes two groups of four storage devices and a second group of four storage devices. A third switching circuit is configured for outputs of the differential amplifier to selected ones of the storage devices. A fourth switching circuit is configured for selectively coupling the storage devices outputs of the chopper amplifier circuit. | 01-30-2014 |
Patent application number | Description | Published |
20090148440 | ANTIBODIES AGAINST INTERLEUKIN-22 BINDING PROTEIN AND ITS USES FOR THE TREATMENT OF METABOLIC DISORDERS - The present invention relates to antibodies and antigen-binding fragments that bind to interleukin-22 binding protein, in particular, human interleukin-22 binding protein (IL-22 BP), and are involved in regulating interleukin-22-associated biological responses. The invention also relates to methods of using the antibodies and antigen-binding fragments to treat disorders associated with interleukin-22. The antibodies disclosed herein are useful in diagnosing, preventing, or treating metabolic disorders including obesity, diabetes, hyperlipidemia and hyperinsulinemia etc. | 06-11-2009 |
20100041101 | EXPRESSION SYSTEM FOR RECOMBINANT HUMAN ARGINASE I - A novel recombinant protein expression system is provided for improving expression of recombinant human arginase I. The system contains an isolated and purified nucleic acid molecule for constructing plasmid and | 02-18-2010 |
20110262385 | USE OF INTERLEUKIN-22 IN THE TREATMENT OF FATTY LIVER DISEASE - The present invention relates to use of interleukin-22 (IL-22) for treating fatty liver disease by decreasing the levels of transaminases. The use of IL-22 in decreasing the levels of transaminases is also provided. | 10-27-2011 |
20110268696 | PREVENTION AND/OR TREATMENT OF MULTIPLE ORGAN DYSFUNCTION SYNDROME WITH INTERLEUKIN-22 - The present invention relates to use an agent for the prevention and/or treatment of multiple organ dysfunction syndrome (MODS) or multiple organ failure (MOF) comprising interleukin-22 (IL-22) as an effective ingredient. The present invention is applicable to prevention of or therapy for diseases from sepsis, septic shock, liver failure, to multiple organ dysfunction syndromes. More particularly, the present invention is useful for an emergency medical service, for treatment of injury caused by a traffic accident, burns, heat attacks, hypercytokinemia or severe infective diseases. | 11-03-2011 |
20140377222 | USE OF INTERLEUKIN-22 IN THE TREATMENT OF FATTY LIVER DISEASE - The present invention relates to use of interleukin-22 (IL-22) for treating fatty liver disease by decreasing the levels of transaminases. The use of IL-22 in decreasing the levels of transaminases is also provided. | 12-25-2014 |
Patent application number | Description | Published |
20100307913 | PLATING APPARATUS FOR METALLIZATION ON SEMICONDUCTOR WORKPIECE - The present invention provides a plating apparatus with multiple anode zones and cathode zones. The electrolyte flow field within each zone is controlled individually with independent flow control devices. A gas bubble collector whose surface is made into pleated channels is implemented for gas removal by collecting small bubbles, coalescing them, and releasing the residual gas. A buffer zone built within the gas bubble collector further allows unstable microscopic bubbles to dissolve. | 12-09-2010 |
20110114120 | METHODS AND APPARATUS FOR CLEANING SEMICONDUCTOR WAFERS - An apparatus for cleaning and conditioning the surface of a semiconductor substrate such as wafer includes a rotatable chuck, a chamber, a rotatable tray for collecting cleaning solution with one or more drain outlets, multiple receptors for collecting multiple cleaning solutions, a first motor to drive chuck, and a second motor to drive the tray. The drain outlet in the tray can be positioned directly above its designated receptor located under the drain outlet. The cleaning solution collected by the tray can be guided into designated receptor. One characteristic of the apparatus is having a robust and precisely controlled cleaning solution recycle with minimum cross contamination. | 05-19-2011 |
20110290277 | Methods and Apparatus for Cleaning Semiconductor Wafers - A method for cleaning semiconductor substrate using ultra/mega sonic device comprising holding a semiconductor substrate by using a chuck, positioning a ultra/mega sonic device adjacent to the semiconductor substrate, injecting chemical liquid on the semiconductor substrate and gap between the semiconductor substrate and the ultra/mega sonic device, changing gap between the semiconductor substrate and the ultra/mega sonic device for each rotation of the chuck during the cleaning process. The gap can be increased or reduced by 0.5λ/N for each rotation of the chuck, where λ is wavelength of ultra/mega sonic wave, N is an integer number between 2 and 1000. The gap is varied in the range of 0.5λn during the cleaning process, where λ is wavelength of ultra/mega sonic wave, and n is an integer number starting from 1. | 12-01-2011 |
20120097195 | Methods and Apparatus for Cleaning Semiconductor Wafers - A method for cleaning semiconductor substrate using ultra/mega sonic device comprising holding a semiconductor substrate by using a chuck, positioning a ultra/mega sonic device adjacent to the semiconductor substrate, injecting chemical liquid on the semiconductor substrate and gap between the semiconductor substrate and the ultra/mega sonic device, changing gap between the semiconductor substrate and the ultra/mega sonic device for each rotation of the chuck during the cleaning process by turn the semiconductor substrate or the ultra/mega sonic device clockwise or count clockwise. | 04-26-2012 |
20140034094 | Methods and Apparatus for Cleaning Semiconductor Wafers - An apparatus for cleaning and conditioning the surface of a semiconductor substrate such as wafer includes a rotatable chuck, a chamber, a rotatable tray for collecting cleaning solution with one or more drain outlets, multiple receptors for collecting multiple cleaning solutions, a first motor to drive chuck, and a second motor to drive the tray. The drain outlet in the tray can be positioned directly above its designated receptor located under the drain outlet. The cleaning solution collected by the tray can be guided into designated receptor. One characteristic of the apparatus is having a robust and precisely controlled cleaning solution recycle with minimum cross contamination. | 02-06-2014 |
Patent application number | Description | Published |
20110121935 | COMPOSITE MAGNETIC CORE ASSEMBLY, MAGNETIC ELEMENT AND FABRICATING METHOD THEREOF - A composite magnetic core assembly includes an inner magnetic core and an outer magnetic core. The inner magnetic core is made of a high saturation flux density and low permeability material. The outer magnetic core is made of a low saturation flux density and high permeability material. The outer magnetic core includes a ring-shaped wall and a receptacle. The inner magnetic core is accommodated within the receptacle. | 05-26-2011 |
20120293293 | MAGNETIC DEVICE AND METHOD FOR GENERATING INDUCTANCE - A magnetic device includes two symmetric magnetic cores, each of which includes a base, a first protruding portion and second protruding portions. The first protruding portion and the second protruding portions are formed on the base separately along two edges of the base. The two symmetric magnetic cores are assembled such that a gap is formed between the first protruding portion of one of the two symmetric magnetic cores and the first protruding portion of the other one of the two symmetric magnetic cores. A method for generating inductance is also disclosed herein. | 11-22-2012 |
20150061807 | Transformer - A transformer includes a magnetic core, a primary winding, and a plurality of secondary windings. The magnetic core has an axial and a radial direction. The primary winding includes a plurality of winding sections and at least one connecting section. The winding sections are arranged along the axial direction. The connecting section is connected between the two adjacent winding sections. Each of the winding sections includes a plurality of primary winding layers and pull-out portions. The primary winding layers surround the magnetic core and are arranged along the radial direction. One pull-out portion connects two primary winding layers adjacent to the pull-out portion. Part of normal projections of the primary winding layers on a surface of the magnetic core are located between normal projections of the pull-out portions on the surface of the magnetic core. The secondary windings surround the primary winding. | 03-05-2015 |
20150069853 | INDUCTOR AND SWITCHING CIRCUIT INCLUDING THE SAME - The present disclosure provides an inductor and a switching circuit including the inductor. The inductor at least includes a winding, and a magnetic core which includes one or more limbs and further includes one or more yokes adapted to form a closed magnetic path, the winding being wounded on the limbs. A gap is provided between at least one end of at least one of the limbs and at least one of the yokes, a flat magnetic core unit is provided in the gap, the flat magnetic core unit is formed of a material having a high permeability and a low saturation magnetic flux density, the limbs and yokes are formed of a material having high permeability and high saturation magnetic flux density, and the saturation magnetic flux density of the material of the flat magnetic core unit is lower than that of the material of the limbs and yokes. | 03-12-2015 |
Patent application number | Description | Published |
20090148440 | ANTIBODIES AGAINST INTERLEUKIN-22 BINDING PROTEIN AND ITS USES FOR THE TREATMENT OF METABOLIC DISORDERS - The present invention relates to antibodies and antigen-binding fragments that bind to interleukin-22 binding protein, in particular, human interleukin-22 binding protein (IL-22 BP), and are involved in regulating interleukin-22-associated biological responses. The invention also relates to methods of using the antibodies and antigen-binding fragments to treat disorders associated with interleukin-22. The antibodies disclosed herein are useful in diagnosing, preventing, or treating metabolic disorders including obesity, diabetes, hyperlipidemia and hyperinsulinemia etc. | 06-11-2009 |
20110262385 | USE OF INTERLEUKIN-22 IN THE TREATMENT OF FATTY LIVER DISEASE - The present invention relates to use of interleukin-22 (IL-22) for treating fatty liver disease by decreasing the levels of transaminases. The use of IL-22 in decreasing the levels of transaminases is also provided. | 10-27-2011 |
20110268696 | PREVENTION AND/OR TREATMENT OF MULTIPLE ORGAN DYSFUNCTION SYNDROME WITH INTERLEUKIN-22 - The present invention relates to use an agent for the prevention and/or treatment of multiple organ dysfunction syndrome (MODS) or multiple organ failure (MOF) comprising interleukin-22 (IL-22) as an effective ingredient. The present invention is applicable to prevention of or therapy for diseases from sepsis, septic shock, liver failure, to multiple organ dysfunction syndromes. More particularly, the present invention is useful for an emergency medical service, for treatment of injury caused by a traffic accident, burns, heat attacks, hypercytokinemia or severe infective diseases. | 11-03-2011 |
20140377222 | USE OF INTERLEUKIN-22 IN THE TREATMENT OF FATTY LIVER DISEASE - The present invention relates to use of interleukin-22 (IL-22) for treating fatty liver disease by decreasing the levels of transaminases. The use of IL-22 in decreasing the levels of transaminases is also provided. | 12-25-2014 |
Patent application number | Description | Published |
20110018856 | OUTDOOR READABLE LIQUID CRYSTAL DISPLAY DEVICE - An outdoor readable liquid crystal display device ( | 01-27-2011 |
20120091997 | DETECTING CIRCUIT FOR PIXEL ELECTRODE VOLTAGE OF FLAT PANEL DISPLAY DEVICE - A detecting circuit for pixel electrode voltage of a flat panel display device, the flat panel display device having a plurality of scanning lines and a plurality of data lines crossing with the plurality of scanning lines, the plurality of scanning lines and data lines define a plurality of pixel units, and each of the pixel units including a pixel switching element and a pixel electrode. The detecting circuit for pixel electrode voltage includes at least one detecting sub-circuit for pixel electrode voltage. The detecting sub-circuit for pixel electrode voltage includes: a signal amplifying unit connected with the pixel electrode in the pixel unit, for amplifying a voltage signal of the pixel electrode; and a signal detecting unit connected with the signal amplifying unit, for detecting the voltage signal of the pixel electrode that has been amplified by the signal amplifying unit, and outputting a variation in the voltage signal of the pixel electrode with time. Compared with the prior art, the present invention has advantages of simple detecting circuit structure and accurate detection result. | 04-19-2012 |
20140001368 | ESD PROTECTION SYSTEM AND X-RAY FLAT PANEL DETECTOR | 01-02-2014 |
20140049702 | ELECTRICAL CONNECTION STRUCTURE OF TOUCH CONTROLLED LIQUID CRYSTAL DISPLAY DEVICE - An electrical connection structure of a touch controlled liquid crystal display device, including: a first substrate; a plurality of first conductive pads on the first substrate, each of the first conductive pads being electrically connected with one first signal line; and at least one isolator between two adjacent first conductive pads. The isolator is arranged between two adjacent first conductive pads so that when the first conductive pads and the isolator are subsequently covered with conductive glue including conductive balls, the conductive balls in the conductive glue between two adjacent first conductive pads will not contact with each other to thereby ensure that the first conductive pads can be kept insulated from each other even if the conductive balls are distributed in the conductive glue at a high density. | 02-20-2014 |
20140078032 | DUAL-GATE DRIVEN LATERAL PIXEL ARRANGEMENT STRUCTURE AND DISPLAY PANEL - A dual-gate-driven lateral pixel arrangement structure includes two horizontally adjacent primary pixel regions having each three vertically adjacent secondary pixel regions forming a grid of six secondary pixel regions, and six thin-film transistors disposed in each of the six secondary pixel areas. The structure also includes two gate lines and three data lines crossing each other and electrically isolated from each other. Each data line is connected to the source of two thin-film transistors having the gate connected to a different gate line. The two gate lines are interposed between the three secondary pixel regions or arranged along a side or opposite sides of the primary pixel regions in a first direction. The three data lines are arranged between the primary pixel regions and along a side or opposite sides of the primary pixel regions in a second direction different from the first direction. | 03-20-2014 |
20140092510 | ESD PROTECTION DEVICE OF TOUCH PANEL - An ESD protection device for a touch panel is disclosed. The protection device includes an ESD protection circuit, and a protection switch connected in series with the ESD protection circuit. The protection switch is configured to turn on in response to an electrostatic potential of a sensing line or a driving line of the touch panel being equal to or greater than a preset potential, such that static electricity from the sensing line or the driving line is conducted to a peripheral common electrode busbar, or to an ESD discharge busbar, or to a ground busbar. In addition, the protection switch is configured to turn off in response to a panel of the touch panel being normally driven. | 04-03-2014 |
20140104205 | TOUCH SCREEN DISPLAY APPARATUS - The present invention provides a touch screen display apparatus including a touch structure. The touch structure includes multiple driving lines arranged in a column direction, multiple sensing lines arranged in a row direction, a preamplifier, a frequency outputter, a first shift register, and a second shift register. The first shift register is arranged between the driving lines and the frequency outputter, and the second shift register is arranged at output ends of the sensing lines. Each driving line outputs a driving signal and each sensing line outputs a sensing signal for the preamplifier. Accordingly, a single preamplifier may be used. | 04-17-2014 |
20140104254 | OUTDOOR READABLE LIQUID CRYSTAL DISPLAY DEVICE - An outdoor readable liquid crystal display device ( | 04-17-2014 |
20140146009 | TOUCH SIGNAL SCAN APPARATUS AND TOUCH SIGNAL SCAN METHOD - A touch signal scan apparatus and a touch signal scan method are disclosed. The apparatus includes: a drive signal supply unit electrically connected with M drive lines in one-to-one correspondence, an electrode layer in which the M drive lines and N sense lines are arranged, and N amplifiers electrically connected with different output ends of the N sense lines in one-to-one correspondence. The drive signal supply unit is configured to supply drive signals with at least two different frequencies to the M drive lines in a period of one frame, and the frequencies of the drive signals supplied to two adjacent drive lines are different. The apparatus further includes a bandwidth filter electrically connected with the N amplifiers and configured to separate sense signals output from the N amplifiers so as to obtain the sense signals corresponding to the respective drive signals with the at least two different frequencies. | 05-29-2014 |
20140160368 | MUTUAL INDUCTIVE CAPACITIVE TOUCH SCREEN - A mutual inductive capacitive touch screen is disclosed. The screen includes a plurality of drive lines, a plurality of sense lines and an electrode structure including a plurality of first electrodes and a plurality of second electrodes. The first electrodes are connected with the drive lines of the touch screen and the second electrodes are connected with the sense lines of the touch screen, or the first electrodes are connected with the sense lines of the touch screen and the second electrodes are connected with the drive lines of the touch screen. In addition, the electrode structure has an isotropic detection characteristic. | 06-12-2014 |
20140168147 | CAPACITIVE TOUCH MODULE AND TOUCH DISPLAY APPARATUS - The invention discloses a capacitive touch module and a touch display apparatus, where a first touch sensing electrode, a second touch sensing electrode connected to one touch sensing line are respectively disposed in two adjacent touch units, and a first touch driving electrode and a second touch driving electrode connected to one touch driving line are respectively disposed in two adjacent touch units, so that the touch sensing signal can respond to the change of the sensing capacitances in the two adjacent touch units, so as to reduce the high-frequency false signal possibility from the touch units, thereby lower the possibilities of an improper trigger and a mis-operation due to a jump and a sudden change at a touch point, thus making a touch event more smooth and fluid. | 06-19-2014 |
20140176494 | TOUCH CONTROL DISPLAY PANEL AND TOUCH DISPLAY DEVICE - The invention discloses a touch control display panel and a touch control display apparatus, where the touch control display panel includes a TFT array substrate and a color film substrate arranged in opposition; the TFT array substrate includes a pixel array and a touch control dual-gate TFT array; and when there is a touch control occurring, an electrically conductive post at a press location approaches the touch control dual-gate TFT along with a press, and a channel current of the touch control dual-gate TFT can be modulated by a current generated by the electrically conductive post. There will be no interference with a display per se in operation of the touch control, and no adverse influence imposed on the arrangement of liquid crystals in the liquid crystal display panel. The process of preparing the pixel array can be compatible with that of the touch control dual-gate TFTs, greatly lowering cost. | 06-26-2014 |
20140184536 | TOUCH PANEL AND TOUCH DETECTING METHOD THEREFOR - A touch panel, which includes a plurality of signal input ends and a plurality of signal output ends, where the touch panel further includes at least one signal detecting unit which includes: a signal inputting unit, a preamplifier, and a signal separating unit; where the signal inputting unit is configured to input driving signals respectively having n frequencies, where n is an integer not less than 2; the preamplifier is configured to acquire the output signals outputted from the touch panel, and amplify and output the signals to the signal separating unit; the signal separating unit, which includes n band-pass filters, is configured to separate the signals respectively having n frequencies. In the touch panels according to embodiments of the present invention, the blind zone of the touch panel can be decreased or even eliminated, thus enlarging the detectable region and greatly improving the detection sensitivity of the touch panel. | 07-03-2014 |
20140232690 | MUTUAL CAPACITIVE TOUCH PANEL - The present invention provides a mutual capacitive touch panel, including: a plurality of driving lines; a plurality of sensing lines intersecting with the plurality of driving lines; a signal output unit disposed at input ends of the driving lines is configured to output driving signals with different frequencies to all the driving lines; a preamplifier disposed at output ends of the sensing lines is configured to capture sensing signals from the sensing lines, and amplify and then output the sensing signals to a signal separation unit; the signal separation unit connected to the preamplifier is configured to separate the sensing signals with different frequencies and obtain addresses of the driving lines corresponding to the sensing signals. In the present invention, driving signals with different frequencies are outputted by the signal output unit to all the driving lines, respectively. | 08-21-2014 |
20150015529 | CONNECTION APPARATUS FOR ELECTRICALLY CONDUCTIVE PADS AND TOUCH CONTROL SCREEN - A connection apparatus for electrically conductive pads includes a first substrate and a second substrate arranged in opposition, wherein a plurality of first electrically conductive pads are arranged on the inside of the first substrate, and a plurality of second electrically conductive pads are arranged on the inside of the second substrate. An electrically conductive glue is arranged between the first electrically conductive pads and the second electrically conductive pads, and the first electrically conductive pads each include a first body, the second electrically conductive pads each include a second body, and the first body and/or the second body includes a hollow portion or portions. The electrically conductive pads with a hollow portion(s) allowing light rays to illuminate and solidify the electrically conductive for bonding and interconnecting the upper and lower electrically conductive pads. | 01-15-2015 |