Patent application number | Description | Published |
20080236580 | Method and system for detecting the level of anesthesia agent in an anesthesia vaporizer - A method of detecting a level of anesthetic agent in an anesthesia vaporizer is disclosed. The anesthetic agent forms a column of liquid within an external indicator; the method projects a beam of light into the external indicator. The method further receives the beam of light after the beam of light has traveled through the column of liquid, and detects when the level of anesthetic agent drops below a predetermined level. | 10-02-2008 |
20110102796 | Method and system for detecting the level of anesthesia agent in an anesthesia vaporizer - A method of detecting a level of anesthesia agent in an anesthesia vaporizer is disclosed. The anesthesia agent forms a column of liquid within an external indicator; the method projects a beam of light into the external indicator. The method further receives the beam of light after the beam of light has traveled through the column of liquid, and detects when the level of anesthesia agent drops below a predetermined level. | 05-05-2011 |
20130236980 | Methods, Devices, Systems and Compositions for Detecting Gases - A method of monitoring a respiratory stream can be provided by monitoring color change of a color change material to determine a CO2 level of the respiratory stream in contact with the color change material by emitting visible light onto the color change material. Related devices, systems, and compositions are also disclosed. | 09-12-2013 |
20130259749 | METHODS, DEVICES, SYSTEMS, AND COMPOSITIONS FOR DETECTING GASES - A method of monitoring a respiratory stream can be provided by monitoring color change of a color change material to determine a CO2 level of the respiratory stream in contact with the color change material by emitting visible light onto the color change material. Related devices, systems, and compositions are also disclosed. | 10-03-2013 |
Patent application number | Description | Published |
20110056368 | ENERGY STORAGE AND GENERATION SYSTEMS AND METHODS USING COUPLED CYLINDER ASSEMBLIES - In various embodiments, pneumatic cylinder assemblies are coupled in series pneumatically, thereby reducing a range of force produced by or acting on the pneumatic cylinder assemblies during expansion or compression of a gas. | 03-10-2011 |
20110107755 | ENERGY STORAGE AND GENERATION SYSTEMS AND METHODS USING COUPLED CYLINDER ASSEMBLIES - In various embodiments, pneumatic cylinder assemblies are coupled in series pneumatically, thereby reducing a range of force produced by or acting on the pneumatic cylinder assemblies during expansion or compression of a gas. | 05-12-2011 |
20110314803 | FORMING LIQUID SPRAYS IN COMPRESSED-GAS ENERGY STORAGE SYSTEMS FOR EFFECTIVE HEAT EXCHANGE - In various embodiments, efficiency of energy storage and recovery systems compressing and expanding gas is improved via heat exchange between the gas and a heat-transfer fluid. | 12-29-2011 |
20120000557 | SYSTEMS AND METHODS FOR REDUCING DEAD VOLUME IN COMPRESSED-GAS ENERGY STORAGE SYSTEMS - In various embodiments, dead space and associated coupling losses are reduced in energy storage and recovery systems employing compressed air. | 01-05-2012 |
20120085086 | FLUID-FLOW CONTROL IN ENERGY STORAGE AND RECOVERY SYSTEMS - In various embodiments, compressed-gas energy storage and recovery systems feature one or more valves, which may be disposed within end caps of cylinder assemblies in which gas is expanded and/or compressed, for admitting fluid to and/or exhausting fluid from the cylinder assembly. | 04-12-2012 |
20120119513 | Energy storage and generation systems and methods using coupled cylinder assemblies - In various embodiments, cylinder assemblies are coupled in series pneumatically, thereby reducing a range of force produced by or acting on the cylinder assemblies during expansion or compression of a gas. | 05-17-2012 |
20130298760 | SYSTEMS AND METHODS FOR REDUCING DEAD VOLUME IN COMPRESSED-GAS ENERGY STORAGE SYSTEMS - In various embodiments, dead space and associated coupling losses are reduced in energy storage and recovery systems employing compressed air. | 11-14-2013 |
20130327029 | ENERGY STORAGE AND GENERATION SYSTEMS AND METHODS USING COUPLED CYLINDER ASSEMBLIES - In various embodiments, cylinder assemblies are coupled in series pneumatically, thereby reducing a range of force produced by or acting on the cylinder assemblies during expansion or compression of a gas. | 12-12-2013 |
20130327033 | FORMING LIQUID SPRAYS IN COMPRESSED-GAS ENERGY STORAGE SYSTEMS FOR EFFECTIVE HEAT EXCHANGE - In various embodiments, efficiency of energy storage and recovery systems compressing and expanding gas is improved via heat exchange between the gas and a heat-transfer fluid. | 12-12-2013 |
20140047826 | FLUID-FLOW CONTROL IN ENERGY STORAGE AND RECOVERY SYSTEMS - In various embodiments, compressed-gas energy storage and recovery systems feature one or more valves, which may be disposed within end caps of cylinder assemblies in which gas is expanded and/or compressed, for admitting fluid to and/or exhausting fluid from the cylinder assembly. | 02-20-2014 |
Patent application number | Description | Published |
20080220606 | SELF-ALIGNED METAL TO FORM CONTACTS TO Ge CONTAINING SUBSTRATES AND STRUCTURE FORMED THEREBY - A method for forming germano-silicide contacts atop a Ge-containing layer that is more resistant to etching than are conventional silicide contacts that are formed from a pure metal is provided. The method of the present invention includes first providing a structure which comprises a plurality of gate regions located atop a Ge-containing substrate having source/drain regions therein. After this step of the present invention, a Si-containing metal layer is formed atop the said Ge-containing substrate. In areas that are exposed, the Ge-containing substrate is in contact with the Si-containing metal layer. Annealing is then performed to form a germano-silicide compound in the regions in which the Si-containing metal layer and the Ge-containing substrate are in contact; and thereafter, any unreacted Si-containing metal layer is removed from the structure using a selective etch process. In some embodiments, an additional annealing step can follow the removal step. The method of the present invention provides a structure having a germano-silicide contact layer atop a Ge-containing substrate, wherein the germano-silicide contact layer contains more Si than the underlying Ge-containing substrate. | 09-11-2008 |
20080227283 | SELF-ALIGNED METAL TO FORM CONTACTS TO Ge CONTAINING SUBSTRATES AND STRUCTURE FORMED THEREBY - A method for forming gennano-silicide contacts atop a Ge-containing layer that is more resistant to etching than are conventional silicide contacts that are formed from a pure metal is provided. The method of the present invention includes first providing a structure which comprises a plurality of gate regions located atop a Ge-containing substrate having source/drain regions therein. After this step of the present invention, a Si-containing metal layer is formed atop the said Ge-containing substrate. In areas that are exposed, the Ge-containing substrate is in contact with the Si-containing metal layer. Annealing is then performed to form a germano-silicide compound in the regions in which the Si-containing metal layer and the Ge-containing substrate are in contact; and thereafter, any unreacted Si-containing metal layer is removed from the structure using a selective etch process. In some embodiments, an additional annealing step can follow the removal step. The method of the present invention provides a structure having a germano-silicide contact layer atop a Ge-containing substrate, wherein the germano-silicide contact layer contains more Si than the underlying Ge-containing substrate. | 09-18-2008 |
20080248616 | Integration of strained Ge into advanced CMOS technology - A structure and method of fabrication for PFET devices in a compressively strained Ge layer is disclosed. The fabrication method of such devices is compatible with standard CMOS technology and it is fully scalable. The processing includes selective epitaxial depositions of an over 50% Ge content buffer layer, a pure Ge layer, and a SiGe top layer. Fabricated buried channel PMOS devices hosted in the compressively strained Ge layer show superior device characteristics relative to similar Si devices. | 10-09-2008 |
20090212366 | CONTACT SCHEME FOR FINFET STRUCTURES WITH MULTIPLE FINs - A FINFET-containing structure having multiple FINs that are merged together without source/drain contact pads or a local interconnect is provided. In accordance with the present invention, the inventive structure includes a plurality of semiconducting bodies (i.e., FINs) which extend above a surface of a substrate. A common patterned gate stack surrounds the plurality of semiconducting bodies and a nitride-containing spacer is located on sidewalls of the common patterned gate stack. An epitaxial semiconductor layer is used to merge each of the semiconducting bodies together. | 08-27-2009 |
20100237425 | High Threshold Voltage NMOS Transistors For Low Power IC Technology - Transistors exhibiting different electrical characteristics such as different switching threshold voltage or different leakage characteristics are formed on the same chip or wafer by selectively removing a film or layer which can serve as an out-diffusion sink for an impurity region such as a halo implant and out-diffusing an impurity such as boron into the out-diffusion sink, leaving the impurity region substantially intact where the out-diffusion sink has been removed. In forming CMOS integrated circuits, such a process allows substantially optimal design for both low-leakage and low threshold transistors and allows a mask and additional associated processes to be eliminated, particularly where a tensile film is employed to increase electron mobility since the tensile film can be removed from selected NMOS transistors concurrently with removal of the tensile film from PMOS transistors. | 09-23-2010 |
20110318897 | Method of Forming a Shallow Trench Isolation Embedded Polysilicon Resistor - Forming a polysilicon embedded resistor within the shallow trench isolations separating the active area of two adjacent devices, minimizing the electrical interaction between two devices and reducing the capacitive coupling or leakage therebetween. The precision polysilicon resistor is formed independently from the formation of gate electrodes by creating a recess region within the STI region when the polysilicon resistor is embedded within the STI recess region. The polysilicon resistor is decoupled from the gate electrode, making it immune to gate electrode related processes. The method forms the polysilicon resistor following the formation of STIs but before the formation of the p-well and n-well implants. In another embodiment the resistor is formed following the formation of the STIs but after the formation of the well implants. | 12-29-2011 |
20130161745 | SOURCE-DRAIN EXTENSION FORMATION IN REPLACEMENT METAL GATE TRANSISTOR DEVICE - In one embodiment a transistor structure includes a gate stack disposed on a surface of a semiconductor body. The gate stack has a layer of gate dielectric surrounding gate metal and overlies a channel region in the semiconductor body. The transistor structure further includes a source having a source extension region and a drain having a drain extension region formed in the semiconductor body, where each extension region has a sharp, abrupt junction that overlaps an edge of the gate stack. Also included is a punch through stopper region having an implanted dopant species beneath the channel in the semiconductor body between the source and the drain. There is also a shallow channel region having an implanted dopant species located between the punch through stopper region and the channel. Both bulk semiconductor and silicon-on-insulator transistor embodiments are described. | 06-27-2013 |
20130161763 | SOURCE-DRAIN EXTENSION FORMATION IN REPLACEMENT METAL GATE TRANSISTOR DEVICE - A method includes forming on a surface of a semiconductor a dummy gate structure comprised of a plug; forming a first spacer surrounding the plug, the first spacer being a sacrificial spacer; and performing an angled ion implant so as to implant a dopant species into the surface of the semiconductor adjacent to an outer sidewall of the first spacer to form a source extension region and a drain extension region, where the implanted dopant species extends under the outer sidewall of the first spacer by an amount that is a function of the angle of the ion implant. The method further includes performing a laser anneal to activate the source extension and the drain extension implant. The method further includes forming a second spacer surrounding the first spacer, removing the first spacer and the plug to form an opening, and depositing a gate stack in the opening. | 06-27-2013 |
20130196476 | HIGH THRESHOLD VOLTAGE NMOS TRANSISTORS FOR LOW POWER IC TECHNOLOGY - Transistors exhibiting different electrical characteristics such as different switching threshold voltage or different leakage characteristics are formed on the same chip or wafer by selectively removing a film or layer which can serve as an out-diffusion sink for an impurity region such as a halo implant and out-diffusing an impurity such as boron into the out-diffusion sink, leaving the impurity region substantially intact where the out-diffusion sink has been removed. In forming CMOS integrated circuits, such a process allows substantially optimal design for both low-leakage and low threshold transistors and allows a mask and additional associated processes to be eliminated, particularly where a tensile film is employed to increase electron mobility since the tensile film can be removed from selected NMOS transistors concurrently with removal of the tensile film from PMOS transistors. | 08-01-2013 |
20140191297 | STRAINED FINFET WITH AN ELECTRICALLY ISOLATED CHANNEL - A fin structure includes an optional doped well, a disposable single crystalline semiconductor material portion, and a top semiconductor portion formed on a substrate. A disposable gate structure straddling the fin structure is formed, and end portions of the fin structure are removed to form end cavities. Doped semiconductor material portions are formed on sides of a stack of the disposable single crystalline semiconductor material portion and a channel region including the top semiconductor portion. The disposable single crystalline semiconductor material portion may be replaced with a dielectric material portion after removal of the disposable gate structure or after formation of the stack. The gate cavity is filled with a gate dielectric and a gate electrode. The channel region is stressed by the doped semiconductor material portions, and is electrically isolated from the substrate by the dielectric material portion. | 07-10-2014 |
20140252413 | SILICON-GERMANIUM FINS AND SILICON FINS ON A BULK SUBSTRATE - A first silicon-germanium alloy layer is formed on a semiconductor substrate including silicon. A stack of a first silicon layer and a second silicon-germanium alloy layer is formed over a first region of the first silicon-germanium alloy layer, and a second silicon layer thicker than the first silicon layer is formed over a second region of the first silicon-germanium alloy layer. At least one first semiconductor fin is formed in the first region, and at least one second semiconductor fin is formed in the second region. Remaining portions of the first silicon layer are removed to provide at least one silicon-germanium alloy fin in the first region, while at least one silicon fin is provided in the second region. Fin field effect transistors can be formed on the at least one silicon-germanium alloy fin and the at least one silicon fin. | 09-11-2014 |
20140252479 | SEMICONDUCTOR FIN ISOLATION BY A WELL TRAPPING FIN PORTION - A bulk semiconductor substrate including a first semiconductor material is provided. A well trapping layer including a second semiconductor material and a dopant is formed on a top surface of the bulk semiconductor substrate. The combination of the second semiconductor material and the dopant within the well trapping layer is selected such that diffusion of the dopant is limited within the well trapping layer. A device semiconductor material layer including a third semiconductor material can be epitaxially grown on the top surface of the well trapping layer. The device semiconductor material layer, the well trapping layer, and an upper portion of the bulk semiconductor substrate are patterned to form at least one semiconductor fin. Semiconductor devices formed in each semiconductor fin can be electrically isolated from the bulk semiconductor substrate by the remaining portions of the well trapping layer. | 09-11-2014 |
20140377924 | STRAINED FINFET WITH AN ELECTRICALLY ISOLATED CHANNEL - A fin structure includes an optional doped well, a disposable single crystalline semiconductor material portion, and a top semiconductor portion formed on a substrate. A disposable gate structure straddling the fin structure is formed, and end portions of the fin structure are removed to form end cavities. Doped semiconductor material portions are formed on sides of a stack of the disposable single crystalline semiconductor material portion and a channel region including the top semiconductor portion. The disposable single crystalline semiconductor material portion may be replaced with a dielectric material portion after removal of the disposable gate structure or after formation of the stack. The gate cavity is filled with a gate dielectric and a gate electrode. The channel region is stressed by the doped semiconductor material portions, and is electrically isolated from the substrate by the dielectric material portion. | 12-25-2014 |
20150021625 | SEMICONDUCTOR FIN ISOLATION BY A WELL TRAPPING FIN PORTION - A bulk semiconductor substrate including a first semiconductor material is provided. A well trapping layer including a second semiconductor material and a dopant is formed on a top surface of the bulk semiconductor substrate. The combination of the second semiconductor material and the dopant within the well trapping layer is selected such that diffusion of the dopant is limited within the well trapping layer. A device semiconductor material layer including a third semiconductor material can be epitaxially grown on the top surface of the well trapping layer. The device semiconductor material layer, the well trapping layer, and an upper portion of the bulk semiconductor substrate are patterned to form at least one semiconductor fin. Semiconductor devices formed in each semiconductor fin can be electrically isolated from the bulk semiconductor substrate by the remaining portions of the well trapping layer. | 01-22-2015 |
20150340381 | FORMING FINS OF DIFFERENT SEMICONDUCTOR MATERIALS ON THE SAME SUBSTRATE - A method of manufacturing a semiconductor device, by etching a region of an SOI substrate so that only a portion of the original semiconductor is present above the insulator layer. After etching has occurred, a different semiconductor material is grown in the etched region, and fins are formed. An isolation layer is deposited to a height above that the base semiconductor of the etched region. | 11-26-2015 |
Patent application number | Description | Published |
20090219051 | HYBRID NANOTUBE/CMOS DYNAMICALLY RECONFIGURABLE ARCHITECTURE AND AN INTEGRATED DESIGN OPTIMIZATION METHOD AND SYSTEM THEREFOR - A hybrid nanotube, high-performance, dynamically reconfigurable architecture, NATURE, is provided, and a design optimization flow method and system, NanoMap. A run-time reconfigurable architecture is provided by associating a non-volatile universal memory to each logic element to enable cycle-by-cycle reconfiguration and logic folding, while remaining CMOS compatible. Through logic folding, significant logic density improvement and flexibility in performing area-delay tradeoffs are possible. NanoMap incorporates temporal logic folding during the logic mapping, temporal clustering and placement steps. NanoMap provides for automatic selection of a best folding level, and uses force-direct scheduling to balance resources across folding stages. Mapping can thereby target various optimization objectives and user constraints. A high-density, high-speed carbon nanotube RAM can be implemented as the universal memory, allowing on-chip multi-context configuration storage, enabling fine-grain temporal logic folding, and providing a significant increase in relative logic density. | 09-03-2009 |
20130135008 | METHOD AND SYSTEM FOR A RUN-TIME RECONFIGURABLE COMPUTER ARCHITECTURE - A reconfigurable computer architecture is disclosed. The reconfigurable computer architecture has a plurality of logic elements, a plurality of connection switching elements, and a plurality of volatile and/or non-volatile configuration random access memories (RAMs). Each of the configuration RAMs is electrically coupled to at least one of the plurality of logic elements or at least one of the connection switching elements. | 05-30-2013 |
20140059282 | HYBRID NANOTUBE/CMOS DYNAMICALLY RECONFIGURABLE ARCHITECTURE AND SYSTEM THEREFORE - A hybrid nanotube, high-performance, dynamically reconfigurable architecture, NATURE, is provided, and a design optimization flow method and system, NanoMap. A run-time reconfigurable architecture is provided by associating a non-volatile universal memory to each logic element to enable cycle-by-cycle reconfiguration and logic folding, while remaining CMOS compatible. Through logic folding, significant logic density improvement and flexibility in performing area-delay tradeoffs are possible. NanoMap incorporates temporal logic folding during the logic mapping, temporal clustering and placement steps. NanoMap provides for automatic selection of a best folding level, and uses force-direct scheduling to balance resources across folding stages. Mapping can thereby target various optimization objectives and user constraints. A high-density, high-speed carbon nanotube RAM can be implemented as the universal memory, allowing on-chip multi-context configuration storage, enabling fine-grain temporal logic folding, and providing a significant increase in relative logic density. | 02-27-2014 |
Patent application number | Description | Published |
20130007518 | TRANSPARENT FAILOVER - Described are embodiments directed at persistent handles that are used to retain state across network failures and server failovers. Persistent handles are requested by a client after a session has been established with a file server. The request for the persistent handle includes a handle identifier generated by the client. The server uses the handle identifier to associate with state information. When there is a network failure or a server failover, and a reconnection to the client, the handle identifier is used to identify replayed requests that if replayed would create an inconsistent state on the server. The replayed requests are then appropriately handled. | 01-03-2013 |
20130067095 | SMB2 SCALEOUT - Systems and methods are disclosed for clients and servers operating in a scaled cluster environment. Efficiencies are introduced to the process of connecting a client to a clustered environment by providing the client with the ability to attempt a connection with multiple servers in parallel. Servers operating the in the clustered environment are also capable of providing persistent storage of file handles and other state information. Ownership of the state information and persistent handles may be transferred between servers, thereby providing clients with the opportunity to move from one server to another while maintaining access to resources in the clustered environment. | 03-14-2013 |
20140372521 | TRANSPARENT FAILOVER - Described are embodiments directed at persistent handles that are used to retain state across network failures and server failovers. Persistent handles are requested by a client after a session has been established with a file server. The request for the persistent handle includes a handle identifier generated by the client. The server uses the handle identifier to associate with state information. When there is a network failure or a server failover, and a reconnection to the client, the handle identifier is used to identify replayed requests that if replayed would create an inconsistent state on the server. The replayed requests are then appropriately handled. | 12-18-2014 |
20150365482 | SMB2 SCALEOUT - Systems and methods are disclosed for clients and servers operating in a scaled cluster environment. Efficiencies are introduced to the process of connecting a client to a clustered environment by providing the client with the ability to attempt a connection with multiple servers in parallel. Servers operating the in the clustered environment are also capable of providing persistent storage of file handles and other state information. Ownership of the state information and persistent handles may be transferred between servers, thereby providing clients with the opportunity to move from one server to another while maintaining access to resources in the clustered environment. | 12-17-2015 |
Patent application number | Description | Published |
20090280002 | Method and system for determining gas turbine tip clearance - A system for sensing at least one physical characteristic associated with an engine including a turbine having a plurality of blades turning inside a casing, the system including: a pressure sensor coupled substantially adjacent to the casing and including at least one output; a port in the turbine casing for communicating a pressure indicative of a clearance between the blades and casing to the pressure sensor; a cooling cavity substantially surrounding the pressure sensor; and, an inlet for receiving fluid from the engine and feeding the fluid to the cooling cavity to cool the pressure sensor; wherein, the pressure sensor output is indicative of the clearance between the blades and casing. | 11-12-2009 |
20100139408 | Low pass filter semiconductor structures for use in transducers for measuring low dynamic pressures in the presence of high static pressures - A semiconductor filter is provided to operate in conjunction with a differential pressure transducer. The filter receives a high and very low frequency static pressure attendant with a high frequency low dynamic pressure at one end, the filter operates to filter said high frequency dynamic pressure to provide only the static pressure at the other filter end. A differential transducer receives both dynamic and static pressure at one input port and receives said filtered static pressure at the other port where said transducer provides an output solely indicative of dynamic pressure. The filter in one embodiment has a series of etched channels directed from an input end to an output end. The channels are etched pores of extremely small diameter and operate to attenuate or filter the dynamic pressure. In another embodiment, a spiral tubular groove is found between a silicon wafer and a glass cover wafer, an input port of the groove receives both the static and dynamic pressure with an output port of the groove providing only static pressure. The groove filters attenuate dynamic pressure to enable the differential transducer to provide an output only indicative of dynamic pressure by cancellation of the static pressure. | 06-10-2010 |
20110061467 | LOW PASS FILTER SEMICONDUCTOR STRUCTURES FOR USE IN TRANSDUCERS FOR MEASURING LOW DYNAMIC PRESSURES IN THE PRESENCE OF HIGH STATIC PRESSURES - A semiconductor filter is provided to operate in conjunction with a differential pressure transducer. The filter receives a high and very low frequency static pressure attendant with a high frequency low dynamic pressure at one end, the filter operates to filter said high frequency dynamic pressure to provide only the static pressure at the other filter end. A differential transducer receives both dynamic and static pressure at one input port and receives said filtered static pressure at the other port where said transducer provides an output solely indicative of dynamic pressure. The filter in one embodiment has a series of etched channels directed from an input end to an output end. The channels are etched pores of extremely small diameter and operate to attenuate or filter the dynamic pressure. In another embodiment, a spiral tubular groove is found between a silicon wafer and a glass cover wafer, an input port of the groove receives both the static and dynamic pressure with an output port of the groove providing only static pressure. The groove filters attenuate dynamic pressure to enable the differential transducer to provide an output only indicative of dynamic pressure by cancellation of the static pressure. | 03-17-2011 |
20110188994 | METHOD AND SYSTEM FOR DETERMINING GAS TURBINE TIP CLEARANCE - A system for sensing at least one physical characteristic associated with an engine including a turbine having a plurality of blades turning inside a casing, the system including: a pressure sensor coupled substantially adjacent to the casing and including at least one output; a port in the turbine casing for communicating a pressure indicative of a clearance between the blades and casing to the pressure sensor; a cooling cavity substantially surrounding the pressure sensor; and, an inlet for receiving fluid from the engine and feeding the fluid to the cooling cavity to cool the pressure sensor; wherein, the pressure sensor output is indicative of the clearance between the blades and casing. | 08-04-2011 |
20130091940 | Method and System for Determining Gas Turbine Tip Clearance - A system for sensing at least one physical characteristic associated with an engine including a turbine having a plurality of blades turning inside a casing, the system including: a pressure sensor coupled substantially adjacent to the casing and including at least one output; a port in the turbine casing for communicating a pressure indicative of a clearance between the blades and casing to the pressure sensor; a cooling cavity substantially surrounding the pressure sensor; and, an inlet for receiving fluid from the engine and feeding the fluid to the cooling cavity to cool the pressure sensor; wherein, the pressure sensor output is indicative of the clearance between the blades and casing. | 04-18-2013 |
Patent application number | Description | Published |
20080276712 | Pressure transducer employing a micro-filter and emulating an infinite tube pressure transducer - A pressure transducer for measuring pressures in high temperature environments employs a tube which is terminated at one end by an acoustic micro-filter. The acoustic filter or micro-filter has a plurality of apertures extending from one end to the other end, each aperture is of a small diameter as compared to the diameter of the transducer and the damper operates to absorb acoustic waves impinging on it with limited or no reflection. Mounted to the tube is a pressure transducer with a diaphragm flush with the inner wall of the tube. The tube is mounted in an aperture in a casing of a gas turbine operating at a high temperature. The hot gases propagate through the tube where the pressure of the gases are measured by the transducer coupled to the tube and where the acoustic filter operates to absorb acoustic waves impinging on it with little or no reflection, therefore enabling the pressure transducer to be mainly responsive to high frequency waves associated with the gas turbine operation. | 11-13-2008 |
20090139339 | Pressure transducer employing a micro-filter and emulating an infinite tube pressure transducer - A pressure transducer for measuring pressures in high temperature environments employs a tube which is terminated at one end by an acoustic micro-filter. The acoustic filter or micro-filter has a plurality of apertures extending from one end to the other end, each aperture is of a small diameter as compared to the diameter of the transducer and the damper operates to absorb acoustic waves impinging on it with limited or no reflection. Mounted to the tube is a pressure transducer with a diaphragm flush with the inner wall of the tube. The tube is mounted in an aperture in a casing of a gas turbine operating at a high temperature. The hot gases propagate through the tube where the pressure of the gases are measured by the transducer coupled to the tube and where the acoustic filter operates to absorb acoustic waves impinging on it with little or no reflection, therefore enabling the pressure transducer to be mainly responsive to high frequency waves associated with the gas turbine operation. | 06-04-2009 |
20100175482 | PRESSURE TRANSDUCER EMPLOYING A MICRO-FILTER AND EMULATING AN INFINITE TUBE PRESSURE TRANSDUCER - It is an objective of the present invention to provide a pressure transducer assembly for measuring pressures in high temperature environments that employs an elongated tube which is terminated at one end by an acoustic micro-filter. The micro-filter has a plurality of apertures extending from one end to the other end, each aperture is of a small diameter as compared to the diameter of the transducer and the damper operates to absorb acoustic waves impinging on it with limited or no reflection. To improve the absorption of acoustic waves, the elongated tube may be tapered and/or mounted to a support block and further convoluted to reduce the overall size and mass of the device. A pressure transducer with a diaphragm flush may be mounted to the elongated tube and extend through to the inner wall of the tube. Hot gases propagate through the elongated tube and their corresponding pressures are measured by the transducer. The acoustic filter operates to absorb acoustic waves resultant from the hot gases, therefore enabling the pressure transducer to be mainly responsive to high frequency waves associated with the gas turbine operation. | 07-15-2010 |
20110296924 | PRESSURE TRANSDUCER EMPLOYING A MICRO-FILTER AND EMULATING AN INFINITE TUBE PRESSURE TRANSDUCER - A pressure transducer assembly for measuring pressures in high temperature environments employing an elongated tube which is terminated at one end by an acoustic micro-filter. The micro-filter is operative to absorb acoustic waves impinging on it with limited or no reflection. To improve the absorption of acoustic waves, the elongated tube may be tapered and/or mounted to a support block and further convoluted to reduce the overall size and mass of the device. A pressure transducer with a diaphragm flush may be mounted to the elongated tube and extend through to the inner wall of the tube. Hot gases propagate through the elongated tube and their corresponding pressures are measured by the transducer. The acoustic filter operates to absorb acoustic waves resultant from the hot gases, therefore enabling the pressure transducer to be mainly responsive to high frequency waves associated with the gas turbine operation. | 12-08-2011 |
20120073377 | ENHANCED STATIC-DYNAMIC PRESSURE TRANSDUCER SUITABLE FOR USE IN GAS TURBINES AND OTHER COMPRESSOR APPLICATIONS - A transducer comprising a filter assembly that measures low amplitude, dynamic pressure perturbations superimposed on top of a high static pressure through the implementation of a low-pass mechanical filter assembly. The filter assembly may comprise a dual lumen reference tube and a removable filter subassembly further comprising a porous metal filter and narrow diameter tube. The transducer, which may be capable of operating at ultra-high temperatures and in harsh environments, may comprise of a static piezoresistive pressure sensor, which measures the large pressures on the order of 200 psi and greater, and an ultrasensitive, dynamic piezoresistive pressure sensor which may capture small, high frequency pressure oscillations on the order of a few psi. The filter assembly may transmit static pressure to the back of the dynamic pressure sensor to cancel out the static pressure present at the front of the sensor while removing dynamic pressure. | 03-29-2012 |
20130098159 | LOW PASS FILTER SEMICONDUCTOR STRUCTURES FOR USE IN TRANSDUCERS FOR MEASURING LOW DYNAMIC PRESSURES IN THE PRESENCE OF HIGH STATIC PRESSURES - A semiconductor filter is provided to operate in conjunction with a differential pressure transducer. In one embodiment, a method comprises receiving, at a filter, a pressure, wherein the pressure includes a static pressure component and a dynamic pressure component; filtering, by the filter, at least the dynamic pressure component of the pressure; outputting, from the filter, a filtered pressure; receiving, at a first surface of a diaphragm, the pressure; receiving, at a second surface of the diaphragm, the filtered pressure, wherein the second surface of the diaphragm is operatively coupled to the filter; and measuring, at a sensor operatively coupled to the diaphragm, a difference between the pressure and the filtered pressure. | 04-25-2013 |