Patent application number | Description | Published |
20080238274 | Noise-suppressing dishwasher - Disclosed is a dishwasher that excludes operating noise transferred forwardly through a gap between a lower end of a main body and a mounting surface, thus minimizing noise perceived by a user. The dishwasher includes a main body provided with a washing chamber; and a front panel installed at a lower part of a front surface of the main body, and provided with a lower part covering a gap between the lower end of the main body and a mounting surface. The front panel includes a closure made of a flexible material connected to the lower part of the front panel. | 10-02-2008 |
20090110542 | Fan guard and outdoor unit for air conditioner having the same - An outdoor unit for an air conditioner is disclosed. The outdoor unit according to the present invention comprises a housing which has an air inlet and an air outlet, a ventilation fan rotatably mounted in the housing, and a fan guard connected to the housing to cover the air outlet. Here, the fan guard comprises a plurality of closed ribs arranged sequentially and concentrically between a center and an outline thereof, and a plurality of radial ribs arranged in radial directions to interconnect the plurality of closed ribs, in such a manner that some of the closed ribs, which are disposed at intermediate positions near tips of the ventilation fan, are at a further distance from the ventilation fan than the other closed ribs, which are disposed near the center and the outline. Accordingly, since the fan guard is convexly raised at a position corresponding to the tips of the ventilation fan, thereby guaranteeing a predetermined space between the fan guard and the tips where the airflow is fastest, the flow resistance and the flow-induced noise can be reduced. | 04-30-2009 |
20090129041 | Stacked semiconductor module, method of fabricating the same, and electronic system using the same - A stacked semiconductor module, a method of fabricating the same, and an electronic system using the module are provided. A first semiconductor module having a plurality of semiconductor devices mounted on a rigid printed circuit board (PCB) and a second semiconductor module having a plurality of other semiconductor devices mounted on a flexible PCB are provided. On the rigid PCB a number L of first tabs may be disposed on a first surface, and a number K of second tabs may be disposed on a second surface of the rigid PCB. The flexible PCB may have a number M of third tabs on a third surface, and a number N of fourth tabs on a fourth surface of the flexible PCB. The second tabs may be combined with the third tabs using a conductive adhesive. The third tabs may be electrically connected to corresponding ones of the second tabs. | 05-21-2009 |
20090140972 | LIGHT SOURCE ASSEMBLY, LIQUID CRYSTAL DISPLAY, AND METHOD OF DRIVING LIGHT SOURCE ASSEMBLY - A light source assembly includes a light source which emits light; a detector which detects the light and generates a light signal based on a property of the light; an operator operably connected to the detector and which receives the light signal and calculates a color coordinate of the light source based on the light signal; a comparator operably connected to the operator and which compares the color coordinate of the light source to a predetermined reference color coordinate; and a control unit operably connected to the comparator and which controls a pulse width modulation signal transmitted to the light source based on a result of the comparison of the comparator. | 06-04-2009 |
20090141246 | PROJECTION TYPE IMAGE DISPLAY APPARATUS - A projection type image display apparatus includes: a cabinet; a screen which is provided in the cabinet; a display device which is placed inside the cabinet and forms an image; and an optical system which projects an image formed by the display device to the screen and comprises at least one mirror, a supporter for supporting the mirror, and a frame through which the supporter is fastened to the cabinet, all of the mirror, the supporter and the frame being disposed within a single interior space formed by the cabinet and the screen. | 06-04-2009 |
20090153957 | PROJECTION-TYPE DISPLAY APPARATUS AND DISPLAY METHOD THEREOF - A projection-type display apparatus and a display method thereof are disclosed, the projection-type display apparatus including a coated portion which is formed on a surface of a substrate, and which scans a video onto a screen, and a patterned portion which is formed on another surface of the substrate in a serrated pattern, wherein the serrated pattern is formed on the substrate according to the surface area of the patterned portion and the depth of the serrated pattern. A serrated pattern is formed on a substrate forming a reflective portion to reflect a video on a screen, so the cooling surface area of the substrate is increased, thereby compensating for distortions in video scanned onto the screen. | 06-18-2009 |
20090179239 | CMOS image sensors and methods of manufacturing the same - A complementary metal-oxide-semiconductor image sensor may include: a semiconductor substrate; a photodiode formed on a first portion of the semiconductor substrate; a transfer gate formed on the semiconductor substrate, near the photodiode, to transfer optical charges accumulated in the photodiode; a floating diffusion area formed on a second portion of the semiconductor substrate, on an opposite side of the transfer gate from the photodiode, to accommodate the optical charges; and/or a channel area formed under the transfer gate and contacting a side of the photodiode to transfer the optical charges. The transfer gate may be formed, at least in part, of transparent material. A method of manufacturing a complimentary metal-oxide-semiconductor image sensor may include: forming the photodiode; forming the floating diffusion area, separate from the photodiode; and/or forming the transfer gate, near the photodiode, to transfer optical charges accumulated in the photodiode. | 07-16-2009 |
20090189152 | FERROELECTRIC MEMORY DEVICE - Provided is a ferroelectric memory device. The ferroelectric memory device includes an inorganic channel pattern on a substrate, a source electrode and a drain electrode spaced apart from each other on the substrate and contacting the inorganic channel pattern, a gate electrode disposed adjacent to the inorganic channel pattern, and an organic ferroelectric layer interposed between the inorganic channel pattern and the gate electrode. | 07-30-2009 |
20090191042 | SEMICONDUCTOR DEVICE MANUFACTURING APPARATUS AND WAFER LOADING/UNLOADING METHOD THEREOF - A semiconductor manufacturing apparatus and a wafer loading/unloading method thereof increase productivity. The semiconductor manufacturing apparatus includes a first boat and a second boat having a plurality of first slots and a plurality of second slots, respectively, and disposed such that the first slots and the second slots alternate each other, the first boat mounting a plurality of first wafers in the first slots to direct front faces of the first wafers in a predetermined direction, the second boat mounting a plurality of second wafers in the second slots to direct back faces of the second wafers in the predetermined direction; a reaction tube having an opening and containing the first and second boats mounting the first and second wafers; a plate sealing up the opening of the reaction tube containing the first boat and the second boat; a reaction gas supplier supplying reaction gas into the sealed reaction tube for a predetermined process; and a reaction gas exhauster exhausting the reaction gas from the reaction tube to the external of the reaction tube after the predetermined process. | 07-30-2009 |
20090200357 | Wire clamp and wire bonding apparatus having the same - A wire clamp includes a pair of clamp arms at a predetermined distance from each other to define an interval therebetween for a bonding wire, a clamp body coupled to the clamp arms, the clamp body configured to adjust the predetermined distance between the clamp arms with respect to a process to be performed, a clamping section in each clamp arm, the clamping section having concave portions facing the interval between the clamp arms, the concave portions being configured to contact the bonding wire when the clamp arms are brought close together, and at least one abrasion prevention member in each clamping section, the abrasion prevention members being configured to prevent abrasion during contact with the bonding wire. | 08-13-2009 |
20090200362 | METHOD OF MANUFACTURING A SEMICONDUCTOR PACKAGE - In a lead-free solder, a semiconductor package and a method of manufacturing the semiconductor package, the lead-free solder includes about 3.5 percent by weight to about 6 percent by weight of silver, about 0.05 percent by weight to about 0.5 percent by weight of copper and a remainder of tin. The lead-free solder is employed in the semiconductor package. The lead-free solder has high impact resistance and high heat resistance to reduce failures of the semiconductor package. | 08-13-2009 |
20090271982 | Method of forming a wiring having carbon nanotube - In a method of forming a wiring having a carbon nanotube, a lower wiring is formed on a substrate, and a catalyst layer is formed on the lower wiring. An insulating interlayer is formed on the substrate to cover the catalyst layer, and an opening is formed through the insulating interlayer to expose an upper face of the catalyst layer. A carbon nanotube wiring is formed in the opening, and an upper wiring is formed on the carbon nanotube wiring and the insulating interlayer to be electrically connected to the carbon nanotube wiring. A thermal stress is generated between the carbon nanotube wiring and the upper wiring to produce a dielectric breakdown of a native oxide layer formed on a surface of the carbon nanotube wiring. A wiring having a reduced electrical resistance between the carbon nanotube wiring and the upper wiring may be obtained. | 11-05-2009 |
20100002943 | METHOD AND APPARATUS FOR ENCODING AND DECODING IMAGE USING IMAGE SEPARATION BASED ON BIT LOCATION - Provided are method and apparatus for encoding and decoding an image by using a bit plane-based image encoding method and a block-based image encoding method respectively on bit planes based on the n-m most significant bits of an input image including n-bit pixel values and an image based on the m least significant bits of the input image. | 01-07-2010 |
20100013563 | Voltage-controlled oscillator circuit including level shifter, and semiconductor device including voltage-controlled oscillator circuit - A voltage-controlled oscillator (VCO) circuit includes a level shifter, and a semiconductor device includes the VCO circuit. The VCO circuit includes an input voltage receiver, a current mirror, and a frequency oscillator. The input voltage receiver receives a first voltage input to the VCO circuit so as to generate a first current. The current mirror copies the first current so as to generate a second current. The frequency oscillator oscillates in response to the second current. The input voltage receiver includes a level shifter and a first current generator. The level shifter shifts a voltage level of the first voltage to a voltage level of a second voltage. The first current generator generates the first current corresponding to the second voltage | 01-21-2010 |
20100020094 | METHOD OF BOOSTING A DISPLAY IMAGE, CONTROLLER UNIT FOR PERFORMING THE METHOD, AND DISPLAY APPARATUS HAVING THE CONTROLLER UNIT - Controller unit includes local dimming logic board and controller board. Local dimming logic board generates local dimming signals in response to image data received from external device. When boost-worthy portion of image data is found to satisfy predefined boosting conditions, local dimming logic board increases luminance value of backlight dimming signal supplied for corresponding boost-worthy area portion of image data. Controller board receives image data from local dimming logic board, and gamma converts peripheral area data corresponding to peripheral area of image data into converted image data using compensating gamma conversion different than that used for image data of backlight boosted area so that luminance of peripheral area adjacent to boosting area is decreased by use of compensating gamma conversion in place of normal or reference gamma conversion. Decreased luminance substantially counter compensates for increased luminance due to light from spreading into peripheral area from adjacent boosted area. | 01-28-2010 |
20100071847 | Wafer bonding apparatus - It is an aspect of the present invention to provide a wafer bonding apparatus having a pressing apparatus configured to press wafers fixed in a fixing apparatus, wherein the fixing apparatus is configured to allow the pressing apparatus to press the wafers without interference. The wafer bonding apparatus may include an upper wafer and a lower wafer, a support member configured to support the upper wafer and the lower wafer, a push member on the upper wafer, and a fixing apparatus configured to fix the push member to the support member, wherein the push member includes a fixing part extending outward from a periphery of the upper wafer, and the fixing apparatus is coupled to the fixing part. It is also an aspect of the present invention to provide a method for bonding wafers. | 03-25-2010 |
20100091731 | CHANNEL ALLOCATION METHOD AND APPARATUS FOR WIRELESS COMMUNICATION NETWORKS - A channel allocation method for use in a wireless communication environment, where Wireless Local Area Networks (WLANs) and Wireless Personal Area Networks (WPANs) coexist, includes collecting, at an access point, information on channels used by the WLANs and WPANs, determining available WLAN channels and available WPAN channels based on the channel information, allocating one of the available WLAN channels and one of the available WPAN channels to the access point, and informing the WLANs and WPANs of the allocated WLAN and WPAN channels. | 04-15-2010 |
20100110214 | Exposure apparatuses and methods to compress exposure data - A method to compress exposure data may include converting image data into a plurality of exposure data, generating new exposure data by combining part of the plurality of exposure data or by excluding part of the plurality of exposure data, and compressing the new exposure data. An exposure apparatus may include a conversion unit that converts image data into a plurality of exposure data, a control unit that generates new exposure data by combining part of the plurality of exposure data or by excluding part of the plurality of exposure data, and a compression unit that compresses the new exposure data. | 05-06-2010 |
20100118615 | Semiconductor memory device - A semiconductor memory device includes a sub memory cell array region having memory cells each connected between word lines extending in a first direction and bit lines extending in a second direction that is orthogonal to the first direction of extension of the word lines and a sub word line driver region disposed at a side of the sub memory cell array region in the first direction and including sub word line drivers that activate the word lines. A sensing region is disposed at a side of the sub memory cell array region in the second direction and including an equalizer that precharges the bit line in response to a signal transferred through a drive signal line and at least one first control signal driver that activates an inverted control signal line in response to a signal transferred through a control signal line. A conjunction region disposed at an intersection between the sub word line driver region and the sensing region, in which the inverted control signal line is connected to the drive signal line. | 05-13-2010 |
20100122984 | Packing box - A packing box for an electronic product to protect an electronic product from external impact. The packing box includes a first packing unit to pack an upper part of the product, a second packing unit passing through the first packing unit and joined to a lower part of the first packing unit, to pack a middle part of the product, and a third packing unit passing through the first and second packing units and joined to a lower part of the second packing unit, to pack a lower part of the product. The packing box is readily disassembled and allows the product to be easily repacked. | 05-20-2010 |
20100126191 | Cooling system and method of controlling the same - An oscillatory wave generating unit and an oscillatory wave sensing unit are installed at both ends of a refrigerant pipe of an evaporator of the cooling system, an amount of frost formed on the refrigerant pipe is determined by comparing a wave form of an oscillatory wave generated from one end of the refrigerant through the oscillatory wave generating unit and a wave form of the oscillatory wave sensed by the other one end of the refrigerant through the oscillatory wave sensing unit, and whether or not a defrosting operation is performed is determined by a result of the determination. The cooling system increases the accuracy in sensing the amount of the frost formed on the evaporator of a refrigerator, a Kimchi refrigerator, or an air conditioner, and respectively starts and ends the defrosting operation at proper points of time, thus enhancing a heat-exchanging performance and increasing energy efficiency. | 05-27-2010 |
20100127731 | Antifuse circuit of inverter type and method of programming the same - Example embodiments are directed to an antifuse circuit of an inverter type and a method of programming the same. The antifuse circuit has improved corrosion resistance, utilizes lesser chip area and can be programmed at a low voltage. The antifuse circuit includes a PMOS transistor with the gate coupled to a drive power voltage terminal and the source coupled to an anti-pad terminal. During programming the PMOS transistor is off and the source receives an alternating current. Programming the antifuse circuit involves trapping a plurality of electron in an STI region as a result of gate-induced drain leakage. The antifuse circuit also includes an NMOS transistor with the drain connected to the drain of the PMOS transistor, the source connected to ground and the gate connected to a program control signal. The antifuse circuit results in reliable fuse programming at a low voltage by using the PMOS transistor as an anti-fuse device. | 05-27-2010 |
20100134707 | LIQUID CRYSTAL DISPLAY - A liquid crystal display includes; first and second substrates facing each other, a liquid crystal layer interposed between the first and second substrates and including liquid crystal molecules, a first subpixel electrode disposed on the first substrate, the first subpixel electrode receiving a first data voltage, a second subpixel electrode disposed on the first substrate, the second subpixel electrode receiving a second data voltage; and a short protrusion disposed on the second substrate and simultaneously facing the first and second subpixel electrodes, wherein the liquid crystal layer is vertically aligned and has positive dielectric anisotropy. | 06-03-2010 |
20100147582 | DISPLAY PANEL AND DISPLAY DEVICE INCLUDING THE SAME - A display device comprises: a display panel including a first insulating substrate and a second insulating substrate that is arranged so as to deviate from the first insulating substrate; and an intermediate frame, wherein the intermediate frame includes: side walls that are arranged so as to correspond to four side surface of the display panel; a mounting portion which protrudes from the side walls inward and on which the first insulating substrate is mounted; and a supporting protrusion that protrudes from the mounting portion to the second insulating substrate and is arranged below the second insulating substrate and on the side of the first insulating substrate. | 06-17-2010 |
20100154130 | Damper, washing machine with the same and control method thereof - A damper including a cylinder, a piston inserted in the cylinder, a movable member disposed in the piston to be movable in the cylinder in a length direction of the cylinder, and a weight sensor mounted on an inner surface of the cylinder, facing an end of the piston, to perceive weight loaded on the piston through contact with the movable member. When applied to a washing machine, the damper is capable of perceiving accurate weight of the laundry supplied in the washing machine. | 06-24-2010 |
20100155729 | FAN-OUT UNIT AND THIN-FILM TRANSISTOR ARRAY SUBSTRATE HAVING THE SAME - A fan-out unit which can control a resistance difference among channels with efficient space utilization and a thin-film transistor (TFT) array substrate having the fan-out unit are presented. The fan-out unit includes: an insulating substrate; a first wiring layer which is formed on the insulating substrate and connected to a pad; a second wiring layer which is formed on the insulating substrate and connected to a TFT; and a resistance controller which is connected between the first wiring layer and the second wiring layer and includes a plurality of first resistors extending parallel to the first wiring layer and a plurality of second resistors extending perpendicular to the first resistors and alternately connecting to the first resistors, wherein the first resistors are longer than the second resistors. | 06-24-2010 |
20100164101 | Ball land structure having barrier pattern - Disclosed is a ball land structure suitable for use with a semiconductor package. The ball land structure includes a ball land and a barrier on a core. The barrier may be configured to connect to the ball land so as to form a barrier hole between an edge of the ball land and an edge of the barrier thus exposing a portion of the core. A solder mask may be deposited on the ball land and a portion of the core exposed by the barrier hole so as to partially expose the core. | 07-01-2010 |
20100248442 | METHODS OF FORMING A PHASE CHANGE MEMORY DEVICE - Provided are methods of forming a phase change memory device. A semiconductor device having a lower electrode and an interlayer insulating layer may be prepared. The lower electrode may be surrounded by the interlayer insulating layer. Source gases, a reaction gas and a purge gas may be injected into a process chamber of a semiconductor fabrication device to form a phase change material layer on a semiconductor substrate. The source gases may be simultaneously injected into the process chamber. The phase change material layer may be in contact with the lower electrode through the interlayer insulating layer. The phase change material layer may be etched to form a phase change memory cell in the interlayer insulating layer. An upper electrode may be formed on the phase change memory cell. | 09-30-2010 |
20100248460 | Method of forming information storage pattern - A method of forming an information storage pattern, includes placing a semiconductor substrate in a process chamber, injecting first, second and third process gases into the process chamber during a first process to form a lower layer on the substrate based on a first injection time and/or a first pause time, injecting the second process gas into the process chamber during a second process, wherein the second process gas is injected into the process chamber during a first elimination time, injecting a fourth process gas together with the second and third process gases into the process chamber during a third process in accordance with a second injection time and/or a second pause time to form an upper layer on the lower layer, and injecting the second process gas into the process chamber during a fourth process, wherein the second process gas is injected into the process chamber during a second elimination. | 09-30-2010 |
20100259963 | Data line layouts - A data line layout includes column selection lines arranged in a first direction at a layer on a memory cell array region, and data lines arranged in the first direction at the layer, the data lines being connected between I/O sense amplifiers and I/O pads. | 10-14-2010 |
20110102968 | MULTILAYER STRUCTURE, CAPACITOR INCLUDING THE MULTILAYER STRUCTURE AND METHOD OF FORMING THE SAME - In a multilayer structure and a method of forming the same, a conductive layer including a metal nitride and a dielectric layer positioned on a surface of the conductive layer and having a high dielectric constant. The metal nitride comprises one of niobium, vanadium and compositions thereof. Thus, the EOT and leakage current of the multilayer structure may be sufficiently improved. | 05-05-2011 |
20110293903 | WAVE SOLDERING APPARATUS TO APPLY BUOYANCY, SOLDERING METHOD, AND METHOD OF FORMING SOLDER BUMPS FOR FLIP CHIPS ON A SUBSTRATE - The present general inventive concept includes a wave soldering apparatus, a soldering method using the wave soldering apparatus, and a method of forming a solder bump for a flip chip. The wave soldering apparatus includes a solder bath containing a molten solder. A nozzle is arranged in the solder bath so as to upwardly spout the molten solder toward a bottom surface of a substrate that passes an upper portion of the solder bath. A liquid that is separated from the molten solder is contained in a downstream area of the solder bath, and buoyancy is applied to the molten solder, which is adhered to the substrate, by the liquid. Since the amount of the molten solder adhered to the substrate is increased by the buoyancy, it is possible to form the solder bump to have a height sufficient to use it as a flip chip. | 12-01-2011 |
20130200092 | FOLDING TYPE PACKAGE - A folding type package includes a body including first and second parts to face each other when the body is folded to enclose a product, at least one product housing part formed at the body, and a buffer part extending from the product housing part to secure a buffer space to buffer a shock applied to the product. | 08-08-2013 |