Patent application number | Description | Published |
20080219069 | DEVICE THRESHOLD CALIBRATION THROUGH STATE DEPENDENT BURNIN - Disclosed are embodiments of a method for reducing and/or eliminating mismatch. The embodiments sample the bias of one or more circuit sub-components that require a balanced state (e.g., sampling the bias of the cross-coupled transistors in each memory cell and/or sense amp in a memory array) before chip burn-in, by initiating a burn-in process during which an individually selected state is applied to each of the devices in the circuit. This fatigues the devices away from their preferred states and towards a balanced state. The bias is periodically reassessed during the burn-in process to avoid over-correction. By using this method both memory cell and sense-amplifier mismatch can be reduced in memory arrays, resulting in smaller timing uncertainty and therefore faster memories. | 09-11-2008 |
20080265982 | METHOD OF IMPROVING FUSE STATE DETECTION AND YIELD IN SEMICONDUCTOR APPLICATIONS - Disclosed are embodiments of an apparatus incorporating a detection circuit adapted for determining the state of selected fuses and a programming circuit for blowing selected fuses on demand. Also, disclosed are embodiments of an associated method. The detection circuit comprises a plurality of fuses in identical signal and reference legs in order to increase the signal margin for detecting blown fuses and/or current sources configured to pass offset currents through the signal and reference legs in order to set the trip point for detecting blown fuses between the un-blown and the minimum blown resistances. Thus, the invention provides the flexibility of single-sided fuse state detection devices with even greater sensitivity than both single-sided and differential fuse state detection device. | 10-30-2008 |
20090080276 | Temperature Dependent Bias for Minimal Stand-by Power in CMOS Circuits - A circuit is disclosed which generates such a bias voltage that when this bias voltage is received by a large plurality of devices of a semiconductor chip, power consumption is reduced in the stand-by mode at any particular operating temperature. The disclosed circuit contains at least one monitor FET, which is kept in its off-state, and which has common properties with the large plurality of FET devices. The temperature dependent leakage current of the monitor FET is sensed, and used to generate the bias voltage in proportion to the leakage current. This bias voltage is received by the large plurality FET devices on their gate electrodes, or on their body terminals. | 03-26-2009 |
20090099828 | Device Threshold Calibration Through State Dependent Burnin - Disclosed are embodiments of a design structure for reducing and/or eliminating mismatch. The embodiments sample the bias of one or more circuit sub-components that require a balanced state (e.g., sampling the bias of the cross-coupled transistors in each memory cell and/or sense amp in a memory array) before chip burn-in, by initiating a burn-in process during which an individually selected state is applied to each of the devices in the circuit. This fatigues the devices away from their preferred states and towards a balanced state. The bias is periodically reassessed during the burn-in process to avoid over-correction. By using this method both memory cell and sense-amplifier mismatch can be reduced in memory arrays, resulting in smaller timing uncertainty and therefore faster memories. | 04-16-2009 |
20090129181 | SYSTEM AND METHOD FOR IMPLEMENTING ROW REDUNDANCY WITH REDUCED ACCESS TIME AND REDUCED DEVICE AREA - A system for implementing row redundancy in integrated circuit memory devices includes one or more main subarrays having word line, bit line and memory cell devices, each of the one or more main subarrays including a set of support circuitry associated therewith. A discrete, redundant subarray is associated with the main subarrays, and also includes a set of support circuitry associated therewith. A common global bit line is shared by the main subarrays and the redundant subarray, and redundancy steering control circuitry is associated with the main subarrays and the redundant subarray. The redundancy steering control circuitry is configured such that word line activation of the main subarrays and the redundant subarray is performed in parallel with address compare operations performed by the redundancy steering control circuitry. | 05-21-2009 |
20090129192 | DESIGN STRUCTURE FOR LOW OVERHEAD SWITCHED HEADER POWER SAVINGS APPARATUS - A design structure embodied in a machine readable medium used in a design process includes a tri-state power gating apparatus for reducing leakage current in a memory array. The apparatus includes a first distributed header device coupled to the memory array, the first distributed header device is configured for limiting leakage current through the memory array; and a header driver operatively coupled to the first distributed header device for enabling tri-state operation of the first distributed header device, wherein tri-state operation includes sleep mode, wake mode, and retention mode. | 05-21-2009 |
20090141538 | Voltage Controlled Static Random Access Memory - A static random access memory (SRAM) comprising a plurality of SRAM cells, a plurality of wordlines (WL | 06-04-2009 |
20090153228 | STRUCTURE FOR IMPROVING FUSE STATE DETECTION AND YIELD IN SEMICONDUCTOR APPLICATIONS - Disclosed is a design structure of an apparatus incorporating a detection circuit adapted for determining the state of selected fuses and a programming circuit for blowing selected fuses on demand. Also, disclosed are embodiments of an associated method. The detection circuit comprises a plurality of fuses in identical signal and reference legs in order to increase the signal margin for detecting blown fuses and/or current sources configured to pass offset currents through the signal and reference legs in order to set the trip point for detecting blown fuses between the un-blown and the minimum blown resistances. Thus, the invention provides the flexibility of single-sided fuse state detection devices with even greater sensitivity than both single-sided and differential fuse state detection device. | 06-18-2009 |
20090207650 | SYSTEM AND METHOD FOR INTEGRATING DYNAMIC LEAKAGE REDUCTION WITH WRITE-ASSISTED SRAM ARCHITECTURE - A system for integrating dynamic leakage reduction with a write-assisted SRAM architecture includes power line selection circuitry associated with each column of one or more SRAM sub arrays, controlled by a selection signal that selects the associated sub array for a read or write operation, and by a column write signal that selects one of the columns of the sub arrays. The power line selection circuitry locally converts a first voltage, corresponding to a cell supply voltage for a read operation, to a second lower voltage to be supplied to each cell selected for a write operation, as to facilitate a write function. The power line selection circuitry also locally converts the first voltage to a third voltage to be supplied to power lines in unselected sub arrays, the third voltage also being lower than the first voltage so as to facilitate dynamic leakage reduction. | 08-20-2009 |
20090235171 | APPARATUS AND METHOD FOR IMPLEMENTING WRITE ASSIST FOR STATIC RANDOM ACCESS MEMORY ARRAYS - An apparatus for implementing a write assist for a memory array includes a common discharge node configured to provide a discharge path for precharged write data lines and bit lines selected during a write operation of the memory array; negative boost circuitry configured to introduce a voltage lower than a nominal logic low supply voltage onto the common discharge node following the discharge of the common discharge node, write data lines and bit lines; and a clamping device coupled to the common discharge node, the clamping device configured to limit the magnitude of negative voltage applied to common discharge node by the negative boost circuitry so as to prevent activation of non-selected bit switches. | 09-17-2009 |
20100002495 | Column Selectable Self-Biasing Virtual Voltages for SRAM Write Assist - A static random access memory decoder circuit includes a first cell supply line coupled to provide a first column of memory cells a first cell supply voltage and a second cell supply line coupled to provide a first column of memory cells a first cell supply voltage. The decoder circuit further includes a write assist circuit having a first threshold transistor coupled to the first cell supply line and a second threshold transistor coupled to the second cell supply line. In response to a write assist signal, the write assist circuit connects one of the first and second cell supply lines selected by control circuitry to an associated one of the first and second threshold transistors, such that a cell supply voltage of the selected one of the first and second cell supply lines is reduced toward the threshold voltage of the threshold transistor. | 01-07-2010 |
20110085390 | WORD-LINE LEVEL SHIFT CIRCUIT - A dual word-line level shifter circuit and associated SRAM. A circuit is disclosed that includes a first transistor gated by a data input at the lower voltage, and a second transistor gated by a restore input at the higher voltage, wherein the first and second transistors are coupled along a series path to a source at the higher voltage; a control node along the series path; an output node coupled to the control node via a first pair of parallel transistors; and a feedback circuit having a second pair of parallel transistors and a feedback transistor, wherein the feedback transistor couples the second pair of parallel transistors to the control node and is gated by the output node. | 04-14-2011 |
20110090750 | SRAM DELAY CIRCUIT THAT TRACKS BITCELL CHARACTERISTICS - An SRAM delay circuit that tracks bitcell characteristics. A circuit is disclosed that includes an input node for receiving an input signal; a reference node for capturing a reference current from a plurality of reference cells; a capacitance network having a discharge that is controlled by the reference current; and an output circuit that outputs the input signal with a delay, wherein the delay is controlled by the discharge of the capacitance network. | 04-21-2011 |
20110164463 | Structure and Method for Decoding Read Data-Bus With Column-Steering Redundancy - A random access memory circuit enabling a decodable sense amplifier array for power saving with column steering redundancy. A first decoder receives an input address and accesses at least one memory cell in the array and is capable of executing column steering redundancy. A master redundancy signal is triggered when column steering redundancy is requested. A plurality of sense amplifiers, wherein, each sense amplifier in the plurality of sense amplifiers is coupled to at least one memory cell in an array of memory cells. A second decoder receives the input address and selectively activates a first set of sense amplifiers of the plurality of sense amplifiers and selectively activates a second set of sense amplifiers in the plurality of amplifier only when the master redundancy signal is activated. | 07-07-2011 |
20110280088 | SINGLE SUPPLY SUB VDD BITLINE PRECHARGE SRAM AND METHOD FOR LEVEL SHIFTING - A reduced bitline precharge level has been found to increase the SRAM Beta ratio, thus improving the stability margin. The precharge level is also supplied to Sense amplifier, write driver, and source voltages for control signals. In the sense amplifier, the lower precharge voltage compensates for performance loss in the bit-cell by operating global data-line drivers with increased overdrive. In the write driver, the reduced voltage improves the Bitline discharge rate, improves the efficiency of the negative boost write assist, and decreases the reliability exposure of transistors in the write path from negative boost circuit. | 11-17-2011 |
20120075918 | SRAM Having Wordline Up-Level Voltage Adjustable to Assist Bitcell Stability and Design Structure for Same - An integrated circuit that includes memory containing wordlines and bitcells having SRAM storage elements and being connected to the wordlines. Wordline up-level assist circuitry is provided that is designed and configured to provide a plurality of selectable voltage values that can be selected to provide the wordline up-level voltage that is provided to the bitcells during a memory read cycle and/or write cycle. In one example, the voltage value selected is selected based on characterization of the as-fabricated bitcells so as to decrease the likelihood of the bitcells experiencing a stability failure. | 03-29-2012 |
20120075919 | Methods and Systems for Adjusting Wordline Up-Level Voltage to Improve Production Yield Relative to SRAM-Cell Stability - Methods of setting wordline up-level voltage in as-fabricated SRAM. In one example, the method includes determining the relative speed, or strength, of 1) the combination of the pass-gate and pull-down devices and 2) the pull-up devices in the bitcells of the SRAM. These relative strengths are then used to adjust the wordline up-level voltage, if needed, to decrease the likelihood of the SRAM experiencing a stability failure. Corresponding systems are provided for determining the relative strengths of the devices of interest, for determining the amount of up-level voltage adjustment needed, and for selecting and setting the up-level voltage. | 03-29-2012 |
20120134221 | WORD-LINE LEVEL SHIFT CIRCUIT - A dual word-line level shifter circuit and associated SRAM. A circuit is disclosed that includes a first transistor gated by a data input at the lower voltage, and a second transistor gated by a restore input at the higher voltage, wherein the first and second transistors are coupled along a series path to a source at the higher voltage; a control node along the series path; an output node coupled to the control node via a first pair of parallel transistors; and a feedback circuit having a second pair of parallel transistors and a feedback transistor, wherein the feedback transistor couples the second pair of parallel transistors to the control node and is gated by the output node. | 05-31-2012 |
20120140551 | STATIC RANDOM ACCESS MEMORY (SRAM) WRITE ASSIST CIRCUIT WITH LEAKAGE SUPPRESSION AND LEVEL CONTROL - A static random access memory (SRAM) write assist circuit with leakage suppression and level control is described. In one embodiment, the SRAM write assist circuit increases the amount of boost provided in a write cycle, while in another embodiment, the SRAM write assist circuit limits the amount of boost provided at higher supply voltages. | 06-07-2012 |
20130033948 | DEVICE AND METHOD FOR DETECTING RESISTIVE DEFECT - The invention provides a device and method for detecting a resistive defect in a static random access memory (SRAM) device. A first aspect of the invention provides a static random access memory (SRAM) device comprising: a bitline; a wordline; a bitline precharge circuit electrically connected to the bitline and adapted to provide to the bitline a first precharge voltage for precharging the bitline during normal operation of the SRAM device and a second precharge voltage less than the first precharge voltage for testing the SRAM device for a resistive defect between the bitline and the wordline. | 02-07-2013 |
20130135944 | DUAL POWER SUPPLY MEMORY ARRAY HAVING A CONTROL CIRCUIT THAT DYANMICALLY SELECTS A LOWER OF TWO SUPPLY VOLTAGES FOR BITLINE PRE-CHARGE OPERATIONS AND AN ASSOCIATED METHOD - Disclosed is a memory array in which the lower of two supply voltages from two power supplies is dynamically selected for bitline pre-charge operations. In the memory array, a voltage comparator compares the first supply voltage on a first power supply rail to a second supply voltage on a second power supply rail and outputs a voltage difference signal. If the voltage difference signal has a first value indicating that the first supply voltage is equal to or less than the second supply voltage, than a control circuit ensures that the complementary bitlines connected to a memory cell are pre-charged to the first supply voltage. If the voltage difference signal has a second value indicating that the first supply voltage is greater than the second supply voltage, then the control circuit ensures that the complementary bitlines are pre-charged to the second supply voltage. Also disclosed is an associated method. | 05-30-2013 |
20130148455 | FINE GRANULARITY POWER GATING - An approach for providing fine granularity power gating of a memory array is described. In one embodiment, power supply lines are disposed in a horizontal dimension of the memory array parallel to the word lines that access cells arranged in rows and columns of the array, wherein each of the supply lines are shared by adjacent cells in the memory. Power supply lines that activate a row selected by one of the word lines are supplied a full-power voltage value and power supply lines that activate rows adjacent to the selected row are supplied a half-power voltage value, while the power supply lines of the remaining rows in the memory array are supplied a power-gated voltage value. | 06-13-2013 |
20130223161 | VDIFF MAX LIMITER IN SRAMS FOR IMPROVED YIELD AND POWER - An integrated circuit structure comprises a static random access memory (SRAM) structure and a logic circuit. A power supply is operatively connected to the SRAM structure, and provides a first voltage to the SRAM structure. A voltage limiter is operatively connected to the power supply. The voltage limiter comprises a switching device operatively connected to the power supply. The switching device receives the first voltage and a second voltage supplied to structures external to the SRAM structure. A resistive element is operatively connected to the switching device. The switching device connects the resistive element to the power supply. The resistive element is selected to enable an output from the switching device to the logic circuit when a difference between the first voltage and the second voltage is greater than a voltage threshold value of the switching device. | 08-29-2013 |
20140092700 | FINE GRANULARITY POWER GATING - Rows of a memory array are segmented into a predetermined number of word line groups. Each row in a word line group has a word line disposed between parallel power supply lines. Each of the power supply lines in a row of a word line group is shared by an adjacent row in the word line group. A row on a boundary of a word line group has a power supply line shared by a row on a boundary of an adjacent word line group. All power supply lines in a word line group are at a full power voltage in response to one of the rows in the word line group being selected by a word line. Most power supply lines in an adjacent word line group are at a full power voltage. All power supply lines in other word line groups are at a power-gated voltage. | 04-03-2014 |