Patent application number | Description | Published |
20080219061 | APPARATUS AND METHOD FOR DETECTING LEAKAGE CURRENT OF SEMICONDUCTOR MEMORY DEVICE, AND INTERNAL VOLTAGE GENERATING CIRCUIT USING THE SAME - A semiconductor memory device is capable of generating a back bias voltage based on a target level changed according to a leakage current of the semiconductor memory devices, thereby minimizing the amount of the leakage current. The semiconductor memory device includes a leakage current detector and a back bias voltage generator. The leakage current detector is configured to detect a leakage current of a cell array. The back bias voltage generator is configured to generate a back bias voltage having a target level changed according to the leakage current. | 09-11-2008 |
20080284496 | INTERNAL VOLTAGE GENERATION CIRCUIT FOR SEMICONDUCTOR DEVICE AND METHOD FOR GENERATING INTERNAL VOLTAGE THEREIN - An internal voltage generation circuit of a semiconductor device includes: a voltage detecting unit configured to detect a voltage level of an internal voltage output terminal to output a voltage detection signal; an oscillating unit configured to generate a first oscillation signal having a predefined frequency in response to the voltage detection signal; and a pumping unit configured to perform a charge pumping operation in response to the first oscillation signal and the voltage detection signal to output an internal voltage to the internal voltage output terminal, a period of the charge pumping operation being limited within an activation period of the voltage detection signal. | 11-20-2008 |
20080304335 | Semiconductor memory device including apparatus for detecting threshold voltage - A semiconductor device including a threshold voltage detector and a boosted voltage generating unit. The threshold voltage detector detects a threshold voltage level of cell transistors and outputs a detected threshold voltage level. The boosted voltage generating unit changes a target level of a boosted voltage in response to the detected threshold voltage level. The threshold voltage detector includes a detected current generating unit and a detected voltage generating unit. The detected current generating unit has a plurality of cell transistors in a cell array and generates a detected current whose amplitude varies corresponding to an average level of the threshold voltages of the cell transistors. The detected voltage generating unit generates the detected threshold voltage level whose level is determined corresponding to the amplitude of the detected current. | 12-11-2008 |
20090066410 | CORE VOLTAGE GENERATOR - Core voltage generator including a comparison unit configured to compare a reference voltage with a feedback core voltage to output a difference between the reference voltage and the feedback core voltage, an amplification unit configured to output a core voltage by amplifying an external power supply voltage according to an output signal of the comparison unit and a mute unit configured to maintain a voltage level of an output terminal of the amplification unit at a ground voltage level when the output of the core voltage is interrupted. | 03-12-2009 |
20100165761 | SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR DRIVING THE SAME - A semiconductor memory device includes: a modulation controller for generating a modulation control signal for controlling a frequency modulation operation; a delay locked loop (DLL) circuit for performing a delay locking operation to generate first and second DLL clocks and outputting a frequency-modulated DLL clock in response to the modulation control signal; and a data strobe signal generator for outputting the frequency-modulated DLL clock as a data strobe signal. | 07-01-2010 |
20100165762 | SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR DRIVING THE SAME - A semiconductor memory device includes: a modulation controller for generating a modulation control signal for controlling a frequency modulation operation; a delay locked loop (DLL) circuit for performing a delay locking operation to generate first and second DLL clocks and outputting a frequency-modulated DLL clock in response to the modulation control signal; and a data strobe signal generator for outputting the frequency-modulated DLL clock as a data strobe signal. | 07-01-2010 |