Copeland, CA
Chris Copeland, Calgary CA
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20150369025 | DIRECT STEAM GENERATOR DEGASSING - Systems and methods generate steam mixed with desired non-condensable gas concentrations using a direct steam generator. Injecting the steam into a reservoir may facilitate recovering hydrocarbons from the reservoir. Cooling an output of the direct steam generator produces water condensate, which is then separated from the non-condensable gas, such as carbon dioxide. Reducing pressure of the condensate subsequently heated by cross-exchange with effluent of the direct steam generator regenerates the steam with the carbon dioxide removed for the injection. | 12-24-2015 |
Christopher R. Copeland, Calgary CA
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20140166263 | BRINE BASED INDIRECT STEAM BOILER - Systems and methods generate steam in hydrocarbon recovery operations and may further enable emulsion separation and product upgrading. The methods rely on indirect boiling of water by contact with a thermal transfer liquid heated to a temperature sufficient to vaporize the water. Examples of the liquid include oils, recovered hydrocarbons, liquid metals and brine. Heating of the liquid may utilize circulation of the liquid across or through a furnace, heat exchangers, or a gas-liquid contactor supplied with hot gas. Further, a solvent for bitumen introduced into the water may also vaporize upon contact with the thermal transfer liquid. | 06-19-2014 |
20140166281 | LIQUID INDIRECT STEAM BOILER - Systems and methods generate steam in hydrocarbon recovery operations and may further enable emulsion separation and product upgrading. The methods rely on indirect boiling of water by contact with a thermal transfer liquid heated to a temperature sufficient to vaporize the water. Examples of the liquid include oils, recovered hydrocarbons, liquid metals and brine. Heating of the liquid may utilize circulation of the liquid across or through a furnace, heat exchangers, or a gas-liquid contactor supplied with hot gas. Further, a solvent for bitumen introduced into the water may also vaporize upon contact with the thermal transfer liquid. | 06-19-2014 |
Madison M. Copeland, Calgary CA
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20090275120 | EXTRACTION OF CO2 GAS FROM ENGINE EXHAUST - A photo-bioreactor is used for extraction of carbon dioxide from exhaust gases of an engine used for compression of natural gas by providing a series of vessels and in each contacting the gases with a labyrinthine flow of water containing photo-synthetic organisms. Each vessel receives the gases in series and is controlled to manage the temperature and dwell time to take into account the reducing CO | 11-05-2009 |
20110020915 | Extraction of CO2 Gas - A photo-bioreactor is used for extraction of carbon dioxide from exhaust gases of an engine used for compression of natural gas by providing a series of vessels and in each contacting the gases with a labyrinthine flow of water containing photo-synthetic organisms. Each vessel receives the gases in series and is controlled to manage the temperature and dwell time to take into account the reducing CO | 01-27-2011 |
20110020916 | Extraction of CO2 Gas - A photo-bioreactor is used for extraction of carbon dioxide from exhaust gases of an engine used for compression of natural gas by providing a series of vessels and in each contacting the gases with a labyrinthine flow of water containing photo-synthetic organisms. Each vessel receives the gases in series and is controlled to manage the temperature and dwell time to take into account the reducing CO | 01-27-2011 |
Reid Copeland, Richmond Hill CA
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20110113223 | BRANCH TARGET BUFFER FOR EMULATION ENVIRONMENTS - Branch instructions are managed in an emulation environment that is executing a program. A plurality of entries is populated in a branch target buffer that resides within an emulated environment in which the program is executing. Each of the entries comprises an instruction address and a target address of a branch instruction of the program. When an indirect branch instruction of the program is encountered a processor analyzes one of the entries in the branch target buffer to determine if the instruction address of the one entry is associated with a target address of the indirect branch instruction. If the instruction address of the one entry is associated with the target address of the indirect branch instruction a branch to the target address of the one entry is performed. | 05-12-2011 |
20140059331 | BRANCH TARGET BUFFER FOR EMULATION ENVIRONMENTS - Branch instructions are managed in an emulation environment that is executing a program. A plurality of entries is populated in a branch target buffer that resides within an emulated environment in which the program is executing. Each of the entries comprises an instruction address and a target address of a branch instruction of the program. When an indirect branch instruction of the program is encountered a processor analyzes one of the entries in the branch target buffer to determine if the instruction address of the one entry is associated with a target address of the indirect branch instruction. If the instruction address of the one entry is associated with the target address of the indirect branch instruction a branch to the target address of the one entry is performed. | 02-27-2014 |
20140059332 | BRANCH TARGET BUFFER FOR EMULATION ENVIRONMENTS - Branch instructions are managed in an emulation environment that is executing a program. A plurality of slots in a Polymorphic Inline Cache is populated. A plurality of entries is populated in a branch target buffer residing within an emulated environment in which the program is executing. When an indirect branch instruction associated with the program is encountered, a target address associated with the instruction is identified from the indirect branch instruction. At least one address in each of the slots of the Polymorphic Inline Cache is compared to the target address associated with the indirect branch instruction. If none of the addresses in the slots of the Polymorphic Inline Cache matches the target address associated with the indirect branch instruction, the branch target buffer is searched to identify one of the entries in the branch target buffer that is associated with the target address of the indirect branch instruction. | 02-27-2014 |
Reid Copeland, Markham CA
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20110112820 | Reusing Invalidated Traces in a System Emulator - Native code corresponding to an invalidated trace is re-used in a system emulator. A first trace is identified. A dropped second trace is identified. The dropped second trace is associated with a first native code for emulating the second trace. If the identified first trace corresponds to the dropped second trace, the first native code is associated to the first trace, and the first native code is executed. If the identified first trace does not correspond to the dropped second trace, a second native code for emulating the first trace is created, the second native code is associated with the first trace, and the second native code is executed. | 05-12-2011 |
Reid T Copeland, Toronto CA
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20140136179 | Page Mapped Spatially Aware Emulation of Computer Instruction Set - Dynamic creation of a spatially aware emulation environment comprising Host cells of Host pages corresponding to Guest cells of Guest pages of Guest instructions. Each Host cell comprises a semantic routine for emulating a corresponding Guest instruction located at the corresponding Guest cell of the guest page. | 05-15-2014 |
Reid T. Copeland, Markham CA
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20090125893 | METHOD AND APPARATUS FOR MANAGING VARIABLE ASSIGNMENTS IN A PROGRAM - The illustrative embodiments described herein provide a computer-implemented method, apparatus, and computer program product for managing variable assignments in a program. The process identifies a set of variable assignments that is live on a portion of paths to form a set of identified variable assignments. Each of the set of identified variable assignments assign a value to at least one variable of a set of variables. The process determines a set of program points at which the set of identified variable assignments is live on all paths. The process also moves the set of identified variable assignments to the set of program points in response to determining that the set of identified variable assignments is movable to the set of program points. | 05-14-2009 |
20110071813 | Page Mapped Spatially Aware Emulation of a Computer Instruction Set - Dynamic creation of a spatially aware emulation environment comprising Host cells of Host pages corresponding to Guest cells of Guest pages of Guest instructions. Each Host cell comprises a semantic routine for emulating a corresponding Guest instruction located at the corresponding Guest cell of the guest page. | 03-24-2011 |
20110071814 | Self Initialized Host Cell Spatially Aware Emulation of a Computer Instruction Set - A plurality of Guest cells of Guest instructions are provided with corresponding Host cells for emulating Guest instructions, each Guest instruction having a Guest cell corresponding to a Host cell. Each of the Host cells are initialized with an initialization routine for discovering a corresponding semantic routine for emulating the Guest instruction. When an instruction is to be emulated for the first time, the initialization routine patches itself with the discovered semantic routine such that subsequent emulation of the Guest instruction can be directly performed | 03-24-2011 |
20110071815 | Host Cell Spatially Aware Emulation of a Guest Wild Branch - A instructions of a Guest program to be emulated by a Host computer occupy one or more Guest cells of Guest memory, each Guest cell having a corresponding Host cell in Host memory. The emulator selects a Host cell for emulating a Guest instruction. When the Host cell corresponds to a Guest cell other than a cell aligned with the beginning of the Guest instruction, a wild branch handling routine is executed. | 03-24-2011 |
20110071816 | Just In Time Compiler in Spatially Aware Emulation of a Guest Computer Instruction Set - A selected group of Guest machine instructions in an emulation environment are translated to a semantic routine of Host machine instructions, wherein Guest cells corresponding to an opcode portion of a Guest instruction are mapped to corresponding Host cells, wherein the semantic routine of Host machine instructions are patched into a Host cell corresponding to the first Guest cell of the group of Guest machine instructions, wherein other Host cells of the corresponding Host cells are patched with semantic routines for emulating single instructions associated with the corresponding Guest cell. | 03-24-2011 |
20110202729 | EXECUTING ATOMIC STORE DISJOINT INSTRUCTIONS - A disjoint instruction for accessing operands in memory while executing in a processor of a plurality of processes interrogates a state indicator settable by other processors to determine if the disjoint instruction accessed the operands without an intervening store operation from another processor to the operand. A condition code is set based on the state indicator. | 08-18-2011 |
20130173891 | CONVERT FROM ZONED FORMAT TO DECIMAL FLOATING POINT FORMAT - Machine instructions, referred to herein as a long Convert from Zoned instruction (CDZT) and extended Convert from Zoned instruction (CXZT), are provided that read EBCDIC or ASCII data from memory, convert it to the appropriate decimal floating point format, and write it to a target floating point register or floating point register pair. Further, machine instructions, referred to herein as a long Convert to Zoned instruction (CZDT) and extended Convert to Zoned instruction (CZXT), are provided that convert a decimal floating point (DFP) operand in a source floating point register or floating point register pair to EBCDIC or ASCII data and store it to a target memory location. | 07-04-2013 |
20130173892 | CONVERT TO ZONED FORMAT FROM DECIMAL FLOATING POINT FORMAT - Machine instructions, referred to herein as a long Convert from Zoned instruction (CDZT) and extended Convert from Zoned instruction (CXZT), are provided that read EBCDIC or ASCII data from memory, convert it to the appropriate decimal floating point format, and write it to a target floating point register or floating point register pair. Further, machine instructions, referred to herein as a long Convert to Zoned instruction (CZDT) and extended Convert to Zoned instruction (CZXT), are provided that convert a decimal floating point (DFP) operand in a source floating point register or floating point register pair to EBCDIC or ASCII data and store it to a target memory location. | 07-04-2013 |
20130231913 | Self Initialized Host Cell Spatially Aware Emulation of a Computer Instruction Set - A plurality of Guest cells of Guest instructions are provided with corresponding Host cells for emulating Guest instructions, each Guest instruction having a Guest cell corresponding to a Host cell. Each of the Host cells are initialized with an initialization routine for discovering a corresponding semantic routine for emulating the Guest instruction. When an instruction is to be emulated for the first time, the initialization routine patches itself with the discovered semantic routine such that subsequent emulation of the Guest instruction can be directly performed | 09-05-2013 |
20140331210 | INSERTING IMPLICIT SEQUENCE POINTS INTO COMPUTER PROGRAM CODE TO SUPPORT DEBUG OPERATIONS - Arrangements described herein relate to inserting implicit sequence points into computer program code to support debug operations. Optimization of the computer program code can be performed during compilation of the computer program code and, during the optimization, implicit sequence points can be inserted into the computer program code. The implicit sequence points can be configured to provide virtual reads of symbols contained in the computer program code when the implicit sequence points are reached during execution of the computer program code during a debug operation performed on the computer program code after the computer program code is optimized and compiled. | 11-06-2014 |
20140331215 | INSERTING IMPLICIT SEQUENCE POINTS INTO COMPUTER PROGRAM CODE TO SUPPORT DEBUG OPERATIONS - Arrangements described herein relate to inserting implicit sequence points into computer program code to support debug operations. Optimization of the computer program code can be performed during compilation of the computer program code and, during the optimization, implicit sequence points can be inserted into the computer program code. The implicit sequence points can be configured to provide virtual reads of symbols contained in the computer program code when the implicit sequence points are reached during execution of the computer program code during a debug operation performed on the computer program code after the computer program code is optimized and compiled. | 11-06-2014 |
20150089205 | CONVERT FROM ZONED FORMAT TO DECIMAL FLOATING POINT FORMAT - Machine instructions, referred to herein as a long Convert from Zoned instruction (CDZT) and extended Convert from Zoned instruction (CXZT), are provided that read EBCDIC or ASCII data from memory, convert it to the appropriate decimal floating point format, and write it to a target floating point register or floating point register pair. Further, machine instructions, referred to herein as a long Convert to Zoned instruction (CZDT) and extended Convert to Zoned instruction (CZXT), are provided that convert a decimal floating point (DFP) operand in a source floating point register or floating point register pair to EBCDIC or ASCII data and store it to a target memory location. | 03-26-2015 |
20150089206 | CONVERT TO ZONED FORMAT FROM DECIMAL FLOATING POINT FORMAT - Machine instructions, referred to herein as a long Convert from Zoned instruction (CDZT) and extended Convert from Zoned instruction (CXZT), are provided that read EBCDIC or ASCII data from memory, convert it to the appropriate decimal floating point format, and write it to a target floating point register or floating point register pair. Further, machine instructions, referred to herein as a long Convert to Zoned instruction (CZDT) and extended Convert to Zoned instruction (CZXT), are provided that convert a decimal floating point (DFP) operand in a source floating point register or floating point register pair to EBCDIC or ASCII data and store it to a target memory location. | 03-26-2015 |
Rick Copeland, Beuna Vista Sk CA
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20150218947 | METHOD OF OPERATING A ROCK BOLTING MACHINE - A method of installing a rock bolt is provided. A bolt hole can be formed by applying an insertion force to a drill rod and while the insertion force is being applied, applying a rotational force on the drill rod to rotate the drill rod and bore the bolt hole. A rock bolt can then be installed in the bolt hole by applying an insertion force to the rock bolt to insert the rock bolt into a bolt hole and while the insertion force is applied to the rock bolt, applying a rotational force on the rock bolt to rotate the rock bolt in the bolt hole. As the rotational force being applied to the rock bolt increases, the insertion force applied to the rock bolt can be decreased until no insertion force is being applied and the rock bolt has been torqued to a desired torque amount. | 08-06-2015 |
Sean Copeland, Delta CA
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20080265020 | System and method for performing payment transactions, verifying age, verifying identity, and managing taxes - Age authentication and management of taxes for a merchant. The merchant can verify the age of a customer based on the customer's use of a smartcard that is obtained from a validation authority. The smartcard may contain a certificate related to the age of the user. By utilizing the smartcard, the user can go to an online, virtual, or brick-and-mortar merchant and buy goods requiring age restrictions. When the customer proceeds to purchase a good or service requiring age verification, the merchant's application can obtain information from the smartcard and request from the validation authority information authenticating the user's age. Further, the validation authority may also remit and pay taxes on behalf of the merchant based on the location of the merchant and other information stored in a merchant profile. | 10-30-2008 |
Simon A.r. Copeland, Langley CA
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20130001456 | GATE VALVE - A gate valve for controlling the flow of pressurized fluid having a dynamically-energized seal between a seat ring and a valve body. The dynamically-energized seal may be located in an annular groove defined in a flange sealing face of the seat ring to seal against an annular shoulder sealing face of the valve body. A plurality of fasteners may bring the flange sealing face of the seat ring to a mechanical stop against the shoulder sealing face of the valve body and dynamically energize the dynamically-energized seal. An obturator may engage and disengage the seat ring to control flow through the gate valve. | 01-03-2013 |
Todd Copeland, Ilberton CA
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20080223066 | FREEZING RECEPTACLE AND APPARATUS - Various embodiments for a freezing receptacle and apparatus are described. The freezing receptacle includes a freezing box with a thermal agent that serves to freeze or cool an object or maintain the temperature of the object. The freezing receptacle includes at least one side wall having a sloped inner face that slopes inwards to ensure that the thermal agent remains in thermal contact with the object continuously as the thermal agent changes size and at least one side wall with a vertical face or an outer face that slopes outwards. | 09-18-2008 |
William Copeland, Victoria CA
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20080226110 | MICROPHONE SHIELD SYSTEM - A microphone shield system captures sound in adverse conditions. The system includes a microphone positioned within a membrane. The membrane is inflated around the microphone to form an enclosure. The inflated membrane passes signals within a selected frequency range. The membrane may block or attenuate signals above and/or below the frequency range to pass a desired sound with little surrounding interference. | 09-18-2008 |