Patent application number | Description | Published |
20090122651 | Direct wafer bonded 2-D CUMT array - A capacitive micromachined ultrasonic transducer (CMUT) array connected to a separate electronic unit is provided. The CMUT array includes at least two active elements, a ground element at the array end, and a non-active element having isolation trenches disposed between the active and ground elements. The active element includes a doped first silicon layer, a doped second silicon layer, and a first insulating layer disposed there between. A cavity is in the first silicon layer having a cross section that includes vertical portions disposed at each end of a horizontal portion, and the vertical portion spans from the first insulating layer through the first silicon layer such that a portion of the first silicon layer is isolated by the first insulating layer and the cavity. A membrane layer on the first silicon layer spans the cavity. A bottom electrode is disposed on the bottom of the second silicon layer. | 05-14-2009 |
20090140357 | High-temperature electrostatic transducers and fabrication method - A high temperature micromachined ultrasonic transducer (HTCMUT) is provided. The HTCMUT includes a silicon on insulator (SOI) substrate having a doped first silicon layer, a doped second silicon layer, and a first insulating layer disposed between the first and second silicon layers. A cavity is disposed in the first silicon layer, where a cross section of the cavity includes a horizontal cavity portion on top of vertical cavity portions disposed at each end of the horizontal cavity portion, and the vertical cavity portion spans from the first insulating layer through the first silicon layer, such that a portion of the first silicon layer is isolated by the first insulating layer and the cavity. A membrane layer is disposed on the first silicon layer top surface, and spans across the cavity. A bottom electrode is disposed on the bottom of the second silicon layer. | 06-04-2009 |
20090142872 | Fabrication of capacitive micromachined ultrasonic transducers by local oxidation - Fabrication methods for capacitive micromachined ultrasonic transducers (CMUTS) with independent and precise gap and post thickness control are provided. The fabrication methods are based on local oxidation or local oxidation of silicon (LOCOS) to grow oxide posts. The process steps enable low surface roughness to be maintained to allow for direct wafer bonding of the membrane. In addition, methods for fabricating a step in a substrate are provided with reduced or minimal over-etch time by utilizing the nonlinearity of oxide growth. The fabrication methods of the present invention produce CMUTs with unmatched uniformity, low parasitic capacitance, and high breakdown voltage. | 06-04-2009 |
20100173437 | Method of fabricating CMUTs that generate low-frequency and high-intensity ultrasound - The present invention provides a method of fabricating low-frequency and high-intensity ultrasound CMUTs that includes using deep reactive ion (DRIE) etching to etch at least one cavity in a first surface of a conductive silicon wafer, growing an insulating layer on at least the first surface of the conductive silicon wafer, bonding a silicon layer of a SOI wafer to the insulating layer, where the SOI wafer includes a handle layer, a buried oxide layer and a conductive silicon layer. The handle layer and the buried oxide layer of the SOI wafer are removed, where the conductive layer of the SOI wafer forms a membrane across at least one cavity, and electrically isolating at least one the membrane across the at least one cavity, where at least one the low-frequency and high-intensity ultrasound CMUT is provided. | 07-08-2010 |
20100225200 | Monolithic integrated CMUTs fabricated by low-temperature wafer bonding - Low temperature wafer bonding (temperature of 450° C. or less) is employed to fabricate CMUTs on a wafer that already includes active electrical devices. The resulting structures are CMUT arrays integrated with active electronics by a low-temperature wafer bonding process. The use of a low-temperature process preserves the electronics during CMUT fabrication. With this approach, it is not necessary to make compromises in the CMUT or electronics designs, as is typical of the sacrificial release fabrication approach. Various disadvantages of sacrificial release, such as low process control, poor design flexibility, low reproducibility, and reduced performance are avoided with the present approach. With this approach, a CMUT array can be provided with per-cell electrodes connected to the substrate integrated circuitry. This enables complete flexibility in electronically assigning the CMUT cells to CMUT array elements. | 09-09-2010 |