Patent application number | Description | Published |
20080253181 | METHOD FOR PROGRAMMING A SEMICONDUCTOR MEMORY DEVICE - A method for programming a semiconductor memory device including such a program sequence as to program target threshold levels constituting multi-level data into multiple memory cells, which are simultaneously selected, wherein the program sequence is controlled to finish programming the multiple memory cells in order of height of the target threshold levels. | 10-16-2008 |
20080291716 | METHOD OF PROGRAMMING A NON-VOLATILE MEMORY DEVICE - A method of programming a non-volatile memory device with memory cells formed of variable resistance elements and disposed between word lines and bit lines, includes: previously charging a selected word line and a selected bit line together with a non-selected word line and a non-selected bit line up to a certain voltage; and further charging the selected word line and the non-selected bit line up to a program voltage higher than the certain voltage and a program-block voltage, respectively, and simultaneously discharging the selected bit line. | 11-27-2008 |
20080291743 | SEMICONDUCTOR STORAGE DEVICE - This disclosure concerns a semiconductor storage device including a bit line; a first capacitor supplying a charge to a cell; a first sense node transmitting a potential corresponding to data of the cell; a first pre-charge part charging the bit line, the first capacitor, and the first sense node; a first latch part latching the data; a first sense part including a first sense transistor connected between a power supply and the first latch part, the gate is connected to the first sense node; and a first clamp part connecting a first node between the first latch part and the first sense transistor to the bit line, wherein the first capacitor supplies the charge to the bit line during detecting, and the first sense part supplies a charge from the power supply to the bit line via the first clamp part in response a potential at the first sense node. | 11-27-2008 |
20090010039 | NON-VOLATILE MEMORY DEVICE - According to one embodiment, a nonvolatile memory device includes: a memory cell array including memory cells each having a variable resistance element for nonvolatilely storing data identified by an electrically rewritable resistance value; a first data latch storing write and erase data to be written on a given group of memory cells of the memory cell array for a write and erase operation; and a second data latch storing reference data for performing a compensation operation of the given group to compensate write and erase disturbance accompanied by the write or erase operation. | 01-08-2009 |
20090052227 | NON-VOLATILE MEMORY DEVICE AND METHOD FOR WRITING DATA THERETO - The present invention provides a method for writing data to a non-volatile memory device having first wirings and second wirings intersecting one another and memory cells arranged at each intersection therebetween, each of the memory cells having a variable resistive element and a rectifying element connected in series. According to the method, the second wirings are charged to a certain voltage not less than a rectifying-element threshold value, prior to a rise in a selected first wiring. Then, a selected first wiring is charged to a voltage required for writing or erasing, after which a selected second wiring is discharged. | 02-26-2009 |
20090122611 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF DRIVING THE SAME - This disclosure concerns a memory including cell blocks, wherein in a first write sequence for writing data to a first cell block, drivers write the data only to memory cells arranged in a form of a checkered flag among the memory cells included in the first cell block, in a second write sequence for writing the data from the first cell block to a second cell block, the drivers write the data to all memory cells connected to a word line selected in the second cell block, and when the data is read from the first cell block or at a time of data verification when data is written to the first cell block, the word line drivers simultaneously apply a read voltage to two adjacent word lines, and the sense amplifiers detects the data in the memory cells connected to the two word lines. | 05-14-2009 |
20090244978 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device comprises a plurality of memory cells connected to a bit line; and a sense amplifier operative to sense the magnitude of cell current flowing via the bit line in a selected memory cell connected to the bit line to determine the value of data stored in the memory cell. The sense amplifier includes a first transistor for precharge operative to supply current in the bit line via a first and a second sense node, a second transistor for charge transfer interposed between the first and second sense nodes, and a third transistor for continuous current supply operative to supply current in the bit line not via the first and second sense nodes. | 10-01-2009 |
20090310422 | NON-VOLATILE SEMICONDUCTOR STORAGE DEVICE - A controller repeats an erase operation, an erase verify operation, and a step-up operation. A first storage unit stores a value of an erase start voltage applied first as an erase voltage when a series of erase operations are executed. A second storage unit stores a value of an erase completion voltage which is an erase voltage when erasure of data is finished in the erase operation and the erase verify operation. A first comparator compares the erase completion voltage with the erase start voltage each time the erase operation is executed. When the first comparator determines that the erase completion voltage is larger than the erase start voltage, a counter counts up a count value. When the count value becomes larger than a predetermined value, a second comparator updates a value of the erase start voltage stored in the first storage unit. | 12-17-2009 |
20090323432 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - A nonvolatile semiconductor memory device includes a memory cell which stores data and which is capable of being rewritten electrically, a bit line which is connected electrically to one end of a current path of the memory cell, a control circuit which carries out a verify operation to check a write result after data is written to the memory cell, and a voltage setting circuit which sets a charging voltage for the bit line in a verify operation and a read operation and makes a charging voltage in a read operation higher than a charging voltage in a verify operation. | 12-31-2009 |
20100037007 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - A nonvolatile semiconductor memory device includes a memory cell array in which memory cells having an electrically rewritable charge accumulation layer are arranged, a data writing/reading circuit that writes/reads data to/from the memory cell array in units of pages, a write state information storage circuit for nonvolatile storage of write state information indicating a data write state to the memory cell array by the data writing/reading circuit, and a control circuit that controls the data writing/reading circuit based on an access page address indicating a page from which data is about to be read by the data writing/reading circuit and write state information stored in the write state information storage circuit. | 02-11-2010 |
20100067283 | SENSE AMPLIFIER - A sense amplifier according to an example of the present invention has first, second, third and fourth FETs with a flip-flop connection. A drain of a fifth FET is connected to a first input node, and its source is connected to a power source node. A drain of a sixth FET is connected to a second input node, and its source is connected to the power source node. A sense operation is started by charging a first output node from the first input node with a first current and by charging a second output node from the second input node with a second current. The fifth and sixth FET are turned on after starting the sense operation. | 03-18-2010 |
20100315878 | SEMICONDUCTOR MEMORY DEVICE INCLUDING MEMORY CELL WITH CHARGE ACCUMULATION LAYER - According to one embodiment, a semiconductor memory device includes a memory cell, a bit line, a sense amplifier, a first MOS transistor, and a current source circuit. The bit line transfers data read from the memory cell and/or data to be written to the memory cell. The sense amplifier charges the bit line during a data read and a data write. The first MOS transistor connects the bit line and the sense amplifier together. The current source circuit supplies a constant current to a gate of the first MOS transistor to charge the gate during a data write and/or a data read. | 12-16-2010 |
20100322011 | SEMICONDUCTOR MEMORY DEVICE WITH MEMORY CELLS HAVING CHARGE ACCUMULATION LAYER - According to one embodiment, a semiconductor memory device includes memory cells, a memory cell array, a word line, a bit line, a source line, a row decoder, a sense amplifier, and a first MOS transistor. The word line is connected to gates of the memory cells. The bit line is electrically connected to drains of the memory cells. The source line is electrically connected to sources of the memory cells. The row decoder selects the word line. The sense amplifier senses and amplifies data read onto the bit line in a read operation. The first MOS transistor is capable of connecting a well region where the memory cells are formed with the source line and is arranged between the row decoder or the sense amplifier and the memory cell array. | 12-23-2010 |
20110103135 | NON-VOLATILE MEMORY DEVICE AND METHOD FOR WRITING DATA THERETO - The present invention provides a method for writing data to a non-volatile memory device having first wirings and second wirings intersecting one another and memory cells arranged at each intersection therebetween, each of the memory cells having a variable resistive element and a rectifying element connected in series. According to the method, the second wirings are charged to a certain voltage not less than a rectifying-element threshold value, prior to a rise in a selected first wiring. Then, a selected first wiring is charged to a voltage required for writing or erasing, after which a selected second wiring is discharged. | 05-05-2011 |
20110103152 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device comprises a plurality of memory cells connected to a bit line; and a sense amplifier operative to sense the magnitude of cell current flowing via the bit line in a selected memory cell connected to the bit line to determine the value of data stored in the memory cell. The sense amplifier includes a first transistor for precharge operative to supply current in the bit line via a first and a second sense node, a second transistor for charge transfer interposed between the first and second sense nodes, and a third transistor for continuous current supply operative to supply current in the bit line not via the first and second sense nodes. | 05-05-2011 |
20110176367 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND OPERATION METHOD THEREOF - A nonvolatile semiconductor memory device according to one embodiment includes: a memory cell array; word lines; bit lines; and a control circuit configured to write multi-value data in the memory cells. The control circuit sets either even-ordinal-number bit lines or odd-ordinal-number bit lines as selected bit lines while setting the other as unselected bit lines; applies a write inhibiting voltage to the unselected bit lines; applies a write voltage to the selected bit lines corresponding to unwritten memory cells to be given one of threshold voltage distributions representing different written states; and applies the write inhibiting voltage to the selected bit lines corresponding to unwritten memory cells to be given any other of the threshold voltage distributions representing the different written states, memory cells already written, and memory cells to be maintained in a threshold voltage distribution representing an erased state, thereby executing a write operation. | 07-21-2011 |
20110305089 | THRESHOLD DETECTING METHOD AND VERIFY METHOD OF MEMORY CELLS - According to one embodiment, a threshold detecting method for detecting threshold values of nonvolatile semiconductor memory cells comprises applying a preset voltage to a word line connected to the memory cells, and performing bit-line sense at two different timings during discharging of one of a bit line connected to the memory cells and a node corresponding to the bit line, while a potential of the word line is kept constant. | 12-15-2011 |
20120063224 | NONVOLATILE SEMICONDUCTOR MEMORY - According to one embodiment, a nonvolatile semiconductor memory includes a source line connected to first and second cell units, a cell-source driver setting the source line on a fixed potential in a programming, a data latch circuit temporary storing program data, a hookup circuit connecting one of the first and second bit lines to the data latch circuit, and connecting the other one of the first and second bit lines to the source line, in the programming, a level detection circuit detecting a potential level of the source line, and a control circuit determining a completion of a charge of the first and second bit lines when the potential level of the source line is larger than a threshold value, and making a charge time of the first and second bit lines variable, in the programming. | 03-15-2012 |
20120069656 | SEMICONDUCTOR STORAGE DEVICE - A memory includes plurality of word lines extending in a first direction, plurality of bit lines extending in a second direction to intersect with the word lines, and a memory cell array including plurality of memory cells connected to the word lines and the bit lines. Plurality of sense amplifiers include detectors configured to detect data transmitted from the memory cells to sense nodes via the corresponding bit lines, and capacitors connected between the sense nodes and a reference potential, respectively, and are provided to be arranged in the second direction from at least a side of one ends of the bit lines. Each of k capacitors corresponding to k detectors, where k is equal to or greater than 2, has a width corresponding to widths of the k detectors, the k capacitors are arranged in the second direction, and the k detectors are arranged in the first direction. | 03-22-2012 |
20120092931 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - According to one embodiment, a nonvolatile semiconductor memory device includes a memory cell array, threshold voltages of memory cells being set lowest in an erase state and sequentially set higher according to data in a program state, a plurality of bit lines connected to the memory cells, a word line connected to the memory cells, and a control circuit. In a case where a first memory cell is programmed to a first threshold voltage that is lowest among threshold voltages in the program state, the control circuit is configured to charge a first bit line connected to the first memory cell to a third voltage between a first voltage applied to a bit line when a memory cell is programmed to a second threshold voltage higher than the first threshold voltage and a second voltage applied to a bit line when a memory cell is inhibited from being programmed. | 04-19-2012 |
20120106282 | PATTERN LAYOUT IN SEMICONDUCTOR DEVICE - According to one embodiment, a semiconductor device having a pattern layout includes a first interconnect pattern and a contact pad. The first interconnect pattern includes lines and spaces which are alternately aligned in a first direction with a predetermined pitch. The contact pad is arranged between the lines in the first interconnect pattern and has a width that is triple the predetermined pitch. An interval between the line in the first interconnect pattern and the contact pad is the predetermined pitch, and the predetermined pitch is 100 nm or below. | 05-03-2012 |
20120243330 | NONVOLATILE SEMICONDUCTOR STORAGE DEVICE - A nonvolatile semiconductor storage device according to an embodiment includes an erase circuit executing an erase sequence, wherein in the erase sequence, the erase circuit executes: an erase operation to change a selection memory cell group to an erased state, after the erase operation, a soft program operation on the selection memory cell group to solve over-erased state, and after the soft program operation, a first soft program verification operation performed on at least one partial selection memory cell group of a first partial selection memory cell group and a second partial selection memory cell group so as to confirm whether the partial selection memory cell group includes a predetermined number of memory cells or more that have threshold values equal to or more than a predetermined first threshold value, and after the first soft program verification operation. | 09-27-2012 |
20130003454 | NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE - A non-volatile semiconductor memory device according to embodiments has a memory cell array and a reading circuit, and, in a reading sequence, the reading circuit executes a prereading operation of supplying a first reading voltage to an adjacent word line and supplying a first reading pass voltage to a selected word line, and after executing the prereading operation, executes a main reading operation of supplying a fixed second reading voltage to the selected word line and supplying a fixed second reading pass voltage to the adjacent word line while sensing a plurality of electrical physical amounts of a target memory cell with different reading conditions. | 01-03-2013 |
20130010541 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - A nonvolatile semiconductor memory device includes a memory cell which stores data and which is capable of being rewritten electrically, a bit line which is connected electrically to one end of a current path of the memory cell, a control circuit which carries out a verify operation to check a write result after data is written to the memory cell, and a voltage setting circuit which sets a charging voltage for the bit line in a verify operation and a read operation and makes a charging voltage in a read operation higher than a charging voltage in a verify operation. | 01-10-2013 |
20140379311 | ESTIMATION SYSTEM, ESTIMATION APPARATUS, AND ESTIMATION METHOD - According to an embodiment, an estimation system estimates the power generation amount of a photovoltaic power generation unit. The estimation system includes a calculation unit and a coefficient optimization unit. The calculation unit calculates the estimated value of the power generation amount from the estimated value of a solar irradiance based on a power generation coefficient that converts the solar irradiance into the power generation amount. The coefficient optimization unit adaptively changes the power generation coefficient. | 12-25-2014 |