Patent application number | Description | Published |
20080218754 | System and method for active optical target detection with polarized receiver - A receiver including an analyzer and a detector coupled to the output of the analyzer. The analyzer selects a polarized component of a return beam for input to the detector. The analyzer may be linear, circular or elliptical. Coupled with a laser adapted to output a polarized beam, the receiver provides an active optical ‘target detector. An arrangement may be included for compensating for rotation and ellipticity in the returned beam. In one embodiment, the arrangement for compensating for rotation of the orientation of linear polarization in the returned beam includes a Faraday rotator positioned between the transmitter and the analyzer. An arrangement is disclosed for varying the rotation in the returned beam using a Faraday rotator until a maximum transmittance is achieved. In an alternative embodiment, the arrangement for compensating for ellipticity in the returned beam includes an electro-optical modulator positioned between the transmitter and the analyzer. In another alternative embodiment, two electro-optical modulators are included to compensate for any change in the polarization state in the returned beam. | 09-11-2008 |
20100149533 | SWITCHABLE IMAGING POLARIMETER AND METHOD - A polarimeter and method of polarizing incoming light includes an optical assembly, a first adjustable circular retarder that rotates the polarization content of incoming light, a polarization beam splitter that receives light from the adjustable circular retarder and polarizing the light into a first portion of light having a first polarization and a second portion of light having a second polarization. The first portion of light is directed to a focal plane and the second portion of light is directed to the optical assembly. The optical assembly is switchable between a polarizing mode of operation in which the first portion of light is viewable at the focal plane in absence of the second portion of light and an imaging mode of operation in which the first portion of light and the second portion of light are viewable at the focal plane. | 06-17-2010 |
20110268453 | OPTICAL TRANSCEIVER BUILT-IN TEST (BIT) - An optical transceiver is provided with a light pipe that intercepts, offsets and redirects a portion of the collimated transmit beam to create a virtual object in the receiver field-of-view to perform the BIT. The light pipe comprises an input face and first reflective surface in the transmitter FOV to intercept a portion of the beam along a first axis and re-direct the beam, a second reflective surface and output face in the receiver FOV that re-directs the portion of the beam along a second axis towards the receiver to create the virtual object in the receiver FOV and an optical channel that guides the redirected portion of the beam from the first reflective surface to the second reflective surface to offset the second axis from the first axis. The same detector used during normal operation of the transceiver is used to perform the BIT, which may include a simple “on/off” test or a radiometry test. The light pipe may be designed with an acceptance FOV that preserves collimation, which facilitates a measurement of alignment error between the transmit beam and receiver. | 11-03-2011 |
20130342921 | NANO-NANO-COMPOSITE OPTICAL CERAMIC LENSES - An optical component, for example a lens, integrally formed of a nano/nano class nanocomposite optical ceramic (NNCOC) material. The constituent nanograin materials of the NNCOC material are selected to tailor the thermal and optical properties of the lens so as to provide a lens with a substantially constant focal length over an operating temperature range and/or an optical system in which the image position does not change appreciably over the operating temperature range. | 12-26-2013 |
Patent application number | Description | Published |
20140264246 | Resistive Memory Cell with Trench-Shaped Bottom Electrode - A resistive memory cell, e.g., CBRAM or ReRAM cell, may include a top electrode an a trench-shaped bottom electrode structure defining a bottom electrode connection and a sidewall extending from a first sidewall region adjacent the bottom electrode connection to a tip region defining a tip surface facing generally away from the bottom electrode connection, and wherein the tip surface facing away from the bottom electrode connection has a tip thickness that is less than a thickness of the first sidewall region adjacent the bottom electrode connection. An electrolyte switching region is arranged between the top electrode and the bottom electrode sidewall tip region to provide a path for the formation of a conductive filament or vacancy chain from the bottom electrode sidewall tip surface of the top electrode, via the electrolyte switching region, when a voltage bias is applied to the resistive memory cell. | 09-18-2014 |
20140264614 | Spacer Enabled Poly Gate - A spacer etching process produces ultra-narrow polysilicon and gate oxides for insulated gates used with insulated gate transistors. Narrow channels are formed using dielectric and spacer film deposition techniques. The spacer film is removed from the dielectric wherein narrow channels are formed therein. Insulating gate oxides are grown on portions of the semiconductor substrate exposed at the bottoms of these narrow channels. Then the narrow channels are filled with polysilicon. The dielectric is removed from the face of the semiconductor substrate, leaving only the very narrow gate oxides and the polysilicon. The very narrow gate oxides and the polysilicon are separated into insulated gates for the insulated gate transistors. | 09-18-2014 |
20140264882 | Forming Fence Conductors Using Spacer Etched Trenches - A spacer etching process produces ultra-narrow conductive lines in a plurality of semiconductor dice. Trenches are formed in a first dielectric then a sacrificial film is deposited onto the first dielectric and the trench surfaces formed therein. Planar sacrificial film is removed from the face of the first dielectric and bottom of the trenches, leaving only sacrificial films on the trench walls. A gap between the sacrificial films on the trench walls is filled in with a second dielectric. A portion of the second dielectric is removed to expose tops of the sacrificial films. The sacrificial films are removed leaving ultra-thin gaps that are filled in with a conductive material. The tops of the conductive material in the gaps are exposed to create “fence conductors.” Portions of the fence conductors and surrounding insulating materials are removed at appropriate locations to produce desired conductor patterns comprising isolated fence conductors. | 09-18-2014 |
20140264886 | Forming Fence Conductors Using Spacer Pattern Transfer - A spacer transfer process produces sub-lithographic patterns of conductive lines in a semiconductor die. A dielectric then a conductive material are deposited onto a face of a semiconductor substrate. A sacrificial dielectric is deposited on the conductive material and portions thereof are removed to form at least one trench comprising walls and a bottom exposing the conductive material. A hard mask is deposited over the sacrificial dielectric including the walls and bottom of the trench. Then the hard mask is removed therefrom except from the walls of the trench. Thereafter, the remaining sacrificial dielectric is removed leaving only the hard mask from the walls of the trench. Then all conductive material not protected by the remaining hard mask is removed. Thereafter, the hard mask is removed exposing a sub-lithographic pattern of fence conductors wherein portions thereof are removed at appropriate locations to produce desired conductor patterns comprising isolated fence conductors. | 09-18-2014 |
20140264891 | FORMING FENCE CONDUCTORS IN AN INTEGRATED CIRCUIT - A spacer etching process produces ultra-narrow conductive lines in a plurality of semiconductor dice. Sub-lithographic patterning of the conductive lines are compatible with existing aluminum and copper backend processing. A first dielectric is deposited onto the semiconductor dice and trenches are formed therein. A conductive film is deposited onto the first dielectric and the trench surfaces. All planar conductive film is removed from the faces of the semiconductor dice and bottoms of the trenches, leaving only conductive films on the trench walls, whereby “fence conductors” are created therefrom. Thereafter the gap between the conductive films on the trench walls are filled in with insulating material. A top portion of the insulated gap fill is thereafter removed to expose the tops of the fence conductors. Portions of the fence conductors and surrounding insulating materials are removed at appropriate locations to produce desired conductor patterns comprising isolated fence conductors. | 09-18-2014 |
20150235895 | Spacer Enabled Active Isolation for an Integrated Circuit Device - A method for forming an active isolation structure in a semiconductor integrated circuit die is disclosed. A first hard mask layer is deposited over a semiconductor substrate. Portions of the first hard mask layer are removed to form at least one trench. A spacer layer is deposited over the first hard mask and extends into each trench to cover exposed portions of the semiconductor substrate surface in each trench. Portions of the spacer layer are removed such that remaining portions define spacer layer walls covering the side walls of each trench. A second hard mask layer is deposited and extends into each trench between opposing spacer layer walls. The spacer layer walls are removed such that remaining portions of the first and second hard mask layers define a mask pattern, which is then transferred to the substrate to form openings in the substrate, which are filled with an isolation material. | 08-20-2015 |
20150236255 | Resistive Memory Cell having a Reduced Conductive Path Area - A method of forming a resistive memory cell, e.g., a CBRAM or ReRAM, may include forming a bottom electrode layer, forming an oxide region of an exposed area of the bottom electrode, removing a region of the bottom electrode layer proximate the oxide region to form a bottom electrode having a pointed tip or edge region, and forming first and second electrolyte regions and first and second top electrodes over the bottom electrode to define distinct first and second memory elements. The first memory element defines a first conductive filament/vacancy chain path from the first portion of the bottom electrode pointed tip region to the first top electrode via the first electrolyte region, and second memory element defines a second conductive filament/vacancy chain path from the second portion of the bottom electrode pointed tip region to the second top electrode via the second electrolyte region. | 08-20-2015 |
20150236256 | Resistive Memory Cell with Sloped Bottom Electrode - A method of forming a resistive memory cell, e.g., a CBRAM or ReRAM cell, may include: forming a plurality of bottom electrode connections, depositing a bottom electrode layer over the bottom electrode connections, performing a first etch to remove portions of the bottom electrode layer such that the remaining bottom electrode layer defines at least one sloped surface, forming an oxidation layer on each sloped surface of the remaining bottom electrode layer, performing a second etch on the remaining bottom electrode layer and oxidation layer on each sloped surface to define at least one upwardly-pointing bottom electrode region above each bottom electrode connection, each upwardly-pointing bottom electrode region defining a bottom electrode tip, and forming an electrolyte region and a top electrode over each bottom electrode tip such that the electrolyte region is arranged between the top electrode and the respective bottom electrode top. | 08-20-2015 |
20150236257 | Resistive Memory Cell with Sloped Bottom Electrode - A method of forming a resistive memory cell, e.g., a CBRAM or ReRAM cell, may include forming a plurality of bottom electrode connections, depositing a bottom electrode layer over the bottom electrode connections, performing an etch to remove portions of the bottom electrode layer to form at least one upwardly-pointing bottom electrode region above the bottom electrode connections, each upwardly-pointing bottom electrode region defining a bottom electrode tip, and forming an electrolyte region and a top electrode over each bottom electrode tip such that the electrolyte region is arranged between the top electrode and the respective bottom electrode top. | 08-20-2015 |
20150236258 | RESISTIVE MEMORY CELL HAVING A REDUCED CONDUCTIVE PATH AREA - A method of forming a resistive memory cell, e.g., a CBRAM or ReRAM, may include forming a bottom electrode layer, oxidizing an exposed region of the bottom electrode layer to form an oxide region, removing a region of the bottom electrode layer proximate the oxide region, thereby forming a bottom electrode having a pointed tip region adjacent the oxide region, and forming an electrolyte region and top electrode over at least a portion of the bottom electrode and oxide region, such that the electrolyte region is arranged between the pointed tip region of the bottom electrode and the top electrode, and provides a path for conductive filament or vacancy chain formation from the pointed tip region of the bottom electrode to the top electrode when a voltage bias is applied to the memory cell. A memory cell and memory cell array formed by such method are also disclosed. | 08-20-2015 |
20150249050 | FORMING FENCE CONDUCTORS USING SPACER ETCHED TRENCHES - A spacer etching process produces ultra-narrow conductive lines in a plurality of semiconductor dice. Trenches are formed in a first dielectric then a sacrificial film is deposited onto the first dielectric and the trench surfaces formed therein. Planar sacrificial film is removed from the face of the first dielectric and bottom of the trenches, leaving only sacrificial films on the trench walls. A gap between the sacrificial films on the trench walls is filled in with a second dielectric. A portion of the second dielectric is removed to expose tops of the sacrificial films. The sacrificial films are removed leaving ultra-thin gaps that are filled in with a conductive material. The tops of the conductive material in the gaps are exposed to create “fence conductors.” Portions of the fence conductors and surrounding insulating materials are removed at appropriate locations to produce desired conductor patterns comprising isolated fence conductors. | 09-03-2015 |