Patent application number | Description | Published |
20080280216 | METHOD OF FORMING A HARD MASK PATTERN IN A SEMICONDUCTOR DEVICE - In a method of forming hard mask patterns in a semiconductor device, an etch mask has a pitch less than a resolution limitation of exposure equipment. The method includes forming first hard mask patterns through an exposure process utilizing photoresist patterns, forming a separation layer on a resulting structure including the first hard mask patterns, forming a second hard mask pattern in a space between the first hard mask patterns, and removing the exposed separation layer. | 11-13-2008 |
20080280232 | METHOD OF FORMING PATTERN OF SEMICONDUCTOR DEVICE - The present invention relates to a method of forming a pattern of a semiconductor device. According to the method in accordance with an aspect of the present invention, a photoresist film is formed on a semiconductor substrate. An exposure process is performed on a plurality of light transparent patterns arranged in tandem and the photoresist film corresponding between the light transparent patterns using a photomask including the light transparent patterns. A photoresist pattern is formed by performing a development process so that an opening portion of a line form is formed in the light transparent patterns and the photoresist film between the light transparent patterns. Accordingly, a uniform line pattern can be formed. | 11-13-2008 |
20080280431 | METHOD OF FABRICATING FLASH MEMORY DEVICE - The present invention relates to a method of fabricating a flash memory device. In a method according to an aspect of the present invention, a first hard mask film is formed over a semiconductor laminate. A plurality of first hard mask patterns are formed by etching an insulating layer for a hard mask. Spacers are formed on top surfaces and sidewalls of the plurality of first hard mask patterns. A second hard mask film is formed over a total surface including the spacers. Second hard mask patterns are formed in spaces between the spacers by performing an etch process so that a top surface of the spacers is exposed. The spacers are removed. Accordingly, gate patterns can be formed by employing hard mask patterns having a pitch of exposure equipment resolutions or less. | 11-13-2008 |
20090121787 | Harmonic quadrature demodulation apparatus and method thereof - Disclosed herein is a harmonic quadrature demodulation apparatus and method. The harmonic quadrature demodulation apparatus includes an input terminal for externally receiving an input focused signal, a harmonic phase estimation unit for estimating a second-order harmonic phase component from the input focused signal, and a harmonic detection unit for detecting a second-order harmonic component from the input focused signal. The second-order harmonic detection unit includes an in-phase component extractor, a quadrature component extractor, a Hilbert transformer, an adder and a low pass filter. The in-phase component extractor extracts an in-phase component of the input focused signal. The quadrature component extractor extracts a quadrature component of the input focused signal. The Hilbert transformer Hilbert-transforms a signal transmitted from the quadrature component extractor. The adder receives an output signal of the in-phase component extractor and an output signal of the Hilbert transformer, and adds the two received signals to each other. The harmonic detection unit outputs the second-order harmonic component of the input focused signal. The present invention can extract the harmonic components of an input signal through a single transmission/reception procedure without limiting the bandwidth of a transmission signal. | 05-14-2009 |
20090124203 | Apparatus and method for extracting second harmonic signal - Disclosed herein is an apparatus and method for extracting a second harmonic signal. The apparatus removes a fundamental frequency signal from a reception signal and then extracting the second harmonic signal. A transmitter generates a transmission signal by modulating a reference signal, and then transmits the transmission signal. A receiver extracts the second harmonic components of the reception signal by demodulating the reception signal received after the transmission signal is reflected by an external media. The transmitter includes a reference signal input unit, a first phase modulation unit, a second phase modulation unit, and a transmission signal output unit. The receiver includes a reception signal input unit, a first output signal generation unit, a second output signal generation unit, and a signal output unit. | 05-14-2009 |
20090250743 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor memory device has side surfaces of neighboring bit lines that do not face each other to reduce a capacitance of a parasitic capacitor formed between adjacent bit lines. The semiconductor memory device includes contact plugs formed on a semiconductor substrate. Each contact plug is disposed between gate patterns. First and second conductive pads extend in different directions and are connected to the contact plugs. First and second pad contact plugs are formed on extended peripheries of the first and second conductive pads, respectively. Each of the first pad contact plugs has a height which differs from a height of each of the second pad contact plugs. First bit lines are connected to the first pad contact plugs, and second bit lines are connected to the second pad contact plugs. | 10-08-2009 |
20120021595 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - A method of manufacturing a semiconductor device includes providing a substrate having junction regions and contact plugs formed thereon. A second insulating layer is formed over a first insulating layer and includes first and second pad holes extending in different directions and exposing the contact plugs. First and second conductive pads are formed in the first and second pad holes, respectively. A third insulating layer is formed and includes dual damascene patterns and pad contact holes. The dual damascene pattern exposes the first conductive pad, and each pad contact hole exposes a second conductive pad. First pad contact plugs and a first bit line are formed in the dual damascene pattern and a second pad contract plug is formed in each pad contact hole. A fourth insulating layer including trenches is formed. Each trench exposes a second pad contact plug. A second bit line is formed in each trench. | 01-26-2012 |
20130078521 | COMPOSITIONS AND METHODS FOR MANUFACTURING A CATHODE FOR A SECONDARY BATTERY - Disclosed are compositions and methods for producing a cathode for a secondary battery, where a fluorophosphate of the formula Li | 03-28-2013 |