Patent application number | Description | Published |
20090142892 | Method of fabricating semiconductor device having thin strained relaxation buffer pattern and related device - A method of fabricating a semiconductor device includes forming a buffer pattern on a substrate, the buffer pattern including germanium, recrystallizing the buffer pattern to form a strained relaxation buffer pattern, and forming a tensile silicon cap on the strained relaxation buffer pattern, the cap being under tensile strain. | 06-04-2009 |
20100240197 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND RELATED FABRICATION METHOD - Embodiments of the invention provide a semiconductor integrated circuit device and a method for fabricating the device. The semiconductor device includes a semiconductor substrate having a cell region and a peripheral region, a cell active region formed in the cell region, and a peripheral active region formed in the peripheral region, wherein the cell active region and the peripheral active region are defined by isolation regions. The semiconductor device further includes a first gate stack formed on the cell active region, a second gate stack formed on the peripheral active region, a cell epitaxial layer formed on an exposed portion of the cell active region, and a peripheral epitaxial layer formed on an exposed portion of the peripheral active region, wherein the height of the peripheral epitaxial layer is greater than the height of the cell epitaxial layer. | 09-23-2010 |
20110076012 | OPTICAL NETWORK TERMINAL AND METHOD FOR DETECTING TRANSMISSION ERROR IN OPTICAL NETWORK TERMINAL - Provided are an optical network terminal (ONT) and a method for the ONT to detect an optical transmission error. The ONT is connected with an optical line termination (OLT) and constituting a passive optical network (PON), and includes an optical transmitter configured to transmit an optical signal to the OLT, an error detector configured to detect an error of the optical transmitter; and a controller configured to transmit an error message to the OLT through the optical transmitter when the error detector detects an error of the optical transmitter. | 03-31-2011 |
20110177671 | METHODS OF FORMING A SEMICONDUCTOR CELL ARRAY REGION, METHOD OF FORMING A SEMICONDUCTOR DEVICE INCLUDING THE SEMICONDUCTOR CELL ARRAY REGION, AND METHOD OF FORMING A SEMICONDUCTOR MODULE INCLUDING THE SEMICONDUCTOR DEVICE - Methods of forming a semiconductor cell array region, a method of forming a semiconductor device including the semiconductor cell array region, and a method of forming a semiconductor module including the semiconductor device are provided, the methods of forming the semiconductor cell array region include preparing a semiconductor plate. A semiconductor layer may be formed over the semiconductor plate. The semiconductor layer may be etched to form semiconductor pillars over the semiconductor plate. | 07-21-2011 |
20110266627 | SEMICONDUCTOR DEVICE - A semiconductor device includes a semiconductor substrate including a plurality of active areas defined by a device isolation layer, a gate line structure crossing the plurality of active areas, a buffer insulation layer on the semiconductor substrate, the buffer insulation layer contacting a portion of a side of the gate line structure, a contact etching stopper layer on the buffer insulation layer, and a contact plug passing through the buffer insulation layer and the contact etching stopper layer to be connected to the plurality of active areas. | 11-03-2011 |
20120058609 | METHODS OF MANUFACTURING SEMICONDUCTOR DEVICES - A method of manufacturing a semiconductor device includes forming first and second gate structures on a substrate in first and second regions, respectively, forming a first capping layer on the substrate by a first high density plasma process, such that the first capping layer covers the first and second gate structures except for sidewalls thereof, removing a portion of the first capping layer in the first region, removing an upper portion of the substrate in the first region using the first gate structure as an etching mask to form a first trench, and forming a first epitaxial layer to fill the first trench. | 03-08-2012 |
20120091469 | Semiconductor Devices Having Shallow Junctions - Semiconductor devices are provided including a substrate having a first surface and a second surface recessed from opposite sides of the first surface, a gate pattern formed on the first surface and having a gate insulating layer and a gate electrode, a carbon-doped silicon buffer layer formed on the second surface, and source and drain regions doped with an n-type dopant or p-type dopant, epitaxially grown on the silicon buffer layer to be elevated from a top surface of the gate insulating layer. | 04-19-2012 |
20120112156 | Non-Volatile Memory Devices Having Resistance Changeable Elements And Related Systems And Methods - A non-volatile memory device may include a first wordline on a substrate, an insulating layer on the first wordline, and a second wordline on the insulating layer so that the insulating layer is between the first and second wordlines. A bit pillar may extend adjacent the first wordline, the insulating layer, and the second wordline in a direction perpendicular with respect to a surface of the substrate, and the bit pillar may be electrically conductive. In addition, a first memory cell may include a first resistance changeable element electrically coupled between the first wordline and the bit pillar, and a second memory cell may include a second resistance changeable element electrically coupled between the second wordline and the bit pillar. Related methods and systems are also discussed. | 05-10-2012 |
20130005096 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A semiconductor device comprises a substrate and first and second stress-generating epitaxial regions on the substrate and spaced apart from each other. A channel region is on the substrate and positioned between the first and second stress-generating epitaxial regions. A gate electrode is on the channel region. The channel region is an epitaxial layer, and the first and second stress-generating epitaxial regions impart a stress on the channel region. | 01-03-2013 |
20140027824 | SEMICONDUCTOR DEVICES (as amended) - In a semiconductor device and a method of manufacturing the same, the semiconductor device includes a gate structure crossing an active region of a silicon substrate. Spacers are provided on both sides of the gate structure, respectively. Silicon patterns fill up recessed portions of the silicon substrate and on both sides of the spacers and has a shape protruding higher than a bottom surface of the gate structure, a lower edge of the protruded portion partially makes contact with a top surface of the isolation region, a first side and a second side of each of the silicon patterns, which are opposite to each other in a channel width direction in the gate structure, are inclined toward an inside of the active region. A highly doped impurity region is provided in the silicon patterns and doped with an N type impurity. The semiconductor device represents superior threshold voltage characteristics. | 01-30-2014 |
20140287564 | Semiconductor Devices Having Shallow Junctions - Semiconductor devices are provided including a substrate having a first surface and a second surface recessed from opposite sides of the first surface, a gate pattern formed on the first surface and having a gate insulating layer and a gate electrode, a carbon-doped silicon buffer layer formed on the second surface, and source and drain regions doped with an n-type dopant or p-type dopant, epitaxially grown on the silicon buffer layer to be elevated from a top surface of the gate insulating layer. | 09-25-2014 |
20140299934 | Semiconductor Device and Method for Fabricating the Same - Provided is a semiconductor device. The semiconductor device includes a fin on a substrate; a gate electrode cross the fin on the substrate; a source/drain formed on at least one of both sides of the gate electrode, and including a first film and a second film; and a stress film arranged between an isolation film on the substrate and the source/drain, and formed on a side surface of the fin. | 10-09-2014 |
20140361313 | SEMICONDUCTOR DEVICES - A method of manufacturing a semiconductor device includes forming first and second gate structures on a substrate in first and second regions, respectively, forming a first capping layer on the substrate by a first high density plasma process, such that the first capping layer covers the first and second gate structures except for sidewalls thereof, removing a portion of the first capping layer in the first region, removing an upper portion of the substrate in the first region using the first gate structure as an etching mask to form a first trench, and forming a first epitaxial layer to fill the first trench. | 12-11-2014 |
20150008452 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A semiconductor device comprises a substrate and first and second stress-generating epitaxial regions on the substrate and spaced apart from each other. A channel region is on the substrate and positioned between the first and second stress-generating epitaxial regions. A gate electrode is on the channel region. The channel region is an epitaxial layer, and the first and second stress-generating epitaxial regions impart a stress on the channel region. | 01-08-2015 |
20150035023 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor device may include first and second fins formed side by side on a substrate, a first elevated doped region formed on the first fin and having a first doping concentration of impurities, a second elevated doped region formed on the second fin, and a first bridge connecting the first elevated doped region and the second elevated doped region to each other. Methods of manufacturing such a semiconductor device are also disclosed. | 02-05-2015 |
20150162332 | SEMICONDUCTOR DEVICES HAVING COMPOSITE SPACERS CONTAINING DIFFERENT DIELECTRIC MATERIALS - An integrated circuit device includes an electrically conductive pattern on a substrate. This electrically conductive pattern may be a gate pattern of a field effect transistor. A first electrically insulating spacer is provided on a sidewall of the electrically conductive pattern. The first electrically insulating spacer includes a first lower spacer and a first upper spacer, which extends on the first lower spacer and has a side surface vertically aligned with a corresponding side surface of the first lower spacer. The first upper spacer has a greater dielectric constant relative to a dielectric constant of the first lower spacer. A pair of parallel channel regions may also be provided, which protrude from a surface of the substrate. The electrically conductive pattern may surround top and side surfaces of the pair of parallel channel regions. | 06-11-2015 |
20150333061 | SEMICONDUCTOR DEVICES HAVING BRIDGE LAYER AND METHODS OF MANUFACTURING THE SAME - A semiconductor device includes a substrate, a first active fin and a second active fin on the substrate, respectively, a plurality of first epitaxial layers on the first active fin and on the second active fin, respectively, a plurality of second epitaxial layers on the plurality of first epitaxial layers, a bridge layer connecting the plurality of second epitaxial layers to each other, and a third epitaxial layer on the bridge layer. | 11-19-2015 |
20160027875 | Semiconductor Devices Having Source/Drain Regions with Strain-Inducing Layers and Methods of Manufacturing Such Semiconductor Devices - Semiconductor devices include a strain-inducing layer capable of applying a strain to a channel region of a transistor included in a miniaturized electronic device, and a method of manufacturing the semiconductor device. The semiconductor device includes a substrate having a channel region; a pair of source/drain regions provided on the substrate and arranged on both sides of the channel region in a first direction; and a gate structure provided on the channel region and comprising a gate electrode pattern extending in a second direction that is different from the first direction, a gate dielectric layer disposed between the channel region and the gate electrode pattern, and a gate spacer covering respective lateral surfaces of the gate electrode pattern and the gate dielectric layer. At least one of the source/drain regions includes a first strain-inducing layer and a second strain-inducing layer. The first strain-inducing layer is disposed between a lateral surface of the channel region and the second strain-inducing layer and contacts at least a portion of the gate dielectric layer. | 01-28-2016 |
20160027918 | SEMICONDUCTOR DEVICE - A semiconductor device may include: a semiconductor substrate, a device isolating layer embedded within the semiconductor substrate and defining an active region, a channel region formed in the active region, a gate electrode disposed above the channel region, a gate insulating layer provided between the channel region and the gate electrode, and a silicon germanium epitaxial layer adjacent to the channel region within the active region and including a first epitaxial layer containing a first concentration of germanium, a second epitaxial layer containing a second concentration of germanium, higher than the first concentration, and a third epitaxial layer containing a third concentration of germanium, lower than the second concentration, the first to third epitaxial layers being sequentially stacked on one another in that order. | 01-28-2016 |
20160079367 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor device may have a structure that prevents or reduces an etching amount of certain portions, such as a part of a source/drain region. Adjacent active fins may be merged with a blocking layer extending between adjacent the source/drain region. The blocking layer may be of a material that is relatively high-resistant to the etchant. | 03-17-2016 |
Patent application number | Description | Published |
20080308845 | Heterogeneous Group IV Semiconductor Substrates - Embodiments of the present invention include heterogeneous substrates, integrated circuits formed on such heterogeneous substrates. The heterogeneous substrates according to certain embodiments of the present invention include a first Group IV semiconductor layer (e.g., silicon), a second Group IV pattern (e.g., a silicon-germanium pattern) that includes a plurality of individual elements on the first Group IV semiconductor layer, and a third Group IV semiconductor layer (e.g., a silicon epitaxial layer) on the second Group IV pattern and on a plurality of exposed portions of the first Group IV semiconductor layer. The second Group IV pattern may be removed in embodiments of the present invention. In these and other embodiments of the present invention, the third Group IV semiconductor layer may be planarized. | 12-18-2008 |
20090121268 | Semiconductor Memory Devices Having Vertical Channel Transistors and Related Methods - A semiconductor memory device may include a semiconductor substrate with an active region extending in a first direction parallel with respect to a surface of the semiconductor substrate. A pillar may extend from the active region in a direction perpendicular with respect to the surface of the semiconductor substrate with the pillar including a channel region on a sidewall thereof. A gate insulating layer may surround a sidewall of the pillar, and a word line may extend in a second direction parallel with respect to the surface of the semiconductor substrate. Moreover, the first and second directions may be different, and the word line may surround the sidewall of the pillar so that the gate insulating layer is between the word line and the pillar. A contact plug may be electrically connected to the active region and spaced apart from the word line, and a bit line may be electrically connected to the active region through the contact plug with the plurality of bit lines extending in the first direction. Related methods are also discussed. | 05-14-2009 |
20100001349 | SEMICONDUCTOR DEVICE - A semiconductor device can include a first gate electrode including a gate insulating pattern, a gate conductive pattern and a capping pattern that are sequentially stacked on a semiconductor substrate, and a first spacer of a low dielectric constant disposed on a lower sidewall of the first gate electrode. A second spacer of a high dielectric constant, that is greater than the low dielectric constant, is disposed on an upper sidewall of the first gate electrode above the first spacer. | 01-07-2010 |
20100041201 | Methods of Fabricating MOS Transistors Having Recesses with Elevated Source/Drain Regions - Methods of fabricating metal-oxide-semiconductor (MOS) transistors having elevated source/drain regions are provided. The MOS transistors formed by these methods may include a gate pattern formed to cross over a predetermined region of a substrate. Recessed regions are provided in the substrate adjacent to the gate pattern. Epitaxial layers are provided on bottom surfaces of the recessed regions. High concentration impurity regions are provided in the epitaxial layers. The recessed regions may be formed using a chemical dry etching techniques. | 02-18-2010 |
20100330753 | METHODS OF MANUFACTURING INTEGRATED CIRCUIT DEVICES INCLUDING A TRANSCRIPTION-PREVENTING PATTERN - Integrated circuit devices are provided including a first single-crystalline layer and an insulating layer pattern on the first single-crystalline layer. The insulating layer pattern has an opening therein that partially exposes the first single-crystalline layer. A seed layer is in the opening. A second single-crystalline layer is on the insulating layer pattern and the seed layer. The second single-crystalline layer has a crystalline structure substantially the same as that of the seed layer. A transcription-preventing pattern is on the second single-crystalline layer and a third single-crystalline layer on the transcription-preventing pattern and the second single-crystalline layer. The transcription-preventing pattern is configured to limit transcription of defective portions in the second single-crystalline layer into the third single-crystalline layer. | 12-30-2010 |
20120034746 | Methods of Fabricating MOS Transistors Having Recesses With Elevated Source/Drain Regions - Methods of fabricating metal-oxide-semiconductor (MOS) transistors having elevated source/drain regions are provided. The MOS transistors formed by these methods may include a gate pattern formed to cross over a predetermined region of a substrate. Recessed regions are provided in the substrate adjacent to the gate pattern. Epitaxial layers are provided on bottom surfaces of the recessed regions. High concentration impurity regions are provided in the epitaxial layers. The recessed regions may be formed using a chemical dry etching techniques. | 02-09-2012 |
20120184079 | METHODS OF MANUFACTURING A SEMICONDUCTOR DEVICE - A semiconductor device can include a first gate electrode including a gate insulating pattern, a gate conductive pattern and a capping pattern that are sequentially stacked on a semiconductor substrate, and a first spacer of a low dielectric constant disposed on a lower sidewall of the first gate electrode. A second spacer of a high dielectric constant, that is greater than the low dielectric constant, is disposed on an upper sidewall of the first gate electrode above the first spacer. | 07-19-2012 |
Patent application number | Description | Published |
20100123801 | DIGITAL IMAGE PROCESSING APPARATUS AND METHOD OF CONTROLLING THE DIGITAL IMAGE PROCESSING APPARATUS - Provided are a digital image processing apparatus capable of detecting faces of people on an input image and obtaining images captured based on different setting values for the faces, and a method of controlling the digital image processing apparatus. The method includes receiving an input image; detecting faces of people in the input image; detecting different skin colors of the faces; setting shooting conditions according to different skin colors of the faces detected on the input image; and capturing images based on the shooting conditions. | 05-20-2010 |
20100157109 | DIGITAL PHOTOGRAPHIC APPARATUS AND METHOD FOR CONTROLLING THE SAME - Provided are a digital photographing apparatus which provides the benefit of distorting an image of an object display on an electronic viewfinder so that the object does not appear to be distorted to a user with astigmatism, and a method of controlling the digital photographing apparatus. The digital photographing apparatus includes an image capture device configured to generate data from light incident to an object to generate preview images of the object; and an electronic viewfinder configured to display preview images, wherein the digital photographing apparatus is configured to distort the preview image to correct for the vision of a user and to control the electronic viewfinder to display the distorted preview image. | 06-24-2010 |
20100220225 | DIGITAL PHOTOGRAPHING APPARATUS, METHOD OF CONTROLLING THE SAME, AND RECORDING MEDIUM STORING PROGRAM TO IMPLEMENT THE METHOD - Provided are a digital photographing apparatus, and associated method and recording medium with method instructions, by which smear generation during moving picture photographing or moving picture display is effectively reduced. The digital photographing apparatus includes an imaging device having an effective area that generates first image data from incident light and an optical black area that is disposed outside the effective area and extends horizontally; a first smear correction unit that corrects the first image data generated by the effective area by using smear data generated by the optical black area, thereby acquiring second image data corresponding to a second frame image comprising less smear than a first frame image corresponding to the first image data; a unit corrects the second image data thereby acquiring third image data. | 09-02-2010 |
20110134290 | PHOTOGRAPHING APPARATUS AND SMEAR CORRECTION METHOD THEREOF - A photographing apparatus including an imaging device configured to obtain a first image of a subject captured with a long shutter exposure time and a second image of the subject captured by setting a short shutter exposure time, wherein the long exposure time is greater than the short exposure time; and a live-view generation unit configured to generate a smear-corrected third image by subtracting pixel values of the second image from the corresponding pixel values of the first image. A smear correction method of a photographing apparatus, the method including capturing a first image of a subject by setting a long electrical shutter exposure time; capturing a second image of a subject by setting a short electrical shutter exposure time; and generating a smear-corrected third image by subtracting pixel values of the second images from the corresponding pixel values of the first image. | 06-09-2011 |
20120113279 | DIGITAL PHOTOGRAPHING APPARATUS AND CONTROL METHOD - A digital photographing apparatus such as a digital camera, having a retractable body tube containing a lens assembly, and a method of controlling the same. The digital camera receives an ongoing series of images, analyzes differences between images to determine an abnormal camera condition such as dropping the camera, and automatically retracts the body tube into the camera to protect it from impact. | 05-10-2012 |